Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
226574 |
0 |
0 |
T1 |
8845559 |
813 |
0 |
0 |
T2 |
6550498 |
138 |
0 |
0 |
T3 |
3276828 |
140 |
0 |
0 |
T6 |
10570848 |
140 |
0 |
0 |
T7 |
6714989 |
807 |
0 |
0 |
T8 |
3843192 |
624 |
0 |
0 |
T9 |
1795637 |
132 |
0 |
0 |
T10 |
0 |
29 |
0 |
0 |
T11 |
0 |
80 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T23 |
1700441 |
0 |
0 |
0 |
T24 |
22568417 |
4224 |
0 |
0 |
T25 |
6780955 |
8448 |
0 |
0 |
T33 |
0 |
16 |
0 |
0 |
T34 |
0 |
10 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
229033 |
0 |
0 |
T1 |
9898971 |
815 |
0 |
0 |
T2 |
7341002 |
138 |
0 |
0 |
T3 |
3670532 |
140 |
0 |
0 |
T6 |
11846512 |
140 |
0 |
0 |
T7 |
7514681 |
807 |
0 |
0 |
T8 |
4271208 |
661 |
0 |
0 |
T9 |
2009633 |
132 |
0 |
0 |
T10 |
0 |
102 |
0 |
0 |
T11 |
0 |
16 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T23 |
1902949 |
0 |
0 |
0 |
T24 |
25236613 |
4224 |
0 |
0 |
T25 |
7474895 |
8448 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1883 |
0 |
0 |
T1 |
2213 |
10 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
8 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1944 |
0 |
0 |
T1 |
265566 |
10 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
8 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1917 |
0 |
0 |
T1 |
265566 |
10 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
8 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1917 |
0 |
0 |
T1 |
2213 |
10 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
8 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
950 |
0 |
0 |
T1 |
2213 |
13 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
15 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1012 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
15 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
982 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
15 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
982 |
0 |
0 |
T1 |
2213 |
13 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
15 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
948 |
0 |
0 |
T1 |
2213 |
11 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
11 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1013 |
0 |
0 |
T1 |
265566 |
11 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
985 |
0 |
0 |
T1 |
265566 |
11 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
985 |
0 |
0 |
T1 |
2213 |
11 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
11 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
959 |
0 |
0 |
T1 |
2213 |
11 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
17 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1022 |
0 |
0 |
T1 |
265566 |
11 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
17 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
995 |
0 |
0 |
T1 |
265566 |
11 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
17 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
995 |
0 |
0 |
T1 |
2213 |
11 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
17 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
925 |
0 |
0 |
T1 |
2213 |
6 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
7 |
0 |
0 |
T8 |
4458 |
8 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
991 |
0 |
0 |
T1 |
265566 |
6 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
7 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
961 |
0 |
0 |
T1 |
265566 |
6 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
7 |
0 |
0 |
T8 |
111462 |
8 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
961 |
0 |
0 |
T1 |
2213 |
6 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
7 |
0 |
0 |
T8 |
4458 |
8 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
485 |
0 |
0 |
T1 |
2213 |
9 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
12 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
0 |
0 |
0 |
T25 |
15085 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
550 |
0 |
0 |
T1 |
265566 |
9 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
0 |
0 |
0 |
T25 |
188570 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
973 |
0 |
0 |
T1 |
2213 |
16 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
8 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
0 |
0 |
0 |
T25 |
15085 |
0 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1056 |
0 |
0 |
T1 |
265566 |
16 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
8 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
0 |
0 |
0 |
T25 |
188570 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
3243 |
0 |
0 |
T1 |
2213 |
10 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
13 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
3308 |
0 |
0 |
T1 |
265566 |
10 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
13 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
3281 |
0 |
0 |
T1 |
265566 |
10 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
13 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
3281 |
0 |
0 |
T1 |
2213 |
10 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
13 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
6306 |
0 |
0 |
T1 |
2213 |
4 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
25 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
6373 |
0 |
0 |
T1 |
265566 |
4 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
25 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
6344 |
0 |
0 |
T1 |
265566 |
4 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
25 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
6344 |
0 |
0 |
T1 |
2213 |
4 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
25 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7380 |
0 |
0 |
T1 |
2213 |
12 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
7 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7446 |
0 |
0 |
T1 |
265566 |
12 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
7 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7416 |
0 |
0 |
T1 |
265566 |
12 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
7 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7416 |
0 |
0 |
T1 |
2213 |
12 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
7 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
6184 |
0 |
0 |
T1 |
2213 |
6 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
19 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
6252 |
0 |
0 |
T1 |
265566 |
6 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
19 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
6222 |
0 |
0 |
T1 |
265566 |
6 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
19 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
6222 |
0 |
0 |
T1 |
2213 |
6 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
19 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
991 |
0 |
0 |
T1 |
2213 |
13 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
10 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1058 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
10 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
1 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1031 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
10 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1031 |
0 |
0 |
T1 |
2213 |
13 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
10 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1853 |
0 |
0 |
T1 |
2213 |
12 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
12 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1916 |
0 |
0 |
T1 |
265566 |
12 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
1 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1888 |
0 |
0 |
T1 |
265566 |
12 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1888 |
0 |
0 |
T1 |
2213 |
12 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
12 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1245 |
0 |
0 |
T1 |
2213 |
5 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
7 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1309 |
0 |
0 |
T1 |
265566 |
5 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
7 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
1 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1281 |
0 |
0 |
T1 |
265566 |
5 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
7 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1281 |
0 |
0 |
T1 |
2213 |
5 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
7 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1109 |
0 |
0 |
T1 |
2213 |
19 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
11 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1173 |
0 |
0 |
T1 |
265566 |
19 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1145 |
0 |
0 |
T1 |
265566 |
19 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1145 |
0 |
0 |
T1 |
2213 |
19 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
11 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7055 |
0 |
0 |
T1 |
2213 |
17 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
11 |
0 |
0 |
T8 |
4458 |
8 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7125 |
0 |
0 |
T1 |
265566 |
17 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7096 |
0 |
0 |
T1 |
265566 |
17 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7096 |
0 |
0 |
T1 |
2213 |
17 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
11 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7123 |
0 |
0 |
T1 |
2213 |
13 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
6 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7189 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
6 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7161 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
6 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7161 |
0 |
0 |
T1 |
2213 |
13 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
6 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7081 |
0 |
0 |
T1 |
2213 |
10 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
9 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7147 |
0 |
0 |
T1 |
265566 |
10 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
9 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7118 |
0 |
0 |
T1 |
265566 |
10 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
9 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7118 |
0 |
0 |
T1 |
2213 |
10 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
9 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7063 |
0 |
0 |
T1 |
2213 |
13 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
11 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7125 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7098 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7098 |
0 |
0 |
T1 |
2213 |
13 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
11 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1182 |
0 |
0 |
T1 |
2213 |
8 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
9 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1249 |
0 |
0 |
T1 |
265566 |
8 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
9 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1218 |
0 |
0 |
T1 |
265566 |
8 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
9 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1218 |
0 |
0 |
T1 |
2213 |
8 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
9 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1183 |
0 |
0 |
T1 |
2213 |
17 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
12 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1249 |
0 |
0 |
T1 |
265566 |
17 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1219 |
0 |
0 |
T1 |
265566 |
17 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1219 |
0 |
0 |
T1 |
2213 |
17 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
12 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1165 |
0 |
0 |
T1 |
2213 |
14 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
6 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1228 |
0 |
0 |
T1 |
265566 |
14 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
6 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1201 |
0 |
0 |
T1 |
265566 |
14 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
6 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1201 |
0 |
0 |
T1 |
2213 |
14 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
6 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1170 |
0 |
0 |
T1 |
2213 |
7 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
12 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1234 |
0 |
0 |
T1 |
265566 |
7 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
1 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1206 |
0 |
0 |
T1 |
265566 |
7 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1206 |
0 |
0 |
T1 |
2213 |
7 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
12 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7609 |
0 |
0 |
T1 |
2213 |
6 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
9 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7678 |
0 |
0 |
T1 |
265566 |
6 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
9 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7650 |
0 |
0 |
T1 |
265566 |
6 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
9 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7650 |
0 |
0 |
T1 |
2213 |
6 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
9 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7679 |
0 |
0 |
T1 |
2213 |
10 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
17 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7747 |
0 |
0 |
T1 |
265566 |
10 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
17 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7717 |
0 |
0 |
T1 |
265566 |
10 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
17 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7717 |
0 |
0 |
T1 |
2213 |
10 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
17 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7570 |
0 |
0 |
T1 |
2213 |
13 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
6 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7637 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
6 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7608 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
6 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7608 |
0 |
0 |
T1 |
2213 |
13 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
6 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7598 |
0 |
0 |
T1 |
2213 |
8 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
15 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7663 |
0 |
0 |
T1 |
265566 |
8 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
15 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7636 |
0 |
0 |
T1 |
265566 |
8 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
15 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7636 |
0 |
0 |
T1 |
2213 |
8 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
15 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1742 |
0 |
0 |
T1 |
2213 |
6 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
20 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1812 |
0 |
0 |
T1 |
265566 |
6 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
20 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1781 |
0 |
0 |
T1 |
265566 |
6 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
20 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1781 |
0 |
0 |
T1 |
2213 |
6 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
20 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1696 |
0 |
0 |
T1 |
2213 |
11 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
7 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1767 |
0 |
0 |
T1 |
265566 |
11 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
7 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1734 |
0 |
0 |
T1 |
265566 |
11 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
7 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1734 |
0 |
0 |
T1 |
2213 |
11 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
7 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1712 |
0 |
0 |
T1 |
2213 |
15 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
18 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1779 |
0 |
0 |
T1 |
265566 |
15 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
18 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1750 |
0 |
0 |
T1 |
265566 |
15 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
18 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1750 |
0 |
0 |
T1 |
2213 |
15 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
18 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1690 |
0 |
0 |
T1 |
2213 |
13 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
11 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1762 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1731 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1731 |
0 |
0 |
T1 |
2213 |
13 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
11 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1747 |
0 |
0 |
T1 |
2213 |
24 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
12 |
0 |
0 |
T8 |
4458 |
7 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1813 |
0 |
0 |
T1 |
265566 |
24 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
8 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1787 |
0 |
0 |
T1 |
265566 |
24 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
8 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1787 |
0 |
0 |
T1 |
2213 |
24 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
12 |
0 |
0 |
T8 |
4458 |
8 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T6 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1710 |
0 |
0 |
T1 |
2213 |
7 |
0 |
0 |
T2 |
412 |
1 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
9 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1774 |
0 |
0 |
T1 |
265566 |
7 |
0 |
0 |
T2 |
198038 |
1 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
9 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T6 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1747 |
0 |
0 |
T1 |
265566 |
7 |
0 |
0 |
T2 |
198038 |
1 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
9 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1748 |
0 |
0 |
T1 |
2213 |
7 |
0 |
0 |
T2 |
412 |
1 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
9 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1704 |
0 |
0 |
T1 |
2213 |
19 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
11 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1768 |
0 |
0 |
T1 |
265566 |
19 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1740 |
0 |
0 |
T1 |
265566 |
19 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1740 |
0 |
0 |
T1 |
2213 |
19 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
11 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1708 |
0 |
0 |
T1 |
2213 |
14 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
8 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1777 |
0 |
0 |
T1 |
265566 |
16 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
8 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1747 |
0 |
0 |
T1 |
265566 |
15 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
8 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
1747 |
0 |
0 |
T1 |
2213 |
15 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
8 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
64 |
0 |
0 |
T25 |
15085 |
128 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
902 |
0 |
0 |
T1 |
2213 |
12 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
13 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
0 |
0 |
0 |
T25 |
15085 |
0 |
0 |
0 |
T34 |
0 |
10 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
968 |
0 |
0 |
T1 |
265566 |
12 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
13 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
0 |
0 |
0 |
T25 |
188570 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 28 | 3 | 3 | 100.00 |
CONT_ASSIGN | 46 | 0 | 0 | |
CONT_ASSIGN | 49 | 0 | 0 | |
ALWAYS | 52 | 0 | 0 | |
ALWAYS | 86 | 3 | 3 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
29 |
1 |
1 |
31 |
1 |
1 |
46 |
|
unreachable |
49 |
|
unreachable |
52 |
|
unreachable |
53 |
|
unreachable |
55 |
|
unreachable |
86 |
1 |
1 |
87 |
1 |
1 |
89 |
1 |
1 |
94 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 31
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
28 |
2 |
2 |
100.00 |
IF |
86 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 28 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 86 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
658 |
0 |
0 |
T1 |
2213 |
21 |
0 |
0 |
T2 |
412 |
2 |
0 |
0 |
T3 |
411 |
2 |
0 |
0 |
T6 |
666 |
2 |
0 |
0 |
T7 |
1679 |
12 |
0 |
0 |
T8 |
4458 |
9 |
0 |
0 |
T9 |
431 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T23 |
425 |
0 |
0 |
0 |
T24 |
7940 |
0 |
0 |
0 |
T25 |
15085 |
0 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
725 |
0 |
0 |
T1 |
265566 |
21 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
10 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
0 |
0 |
0 |
T25 |
188570 |
0 |
0 |
0 |