Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1742613 |
0 |
0 |
T1 |
265566 |
4072 |
0 |
0 |
T2 |
198038 |
3542 |
0 |
0 |
T3 |
98837 |
1191 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
3013 |
0 |
0 |
T8 |
111462 |
7763 |
0 |
0 |
T9 |
53930 |
775 |
0 |
0 |
T10 |
0 |
207 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53513 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1917 |
0 |
0 |
T1 |
265566 |
10 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
8 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
868339 |
0 |
0 |
T1 |
265566 |
5365 |
0 |
0 |
T2 |
198038 |
3539 |
0 |
0 |
T3 |
98837 |
1223 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
5843 |
0 |
0 |
T8 |
111462 |
8220 |
0 |
0 |
T9 |
53930 |
780 |
0 |
0 |
T10 |
0 |
639 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53562 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
982 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
15 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
882595 |
0 |
0 |
T1 |
265566 |
4474 |
0 |
0 |
T2 |
198038 |
3599 |
0 |
0 |
T3 |
98837 |
1207 |
0 |
0 |
T6 |
319582 |
3604 |
0 |
0 |
T7 |
201602 |
4236 |
0 |
0 |
T8 |
111462 |
8182 |
0 |
0 |
T9 |
53930 |
733 |
0 |
0 |
T10 |
0 |
935 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19127 |
0 |
0 |
T25 |
188570 |
53446 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
985 |
0 |
0 |
T1 |
265566 |
11 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
867231 |
0 |
0 |
T1 |
265566 |
4498 |
0 |
0 |
T2 |
198038 |
3589 |
0 |
0 |
T3 |
98837 |
1227 |
0 |
0 |
T6 |
319582 |
3756 |
0 |
0 |
T7 |
201602 |
6627 |
0 |
0 |
T8 |
111462 |
7688 |
0 |
0 |
T9 |
53930 |
746 |
0 |
0 |
T10 |
0 |
725 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53549 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
995 |
0 |
0 |
T1 |
265566 |
11 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
17 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 112
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T3,T6 |
1 | - | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
845874 |
0 |
0 |
T1 |
265566 |
2327 |
0 |
0 |
T2 |
198038 |
3642 |
0 |
0 |
T3 |
98837 |
1217 |
0 |
0 |
T6 |
319582 |
3756 |
0 |
0 |
T7 |
201602 |
2521 |
0 |
0 |
T8 |
111462 |
7079 |
0 |
0 |
T9 |
53930 |
715 |
0 |
0 |
T10 |
0 |
633 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19123 |
0 |
0 |
T25 |
188570 |
53396 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
961 |
0 |
0 |
T1 |
265566 |
6 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
7 |
0 |
0 |
T8 |
111462 |
8 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
| Total | Covered | Percent |
Conditions | 16 | 14 | 87.50 |
Logical | 16 | 14 | 87.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 112
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T3 |
1 | - | Covered | T1,T3,T6 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T17,T18,T44 |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T17,T18,T44 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
462376 |
0 |
0 |
T1 |
265566 |
4394 |
0 |
0 |
T2 |
198038 |
3497 |
0 |
0 |
T3 |
98837 |
1401 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
5917 |
0 |
0 |
T8 |
111462 |
8322 |
0 |
0 |
T9 |
53930 |
775 |
0 |
0 |
T10 |
0 |
641 |
0 |
0 |
T11 |
0 |
4124 |
0 |
0 |
T12 |
0 |
4141 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
0 |
0 |
0 |
T25 |
188570 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
524 |
0 |
0 |
T1 |
265566 |
9 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
0 |
0 |
0 |
T25 |
188570 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
| Total | Covered | Percent |
Conditions | 16 | 14 | 87.50 |
Logical | 16 | 14 | 87.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 112
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T3 |
1 | - | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T13,T14,T15 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
936722 |
0 |
0 |
T1 |
265566 |
8426 |
0 |
0 |
T2 |
198038 |
3589 |
0 |
0 |
T3 |
98837 |
1423 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
3799 |
0 |
0 |
T8 |
111462 |
7959 |
0 |
0 |
T9 |
53930 |
752 |
0 |
0 |
T10 |
0 |
854 |
0 |
0 |
T11 |
0 |
4109 |
0 |
0 |
T12 |
0 |
1716 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
0 |
0 |
0 |
T25 |
188570 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1010 |
0 |
0 |
T1 |
265566 |
16 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
8 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
0 |
0 |
0 |
T25 |
188570 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
3128541 |
0 |
0 |
T1 |
265566 |
4087 |
0 |
0 |
T2 |
198038 |
3248 |
0 |
0 |
T3 |
98837 |
1181 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
5042 |
0 |
0 |
T8 |
111462 |
7937 |
0 |
0 |
T9 |
53930 |
713 |
0 |
0 |
T10 |
0 |
787 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53438 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
3281 |
0 |
0 |
T1 |
265566 |
10 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
13 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
5641217 |
0 |
0 |
T1 |
265566 |
1491 |
0 |
0 |
T2 |
198038 |
3662 |
0 |
0 |
T3 |
98837 |
1251 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
9872 |
0 |
0 |
T8 |
111462 |
7927 |
0 |
0 |
T9 |
53930 |
783 |
0 |
0 |
T10 |
0 |
848 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19123 |
0 |
0 |
T25 |
188570 |
53551 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
6344 |
0 |
0 |
T1 |
265566 |
4 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
25 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
6745565 |
0 |
0 |
T1 |
265566 |
5023 |
0 |
0 |
T2 |
198038 |
3548 |
0 |
0 |
T3 |
98837 |
1227 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
2526 |
0 |
0 |
T8 |
111462 |
8486 |
0 |
0 |
T9 |
53930 |
813 |
0 |
0 |
T10 |
0 |
650 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53428 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7416 |
0 |
0 |
T1 |
265566 |
12 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
7 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
5546925 |
0 |
0 |
T1 |
265566 |
2264 |
0 |
0 |
T2 |
198038 |
3530 |
0 |
0 |
T3 |
98837 |
1211 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
7489 |
0 |
0 |
T8 |
111462 |
7948 |
0 |
0 |
T9 |
53930 |
708 |
0 |
0 |
T10 |
0 |
681 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19123 |
0 |
0 |
T25 |
188570 |
53503 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
6222 |
0 |
0 |
T1 |
265566 |
6 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
19 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
903382 |
0 |
0 |
T1 |
265566 |
5376 |
0 |
0 |
T2 |
198038 |
3639 |
0 |
0 |
T3 |
98837 |
1261 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
3827 |
0 |
0 |
T8 |
111462 |
8568 |
0 |
0 |
T9 |
53930 |
426 |
0 |
0 |
T10 |
0 |
762 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53580 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1031 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
10 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1683762 |
0 |
0 |
T1 |
265566 |
5039 |
0 |
0 |
T2 |
198038 |
3539 |
0 |
0 |
T3 |
98837 |
1189 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
4648 |
0 |
0 |
T8 |
111462 |
8336 |
0 |
0 |
T9 |
53930 |
442 |
0 |
0 |
T10 |
0 |
831 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19123 |
0 |
0 |
T25 |
188570 |
53519 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1888 |
0 |
0 |
T1 |
265566 |
12 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1132744 |
0 |
0 |
T1 |
265566 |
1853 |
0 |
0 |
T2 |
198038 |
3808 |
0 |
0 |
T3 |
98837 |
1201 |
0 |
0 |
T6 |
319582 |
3760 |
0 |
0 |
T7 |
201602 |
2470 |
0 |
0 |
T8 |
111462 |
8264 |
0 |
0 |
T9 |
53930 |
484 |
0 |
0 |
T10 |
0 |
869 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53523 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1281 |
0 |
0 |
T1 |
265566 |
5 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
7 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
992932 |
0 |
0 |
T1 |
265566 |
7876 |
0 |
0 |
T2 |
198038 |
3572 |
0 |
0 |
T3 |
98837 |
1153 |
0 |
0 |
T6 |
319582 |
3756 |
0 |
0 |
T7 |
201602 |
4306 |
0 |
0 |
T8 |
111462 |
7816 |
0 |
0 |
T9 |
53930 |
763 |
0 |
0 |
T10 |
0 |
973 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53579 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1145 |
0 |
0 |
T1 |
265566 |
19 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7164037 |
0 |
0 |
T1 |
265566 |
7019 |
0 |
0 |
T2 |
198038 |
3657 |
0 |
0 |
T3 |
98837 |
1199 |
0 |
0 |
T6 |
319582 |
3680 |
0 |
0 |
T7 |
201602 |
4318 |
0 |
0 |
T8 |
111462 |
7459 |
0 |
0 |
T9 |
53930 |
700 |
0 |
0 |
T10 |
0 |
756 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19123 |
0 |
0 |
T25 |
188570 |
53525 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7096 |
0 |
0 |
T1 |
265566 |
17 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7238526 |
0 |
0 |
T1 |
265566 |
5386 |
0 |
0 |
T2 |
198038 |
3621 |
0 |
0 |
T3 |
98837 |
1207 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
2235 |
0 |
0 |
T8 |
111462 |
8416 |
0 |
0 |
T9 |
53930 |
786 |
0 |
0 |
T10 |
0 |
1001 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53616 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7161 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
6 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
6985695 |
0 |
0 |
T1 |
265566 |
4100 |
0 |
0 |
T2 |
198038 |
3484 |
0 |
0 |
T3 |
98837 |
1245 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
3374 |
0 |
0 |
T8 |
111462 |
7898 |
0 |
0 |
T9 |
53930 |
747 |
0 |
0 |
T10 |
0 |
770 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19123 |
0 |
0 |
T25 |
188570 |
53482 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7118 |
0 |
0 |
T1 |
265566 |
10 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
9 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
6951379 |
0 |
0 |
T1 |
265566 |
5519 |
0 |
0 |
T2 |
198038 |
3750 |
0 |
0 |
T3 |
98837 |
1247 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
4249 |
0 |
0 |
T8 |
111462 |
8372 |
0 |
0 |
T9 |
53930 |
746 |
0 |
0 |
T10 |
0 |
848 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53574 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7098 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1104148 |
0 |
0 |
T1 |
265566 |
3140 |
0 |
0 |
T2 |
198038 |
3619 |
0 |
0 |
T3 |
98837 |
1239 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
3381 |
0 |
0 |
T8 |
111462 |
8036 |
0 |
0 |
T9 |
53930 |
757 |
0 |
0 |
T10 |
0 |
862 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53520 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1218 |
0 |
0 |
T1 |
265566 |
8 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
9 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1092082 |
0 |
0 |
T1 |
265566 |
7046 |
0 |
0 |
T2 |
198038 |
3426 |
0 |
0 |
T3 |
98837 |
1173 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
4665 |
0 |
0 |
T8 |
111462 |
7916 |
0 |
0 |
T9 |
53930 |
709 |
0 |
0 |
T10 |
0 |
623 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53490 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1219 |
0 |
0 |
T1 |
265566 |
17 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1075599 |
0 |
0 |
T1 |
265566 |
5841 |
0 |
0 |
T2 |
198038 |
3540 |
0 |
0 |
T3 |
98837 |
1185 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
2165 |
0 |
0 |
T8 |
111462 |
7859 |
0 |
0 |
T9 |
53930 |
816 |
0 |
0 |
T10 |
0 |
714 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53453 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1201 |
0 |
0 |
T1 |
265566 |
14 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
6 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1067320 |
0 |
0 |
T1 |
265566 |
2681 |
0 |
0 |
T2 |
198038 |
3601 |
0 |
0 |
T3 |
98837 |
1385 |
0 |
0 |
T6 |
319582 |
3755 |
0 |
0 |
T7 |
201602 |
4640 |
0 |
0 |
T8 |
111462 |
8024 |
0 |
0 |
T9 |
53930 |
462 |
0 |
0 |
T10 |
0 |
834 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53550 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1206 |
0 |
0 |
T1 |
265566 |
7 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7740150 |
0 |
0 |
T1 |
265566 |
2305 |
0 |
0 |
T2 |
198038 |
3569 |
0 |
0 |
T3 |
98837 |
1175 |
0 |
0 |
T6 |
319582 |
3756 |
0 |
0 |
T7 |
201602 |
3351 |
0 |
0 |
T8 |
111462 |
8338 |
0 |
0 |
T9 |
53930 |
714 |
0 |
0 |
T10 |
0 |
837 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53462 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7650 |
0 |
0 |
T1 |
265566 |
6 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
9 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7831463 |
0 |
0 |
T1 |
265566 |
4036 |
0 |
0 |
T2 |
198038 |
3727 |
0 |
0 |
T3 |
98837 |
1179 |
0 |
0 |
T6 |
319582 |
3830 |
0 |
0 |
T7 |
201602 |
6637 |
0 |
0 |
T8 |
111462 |
8480 |
0 |
0 |
T9 |
53930 |
724 |
0 |
0 |
T10 |
0 |
743 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53541 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7717 |
0 |
0 |
T1 |
265566 |
10 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
17 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7529666 |
0 |
0 |
T1 |
265566 |
5380 |
0 |
0 |
T2 |
198038 |
3433 |
0 |
0 |
T3 |
98837 |
1133 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
2235 |
0 |
0 |
T8 |
111462 |
8136 |
0 |
0 |
T9 |
53930 |
757 |
0 |
0 |
T10 |
0 |
759 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53447 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7608 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
6 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7495070 |
0 |
0 |
T1 |
265566 |
3170 |
0 |
0 |
T2 |
198038 |
3688 |
0 |
0 |
T3 |
98837 |
1257 |
0 |
0 |
T6 |
319582 |
3680 |
0 |
0 |
T7 |
201602 |
5877 |
0 |
0 |
T8 |
111462 |
7876 |
0 |
0 |
T9 |
53930 |
711 |
0 |
0 |
T10 |
0 |
874 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53596 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
7636 |
0 |
0 |
T1 |
265566 |
8 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
15 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1645574 |
0 |
0 |
T1 |
265566 |
2289 |
0 |
0 |
T2 |
198038 |
3517 |
0 |
0 |
T3 |
98837 |
1189 |
0 |
0 |
T6 |
319582 |
3756 |
0 |
0 |
T7 |
201602 |
7800 |
0 |
0 |
T8 |
111462 |
8226 |
0 |
0 |
T9 |
53930 |
667 |
0 |
0 |
T10 |
0 |
608 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53545 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1781 |
0 |
0 |
T1 |
265566 |
6 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
20 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1578148 |
0 |
0 |
T1 |
265566 |
4535 |
0 |
0 |
T2 |
198038 |
3538 |
0 |
0 |
T3 |
98837 |
1167 |
0 |
0 |
T6 |
319582 |
3756 |
0 |
0 |
T7 |
201602 |
2415 |
0 |
0 |
T8 |
111462 |
7995 |
0 |
0 |
T9 |
53930 |
685 |
0 |
0 |
T10 |
0 |
839 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53469 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1734 |
0 |
0 |
T1 |
265566 |
11 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
7 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1603230 |
0 |
0 |
T1 |
265566 |
6209 |
0 |
0 |
T2 |
198038 |
3717 |
0 |
0 |
T3 |
98837 |
1137 |
0 |
0 |
T6 |
319582 |
3831 |
0 |
0 |
T7 |
201602 |
6982 |
0 |
0 |
T8 |
111462 |
8013 |
0 |
0 |
T9 |
53930 |
724 |
0 |
0 |
T10 |
0 |
953 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53530 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1750 |
0 |
0 |
T1 |
265566 |
15 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
18 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1573439 |
0 |
0 |
T1 |
265566 |
5416 |
0 |
0 |
T2 |
198038 |
3537 |
0 |
0 |
T3 |
98837 |
1201 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
4321 |
0 |
0 |
T8 |
111462 |
8113 |
0 |
0 |
T9 |
53930 |
791 |
0 |
0 |
T10 |
0 |
762 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19123 |
0 |
0 |
T25 |
188570 |
53631 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1731 |
0 |
0 |
T1 |
265566 |
13 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1617146 |
0 |
0 |
T1 |
265566 |
9981 |
0 |
0 |
T2 |
198038 |
3569 |
0 |
0 |
T3 |
98837 |
1239 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
4648 |
0 |
0 |
T8 |
111462 |
6872 |
0 |
0 |
T9 |
53930 |
702 |
0 |
0 |
T10 |
0 |
815 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53480 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1787 |
0 |
0 |
T1 |
265566 |
24 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
12 |
0 |
0 |
T8 |
111462 |
8 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1563978 |
0 |
0 |
T1 |
265566 |
2777 |
0 |
0 |
T2 |
198038 |
1862 |
0 |
0 |
T3 |
98837 |
1169 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
3346 |
0 |
0 |
T8 |
111462 |
8313 |
0 |
0 |
T9 |
53930 |
757 |
0 |
0 |
T10 |
0 |
653 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53360 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1748 |
0 |
0 |
T1 |
265566 |
7 |
0 |
0 |
T2 |
198038 |
1 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
9 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1569808 |
0 |
0 |
T1 |
265566 |
7822 |
0 |
0 |
T2 |
198038 |
3571 |
0 |
0 |
T3 |
98837 |
1133 |
0 |
0 |
T6 |
319582 |
3756 |
0 |
0 |
T7 |
201602 |
4304 |
0 |
0 |
T8 |
111462 |
7925 |
0 |
0 |
T9 |
53930 |
702 |
0 |
0 |
T10 |
0 |
684 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19123 |
0 |
0 |
T25 |
188570 |
53469 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1740 |
0 |
0 |
T1 |
265566 |
19 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
11 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1583780 |
0 |
0 |
T1 |
265566 |
6171 |
0 |
0 |
T2 |
198038 |
3793 |
0 |
0 |
T3 |
98837 |
1173 |
0 |
0 |
T6 |
319582 |
3832 |
0 |
0 |
T7 |
201602 |
3000 |
0 |
0 |
T8 |
111462 |
8293 |
0 |
0 |
T9 |
53930 |
840 |
0 |
0 |
T10 |
0 |
746 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
19124 |
0 |
0 |
T25 |
188570 |
53579 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1747 |
0 |
0 |
T1 |
265566 |
15 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
8 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
64 |
0 |
0 |
T25 |
188570 |
128 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T1 |
0 | 1 | Covered | T15,T16,T19 |
1 | 0 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T1 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T15,T16,T19 |
Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T1 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
868605 |
0 |
0 |
T1 |
265566 |
6143 |
0 |
0 |
T2 |
198038 |
3691 |
0 |
0 |
T3 |
98837 |
1487 |
0 |
0 |
T6 |
319582 |
3680 |
0 |
0 |
T7 |
201602 |
6392 |
0 |
0 |
T8 |
111462 |
7883 |
0 |
0 |
T9 |
53930 |
675 |
0 |
0 |
T10 |
0 |
1032 |
0 |
0 |
T11 |
0 |
4055 |
0 |
0 |
T12 |
0 |
4076 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
0 |
0 |
0 |
T25 |
188570 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8025344 |
7185252 |
0 |
0 |
T1 |
2213 |
1413 |
0 |
0 |
T2 |
412 |
12 |
0 |
0 |
T3 |
411 |
11 |
0 |
0 |
T4 |
486 |
86 |
0 |
0 |
T5 |
406 |
6 |
0 |
0 |
T6 |
666 |
266 |
0 |
0 |
T7 |
1679 |
1279 |
0 |
0 |
T8 |
4458 |
58 |
0 |
0 |
T23 |
425 |
25 |
0 |
0 |
T24 |
7940 |
7540 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
938 |
0 |
0 |
T1 |
265566 |
12 |
0 |
0 |
T2 |
198038 |
2 |
0 |
0 |
T3 |
98837 |
2 |
0 |
0 |
T6 |
319582 |
2 |
0 |
0 |
T7 |
201602 |
13 |
0 |
0 |
T8 |
111462 |
9 |
0 |
0 |
T9 |
53930 |
2 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T23 |
51052 |
0 |
0 |
0 |
T24 |
674989 |
0 |
0 |
0 |
T25 |
188570 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1403211215 |
1401429685 |
0 |
0 |
T1 |
265566 |
265429 |
0 |
0 |
T2 |
198038 |
197985 |
0 |
0 |
T3 |
98837 |
98779 |
0 |
0 |
T4 |
24325 |
24252 |
0 |
0 |
T5 |
48690 |
48619 |
0 |
0 |
T6 |
319582 |
319528 |
0 |
0 |
T7 |
201602 |
201542 |
0 |
0 |
T8 |
111462 |
111373 |
0 |
0 |
T23 |
51052 |
50985 |
0 |
0 |
T24 |
674989 |
674889 |
0 |
0 |