Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl_combo
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.15 100.00 92.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_combo 96.15 100.00 92.31



Module Instance : tb.dut.u_sysrst_ctrl_combo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.15 100.00 92.31


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.18 98.76 92.55 100.00 97.00 97.58


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.34 100.00 96.72 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_combo_trigger[0].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect 95.37 97.83 90.48 100.00 95.24 93.33
gen_combo_trigger[0].u_sysrst_ctrl_detect_pre 97.99 100.00 94.74 100.00 95.24 100.00
gen_combo_trigger[1].u_combo_act 92.34 91.67 85.37 100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect 97.71 100.00 95.24 100.00 100.00 93.33
gen_combo_trigger[1].u_sysrst_ctrl_detect_pre 97.99 100.00 94.74 100.00 95.24 100.00
gen_combo_trigger[2].u_combo_act 93.16 91.67 87.80 100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect 95.37 97.83 90.48 100.00 95.24 93.33
gen_combo_trigger[2].u_sysrst_ctrl_detect_pre 97.99 100.00 94.74 100.00 95.24 100.00
gen_combo_trigger[3].u_combo_act 98.37 100.00 95.12 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect 99.05 100.00 95.24 100.00 100.00 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect_pre 97.99 100.00 94.74 100.00 95.24 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl_combo
Line No.TotalCoveredPercent
TOTAL3030100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
56 4 4
68 4 4
72 4 4
94 4 4
108 4 4
113 4 4
153 1 1
156 1 1
157 1 1
160 1 1
165 1 1


Cond Coverage for Module : sysrst_ctrl_combo
TotalCoveredPercent
Conditions524892.31
Logical524892.31
Non-Logical00
Event00

 LINE       72
 EXPRESSION ((in & gen_combo_trigger[0].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT84,T85
1CoveredT16,T17,T18

 LINE       72
 EXPRESSION ((in & gen_combo_trigger[1].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT84,T85
1CoveredT16,T17,T18

 LINE       72
 EXPRESSION ((in & gen_combo_trigger[2].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT84,T85
1CoveredT16,T17,T18

 LINE       72
 EXPRESSION ((in & gen_combo_trigger[3].cfg_in_pre) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT84,T85
1CoveredT16,T17,T18

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[0].cfg_in_sel)) && 
      2  ((gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en) || ((!gen_combo_trigger[0].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT84,T85,T86
11CoveredT17,T21,T22

 LINE       108
 SUB-EXPRESSION ((gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en) || ((!gen_combo_trigger[0].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT84,T85,T86
01CoveredT16,T17,T18
10CoveredT84,T85,T86

 LINE       108
 SUB-EXPRESSION (gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01CoveredT84,T85,T86
10Not Covered
11CoveredT84,T85,T86

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[1].cfg_in_sel)) && 
      2  ((gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en) || ((!gen_combo_trigger[1].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT84,T85
11CoveredT17,T21,T22

 LINE       108
 SUB-EXPRESSION ((gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en) || ((!gen_combo_trigger[1].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT84,T85
01CoveredT16,T17,T18
10CoveredT84,T85

 LINE       108
 SUB-EXPRESSION (gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01CoveredT84,T85
10Not Covered
11CoveredT84,T85

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[2].cfg_in_sel)) && 
      2  ((gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en) || ((!gen_combo_trigger[2].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT84,T85
11CoveredT17,T21,T22

 LINE       108
 SUB-EXPRESSION ((gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en) || ((!gen_combo_trigger[2].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT84,T85
01CoveredT16,T17,T18
10CoveredT84,T85

 LINE       108
 SUB-EXPRESSION (gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01CoveredT84,T85
10Not Covered
11CoveredT84,T85

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[3].cfg_in_sel)) && 
      2  ((gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en) || ((!gen_combo_trigger[3].cfg_combo_pre_en))))
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT84,T85
11CoveredT17,T21,T22

 LINE       108
 SUB-EXPRESSION ((gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en) || ((!gen_combo_trigger[3].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------
-1--2-StatusTests
00CoveredT84,T85
01CoveredT16,T17,T18
10CoveredT84,T85

 LINE       108
 SUB-EXPRESSION (gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------
-1--2-StatusTests
01CoveredT84,T85
10Not Covered
11CoveredT84,T85

 LINE       113
 EXPRESSION ((in & gen_combo_trigger[0].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT17,T21,T22
1CoveredT16,T17,T18

 LINE       113
 EXPRESSION ((in & gen_combo_trigger[1].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT17,T21,T22
1CoveredT16,T17,T18

 LINE       113
 EXPRESSION ((in & gen_combo_trigger[2].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT17,T21,T22
1CoveredT16,T17,T18

 LINE       113
 EXPRESSION ((in & gen_combo_trigger[3].cfg_in_sel) == '0)
            -----------------------1----------------------
-1-StatusTests
0CoveredT17,T21,T22
1CoveredT16,T17,T18
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%