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Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.99 100.00 94.74 100.00 95.24 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.99 100.00 94.74 100.00 95.24 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.05 100.00 95.24 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 92.31 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

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Module Instances:
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Line No.TotalCoveredPercent
TOTAL4343100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
79 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
MISSING_ELSE
205 1 1
206 1 1
209 1 1
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
TotalCoveredPercent
Conditions191894.74
Logical191894.74
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT84,T85
1CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT84,T85

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT84,T85

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT84,T85

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT84,T85
10CoveredT84,T85
11CoveredT84,T85

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT84,T85
01CoveredT84,T85
10CoveredT84,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT84,T85
01CoveredT84,T85
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT84,T85
1-CoveredT84,T85

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T84,T85
DetectSt 168 Covered T84,T85
IdleSt 163 Covered T16,T17,T18
StableSt 191 Covered T84,T85


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T84,T85
DebounceSt->IdleSt 163 Covered T84,T85
DetectSt->IdleSt 186 Covered T84,T85
DetectSt->StableSt 191 Covered T84,T85
IdleSt->DebounceSt 148 Covered T84,T85
StableSt->IdleSt 206 Covered T84,T85



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 92 3 3 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 12 11 91.67
IF 219 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTests
1 - Covered T84,T85
0 1 Covered T84,T85
0 0 Covered T16,T17,T18


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T84,T85
0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
IdleSt 1 - - - - - - Covered T84,T85
IdleSt 0 - - - - - - Covered T84,T85
DebounceSt - 1 - - - - - Covered T84,T85
DebounceSt - 0 1 1 - - - Covered T84,T85
DebounceSt - 0 1 0 - - - Covered T84,T85
DebounceSt - 0 0 - - - - Covered T84,T85
DetectSt - - - - 1 - - Covered T84,T85
DetectSt - - - - 0 1 - Covered T84,T85
DetectSt - - - - 0 0 - Covered T84,T85
StableSt - - - - - - 1 Covered T84,T85
StableSt - - - - - - 0 Covered T84,T85
default - - - - - - - Not Covered


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 2423732 32 0 0
CntIncr_A 2423732 1236 0 0
CntNoWrap_A 2423732 2031933 0 0
DetectStDropOut_A 2423732 2 0 0
DetectedOut_A 2423732 824 0 0
DetectedPulseOut_A 2423732 10 0 0
DisabledIdleSt_A 2423732 2029731 0 0
DisabledNoDetection_A 2423732 2031148 0 0
EnterDebounceSt_A 2423732 18 0 0
EnterDetectSt_A 2423732 14 0 0
EnterStableSt_A 2423732 10 0 0
PulseIsPulse_A 2423732 10 0 0
StayInStableSt 2423732 814 0 0
gen_high_event_sva.HighLevelEvent_A 2423732 2033382 0 0
gen_high_level_sva.HighLevelEvent_A 2423732 2033382 0 0
gen_not_sticky_sva.StableStDropOut_A 2423732 10 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 32 0 0
T35 17445 0 0 0
T84 7721 16 0 0
T85 7721 16 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 1236 0 0
T35 17445 0 0 0
T84 7721 618 0 0
T85 7721 618 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2031933 0 0
T16 1037 636 0 0
T17 17445 15016 0 0
T18 414 13 0 0
T21 17445 15016 0 0
T22 17445 15016 0 0
T23 17445 15016 0 0
T38 8403 2 0 0
T39 627 226 0 0
T40 414 13 0 0
T41 627 226 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2 0 0
T35 17445 0 0 0
T84 7721 1 0 0
T85 7721 1 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 824 0 0
T35 17445 0 0 0
T84 7721 412 0 0
T85 7721 412 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 10 0 0
T35 17445 0 0 0
T84 7721 5 0 0
T85 7721 5 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2029731 0 0
T16 1037 636 0 0
T17 17445 15016 0 0
T18 414 13 0 0
T21 17445 15016 0 0
T22 17445 15016 0 0
T23 17445 15016 0 0
T38 8403 2 0 0
T39 627 226 0 0
T40 414 13 0 0
T41 627 226 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2031148 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 18 0 0
T35 17445 0 0 0
T84 7721 9 0 0
T85 7721 9 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 14 0 0
T35 17445 0 0 0
T84 7721 7 0 0
T85 7721 7 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 10 0 0
T35 17445 0 0 0
T84 7721 5 0 0
T85 7721 5 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 10 0 0
T35 17445 0 0 0
T84 7721 5 0 0
T85 7721 5 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 814 0 0
T35 17445 0 0 0
T84 7721 407 0 0
T85 7721 407 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

gen_high_event_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2033382 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2033382 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 10 0 0
T35 17445 0 0 0
T84 7721 5 0 0
T85 7721 5 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions212095.24
Logical212095.24
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT17,T21,T22
1CoveredT16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT17,T21,T22
10CoveredT16,T17,T18
11CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT17,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT16,T17,T18 VC_COV_UNR
1CoveredT17,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT17,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT17,T21,T22
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT17,T21,T22
01CoveredT84,T85
10CoveredT84,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT17,T21,T22
01CoveredT17,T21,T22
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT17,T21,T22
1-CoveredT17,T21,T22

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T17,T21,T22
DetectSt 168 Covered T17,T21,T22
IdleSt 163 Covered T16,T17,T18
StableSt 191 Covered T17,T21,T22


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T17,T21,T22
DebounceSt->IdleSt 163 Covered T27,T31,T33
DetectSt->IdleSt 186 Covered T84,T85
DetectSt->StableSt 191 Covered T17,T21,T22
IdleSt->DebounceSt 148 Covered T17,T21,T22
StableSt->IdleSt 206 Covered T17,T21,T22



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 21 21 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 11 11 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T17,T21,T22
0 1 Covered T17,T21,T22
0 0 Excluded T16,T17,T18 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T17,T21,T22
0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T17,T21,T22
IdleSt 0 - - - - - - Covered T16,T17,T18
DebounceSt - 1 - - - - - Covered T84,T85
DebounceSt - 0 1 1 - - - Covered T17,T21,T22
DebounceSt - 0 1 0 - - - Covered T27,T31,T33
DebounceSt - 0 0 - - - - Covered T17,T21,T22
DetectSt - - - - 1 - - Covered T84,T85
DetectSt - - - - 0 1 - Covered T17,T21,T22
DetectSt - - - - 0 0 - Covered T17,T21,T22
StableSt - - - - - - 1 Covered T17,T21,T22
StableSt - - - - - - 0 Covered T17,T21,T22
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 2423732 1316 0 0
CntIncr_A 2423732 85828 0 0
CntNoWrap_A 2423732 2030649 0 0
DetectStDropOut_A 2423732 2 0 0
DetectedOut_A 2423732 31354 0 0
DetectedPulseOut_A 2423732 602 0 0
DisabledIdleSt_A 2423732 1557887 0 0
DisabledNoDetection_A 2423732 1558604 0 0
EnterDebounceSt_A 2423732 710 0 0
EnterDetectSt_A 2423732 606 0 0
EnterStableSt_A 2423732 602 0 0
PulseIsPulse_A 2423732 602 0 0
StayInStableSt 2423732 30752 0 0
gen_high_level_sva.HighLevelEvent_A 2423732 2033382 0 0
gen_not_sticky_sva.StableStDropOut_A 2423732 600 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 1316 0 0
T17 17445 8 0 0
T18 414 0 0 0
T21 17445 8 0 0
T22 17445 8 0 0
T23 17445 8 0 0
T27 0 18 0 0
T29 0 8 0 0
T31 0 18 0 0
T33 0 18 0 0
T34 0 18 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 8 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 85828 0 0
T17 17445 368 0 0
T18 414 0 0 0
T21 17445 368 0 0
T22 17445 368 0 0
T23 17445 368 0 0
T27 0 1338 0 0
T29 0 368 0 0
T31 0 1338 0 0
T33 0 1338 0 0
T34 0 1338 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 264 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2030649 0 0
T16 1037 636 0 0
T17 17445 15008 0 0
T18 414 13 0 0
T21 17445 15008 0 0
T22 17445 15008 0 0
T23 17445 15008 0 0
T38 8403 2 0 0
T39 627 226 0 0
T40 414 13 0 0
T41 627 226 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2 0 0
T35 17445 0 0 0
T84 7721 1 0 0
T85 7721 1 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 31354 0 0
T17 17445 278 0 0
T18 414 0 0 0
T21 17445 278 0 0
T22 17445 278 0 0
T23 17445 278 0 0
T27 0 346 0 0
T29 0 278 0 0
T31 0 346 0 0
T33 0 346 0 0
T34 0 346 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 77 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 602 0 0
T17 17445 4 0 0
T18 414 0 0 0
T21 17445 4 0 0
T22 17445 4 0 0
T23 17445 4 0 0
T27 0 8 0 0
T29 0 4 0 0
T31 0 8 0 0
T33 0 8 0 0
T34 0 8 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 1557887 0 0
T16 1037 636 0 0
T17 17445 10617 0 0
T18 414 13 0 0
T21 17445 10617 0 0
T22 17445 10617 0 0
T23 17445 10617 0 0
T38 8403 2 0 0
T39 627 226 0 0
T40 414 13 0 0
T41 627 226 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 1558604 0 0
T16 1037 637 0 0
T17 17445 10621 0 0
T18 414 14 0 0
T21 17445 10621 0 0
T22 17445 10621 0 0
T23 17445 10621 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 710 0 0
T17 17445 4 0 0
T18 414 0 0 0
T21 17445 4 0 0
T22 17445 4 0 0
T23 17445 4 0 0
T27 0 10 0 0
T29 0 4 0 0
T31 0 10 0 0
T33 0 10 0 0
T34 0 10 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 5 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 606 0 0
T17 17445 4 0 0
T18 414 0 0 0
T21 17445 4 0 0
T22 17445 4 0 0
T23 17445 4 0 0
T27 0 8 0 0
T29 0 4 0 0
T31 0 8 0 0
T33 0 8 0 0
T34 0 8 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 3 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 602 0 0
T17 17445 4 0 0
T18 414 0 0 0
T21 17445 4 0 0
T22 17445 4 0 0
T23 17445 4 0 0
T27 0 8 0 0
T29 0 4 0 0
T31 0 8 0 0
T33 0 8 0 0
T34 0 8 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 602 0 0
T17 17445 4 0 0
T18 414 0 0 0
T21 17445 4 0 0
T22 17445 4 0 0
T23 17445 4 0 0
T27 0 8 0 0
T29 0 4 0 0
T31 0 8 0 0
T33 0 8 0 0
T34 0 8 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 30752 0 0
T17 17445 274 0 0
T18 414 0 0 0
T21 17445 274 0 0
T22 17445 274 0 0
T23 17445 274 0 0
T27 0 338 0 0
T29 0 274 0 0
T31 0 338 0 0
T33 0 338 0 0
T34 0 338 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 76 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2033382 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 600 0 0
T17 17445 4 0 0
T18 414 0 0 0
T21 17445 4 0 0
T22 17445 4 0 0
T23 17445 4 0 0
T27 0 8 0 0
T29 0 4 0 0
T31 0 8 0 0
T33 0 8 0 0
T34 0 8 0 0
T35 0 4 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%