Module Definition
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Module : sysrst_ctrl_ulp
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_ulp 87.50 100.00 75.00



Module Instance : tb.dut.u_sysrst_ctrl_ulp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.30 93.48 86.44 83.33 89.66 93.62


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.34 100.00 96.72 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_sysrst_ctrl_detect_ac_present 89.13 93.02 86.67 83.33 88.89 93.75
u_sysrst_ctrl_detect_lid_open 89.81 93.48 88.89 83.33 90.00 93.33
u_sysrst_ctrl_detect_pwrb 89.89 93.48 88.89 83.33 90.00 93.75


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl_ulp
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
90 1 1
94 1 1
99 1 1


Cond Coverage for Module : sysrst_ctrl_ulp
TotalCoveredPercent
Conditions8675.00
Logical8675.00
Non-Logical00
Event00

 LINE       90
 EXPRESSION (pwrb_det_pulse | lid_open_det_pulse | ac_present_det_pulse)
             -------1------   ---------2--------   ----------3---------
-1--2--3-StatusTests
000CoveredT16,T17,T18
001CoveredT16,T19,T20
010CoveredT16,T19,T20
100CoveredT16,T19,T20

 LINE       94
 EXPRESSION (pwrb_det | lid_open_det | ac_present_det)
             ----1---   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT16,T17,T18
001Not Covered
010Not Covered
100CoveredT16,T19,T20
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%