Unified Coverage Report :: Module

Module : sysrst_ctrl_ulp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_ulp	87.50	100.00	75.00

Module Instance : tb.dut.u_sysrst_ctrl_ulp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.30	93.48	86.44		83.33	89.66	93.62

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sysrst_ctrl_detect_ac_present	89.13	93.02	86.67		83.33	88.89	93.75
u_sysrst_ctrl_detect_lid_open	89.81	93.48	88.89		83.33	90.00	93.33
u_sysrst_ctrl_detect_pwrb	89.89	93.48	88.89		83.33	90.00	93.75

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl_ulp

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	99	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
90	1	1
94	1	1
99	1	1

Cond Coverage for Module : sysrst_ctrl_ulp

	Total	Covered	Percent
Conditions	8	6	75.00
Logical	8	6	75.00
Non-Logical	0	0
Event	0	0

 LINE       90
 EXPRESSION (pwrb_det_pulse | lid_open_det_pulse | ac_present_det_pulse)
             -------1------   ---------2--------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T16,T17,T18
0	0	1	Covered	T16,T19,T20
0	1	0	Covered	T16,T19,T20
1	0	0	Covered	T16,T19,T20

 LINE       94
 EXPRESSION (pwrb_det | lid_open_det | ac_present_det)
             ----1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T16,T17,T18
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T16,T19,T20