Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T39,T41,T83

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T39,T41,T83

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T39,T41,T83

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T39,T41,T83
1	0	Covered	T16,T17,T18
1	1	Covered	T39,T41,T83

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T39,T41,T83
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T39,T41,T83
0	1	Covered	T39,T41,T83
1	0	Covered	T84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T39,T41,T83
1	-	Covered	T39,T41,T83

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T39,T41,T83
DetectSt	168	Covered	T39,T41,T83
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T39,T41,T83

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T39,T41,T83
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T39,T41,T83
IdleSt->DebounceSt	148	Covered	T39,T41,T83
StableSt->IdleSt	206	Covered	T39,T41,T83

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T39,T41,T83
0	1	Covered	T39,T41,T83
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T39,T41,T83
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T39,T41,T83
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T39,T41,T83
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T39,T41,T83
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T39,T41,T83
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T41,T83
StableSt	-	-	-	-	-	-	0	Covered	T39,T41,T83
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	204	0	0
CntIncr_A	2423732	4090	0	0
CntNoWrap_A	2423732	2031761	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	408	0	0
DetectedPulseOut_A	2423732	102	0	0
DisabledIdleSt_A	2423732	2023105	0	0
DisabledNoDetection_A	2423732	2024522	0	0
EnterDebounceSt_A	2423732	102	0	0
EnterDetectSt_A	2423732	102	0	0
EnterStableSt_A	2423732	102	0	0
PulseIsPulse_A	2423732	102	0	0
StayInStableSt	2423732	306	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	3358	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	100	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	204
T21	17445	0
T22	17445	0
T23	17445	0
T24	817	0
T39	627	4
T40	414	0
T41	627	4
T42	503	0
T83	0	4
T84	0	2
T85	0	2
T87	0	4
T88	0	4
T89	0	4
T90	0	4
T91	0	4
T93	414	0
T94	414	0

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	4090
T21	17445	0
T22	17445	0
T23	17445	0
T24	817	0
T39	627	81
T40	414	0
T41	627	81
T42	503	0
T83	0	81
T84	0	20
T85	0	20
T87	0	81
T88	0	81
T89	0	81
T90	0	81
T91	0	81
T93	414	0
T94	414	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031761
T16	1037	636
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	222
T40	414	13
T41	627	222

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	408
T21	17445	0
T22	17445	0
T23	17445	0
T24	817	0
T39	627	8
T40	414	0
T41	627	8
T42	503	0
T83	0	8
T84	0	4
T85	0	4
T87	0	8
T88	0	8
T89	0	8
T90	0	8
T91	0	8
T93	414	0
T94	414	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	102
T21	17445	0
T22	17445	0
T23	17445	0
T24	817	0
T39	627	2
T40	414	0
T41	627	2
T42	503	0
T83	0	2
T84	0	1
T85	0	1
T87	0	2
T88	0	2
T89	0	2
T90	0	2
T91	0	2
T93	414	0
T94	414	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2023105
T16	1037	636
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	50
T40	414	13
T41	627	50

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2024522
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	51
T40	414	14
T41	627	51

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	102
T21	17445	0
T22	17445	0
T23	17445	0
T24	817	0
T39	627	2
T40	414	0
T41	627	2
T42	503	0
T83	0	2
T84	0	1
T85	0	1
T87	0	2
T88	0	2
T89	0	2
T90	0	2
T91	0	2
T93	414	0
T94	414	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	102
T21	17445	0
T22	17445	0
T23	17445	0
T24	817	0
T39	627	2
T40	414	0
T41	627	2
T42	503	0
T83	0	2
T84	0	1
T85	0	1
T87	0	2
T88	0	2
T89	0	2
T90	0	2
T91	0	2
T93	414	0
T94	414	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	102
T21	17445	0
T22	17445	0
T23	17445	0
T24	817	0
T39	627	2
T40	414	0
T41	627	2
T42	503	0
T83	0	2
T84	0	1
T85	0	1
T87	0	2
T88	0	2
T89	0	2
T90	0	2
T91	0	2
T93	414	0
T94	414	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	102
T21	17445	0
T22	17445	0
T23	17445	0
T24	817	0
T39	627	2
T40	414	0
T41	627	2
T42	503	0
T83	0	2
T84	0	1
T85	0	1
T87	0	2
T88	0	2
T89	0	2
T90	0	2
T91	0	2
T93	414	0
T94	414	0

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	306
T21	17445	0
T22	17445	0
T23	17445	0
T24	817	0
T39	627	6
T40	414	0
T41	627	6
T42	503	0
T83	0	6
T84	0	3
T85	0	3
T87	0	6
T88	0	6
T89	0	6
T90	0	6
T91	0	6
T93	414	0
T94	414	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	2423732	3358
T16	1037	5
T17	17445	22
T18	414	1
T21	17445	22
T22	17445	22
T23	17445	22
T38	8403	0
T39	627	3
T40	414	1
T41	627	3
T42	0	7

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	2423732	100
T21	17445	0
T22	17445	0
T23	17445	0
T24	817	0
T39	627	2
T40	414	0
T41	627	2
T42	503	0
T83	0	2
T87	0	2
T88	0	2
T89	0	2
T90	0	2
T91	0	2
T93	414	0
T94	414	0
T116	0	2
T117	0	2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T16,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T20
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T20
0	1	Unreachable
1	0	Covered	T16,T19,T20

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T19,T20
DetectSt	168	Covered	T16,T19,T20
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T16,T19,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T19,T20
DebounceSt->IdleSt	163	Covered	T84,T85
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T16,T19,T20
IdleSt->DebounceSt	148	Covered	T16,T19,T20
StableSt->IdleSt	206	Covered	T16,T19,T20

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T19,T20
0	1	Covered	T16,T19,T20
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T16,T19,T20
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T19,T20
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T19,T20
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T16,T19,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T19,T20
StableSt	-	-	-	-	-	-	0	Covered	T16,T19,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	2002	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	5500	0	0
DetectedPulseOut_A	2423732	50	0	0
DisabledIdleSt_A	2423732	2018953	0	0
DisabledNoDetection_A	2423732	2020370	0	0
EnterDebounceSt_A	2423732	54	0	0
EnterDetectSt_A	2423732	50	0	0
EnterStableSt_A	2423732	50	0	0
PulseIsPulse_A	2423732	50	0	0
StayInStableSt	2423732	5450	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	3358	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_sticky_sva.StableStDropOut_A	2423732	4750	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	104
T16	1037	2
T17	17445	0
T18	414	0
T19	0	2
T20	0	2
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	2
T36	0	2
T37	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	2
T44	0	2
T84	0	2
T85	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	2002
T16	1037	37
T17	17445	0
T18	414	0
T19	0	37
T20	0	37
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	37
T36	0	37
T37	0	37
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	37
T44	0	37
T84	0	76
T85	0	76

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031861
T16	1037	634
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	5500
T16	1037	110
T17	17445	0
T18	414	0
T19	0	110
T20	0	110
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	110
T36	0	110
T37	0	110
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	110
T44	0	110
T45	0	110
T46	0	110

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	50
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T45	0	1
T46	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2018953
T16	1037	379
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2020370
T16	1037	380
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	54
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T84	0	2
T85	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	50
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T45	0	1
T46	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	50
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T45	0	1
T46	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	50
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T45	0	1
T46	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	5450
T16	1037	109
T17	17445	0
T18	414	0
T19	0	109
T20	0	109
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	109
T36	0	109
T37	0	109
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	109
T44	0	109
T45	0	109
T46	0	109

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	2423732	3358
T16	1037	5
T17	17445	22
T18	414	1
T21	17445	22
T22	17445	22
T23	17445	22
T38	8403	0
T39	627	3
T40	414	1
T41	627	3
T42	0	7

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	2423732	4750
T16	1037	95
T17	17445	0
T18	414	0
T19	0	95
T20	0	95
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	95
T36	0	95
T37	0	95
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	95
T44	0	95
T45	0	95
T46	0	95

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T16,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T20
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T20
0	1	Unreachable
1	0	Covered	T16,T19,T20

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T19,T20
DetectSt	168	Covered	T16,T19,T20
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T16,T19,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T19,T20
DebounceSt->IdleSt	163	Covered	T84,T85
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T16,T19,T20
IdleSt->DebounceSt	148	Covered	T16,T19,T20
StableSt->IdleSt	206	Covered	T16,T19,T20

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T19,T20
0	1	Covered	T16,T19,T20
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T16,T19,T20
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T19,T20
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T19,T20
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T16,T19,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T19,T20
StableSt	-	-	-	-	-	-	0	Covered	T16,T19,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	3600	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	5800	0	0
DetectedPulseOut_A	2423732	50	0	0
DisabledIdleSt_A	2423732	2018953	0	0
DisabledNoDetection_A	2423732	2020370	0	0
EnterDebounceSt_A	2423732	54	0	0
EnterDetectSt_A	2423732	50	0	0
EnterStableSt_A	2423732	50	0	0
PulseIsPulse_A	2423732	50	0	0
StayInStableSt	2423732	5750	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_sticky_sva.StableStDropOut_A	2423732	2600	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	104
T16	1037	2
T17	17445	0
T18	414	0
T19	0	2
T20	0	2
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	2
T36	0	2
T37	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	2
T44	0	2
T84	0	2
T85	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	3600
T16	1037	69
T17	17445	0
T18	414	0
T19	0	69
T20	0	69
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	69
T36	0	69
T37	0	69
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	69
T44	0	69
T84	0	75
T85	0	75

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031861
T16	1037	634
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	5800
T16	1037	116
T17	17445	0
T18	414	0
T19	0	116
T20	0	116
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	116
T36	0	116
T37	0	116
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	116
T44	0	116
T45	0	116
T46	0	116

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	50
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T45	0	1
T46	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2018953
T16	1037	379
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2020370
T16	1037	380
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	54
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T84	0	2
T85	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	50
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T45	0	1
T46	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	50
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T45	0	1
T46	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	50
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T45	0	1
T46	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	5750
T16	1037	115
T17	17445	0
T18	414	0
T19	0	115
T20	0	115
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	115
T36	0	115
T37	0	115
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	115
T44	0	115
T45	0	115
T46	0	115

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	2423732	2600
T16	1037	52
T17	17445	0
T18	414	0
T19	0	52
T20	0	52
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	52
T36	0	52
T37	0	52
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	52
T44	0	52
T45	0	52
T46	0	52

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	40	93.02
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T16,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T20
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T20
0	1	Unreachable
1	0	Covered	T16,T19,T20

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T19,T20
DetectSt	168	Covered	T16,T19,T20
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T16,T19,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T19,T20
DebounceSt->IdleSt	163	Covered	T84,T85
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T16,T19,T20
IdleSt->DebounceSt	148	Covered	T16,T19,T20
StableSt->IdleSt	206	Covered	T16,T19,T20

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	16	88.89
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T19,T20
0	1	Covered	T16,T19,T20
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T16,T19,T20
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T19,T20
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T19,T20
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T16,T19,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T19,T20
StableSt	-	-	-	-	-	-	0	Covered	T16,T19,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	5006	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	5400	0	0
DetectedPulseOut_A	2423732	50	0	0
DisabledIdleSt_A	2423732	2018953	0	0
DisabledNoDetection_A	2423732	2020370	0	0
EnterDebounceSt_A	2423732	54	0	0
EnterDetectSt_A	2423732	50	0	0
EnterStableSt_A	2423732	50	0	0
PulseIsPulse_A	2423732	50	0	0
StayInStableSt	2423732	5350	0	0
gen_high_event_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_sticky_sva.StableStDropOut_A	2423732	2250	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	104
T16	1037	2
T17	17445	0
T18	414	0
T19	0	2
T20	0	2
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	2
T36	0	2
T37	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	2
T44	0	2
T84	0	2
T85	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	5006
T16	1037	97
T17	17445	0
T18	414	0
T19	0	97
T20	0	97
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	97
T36	0	97
T37	0	97
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	97
T44	0	97
T84	0	78
T85	0	78

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031861
T16	1037	634
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	5400
T16	1037	108
T17	17445	0
T18	414	0
T19	0	108
T20	0	108
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	108
T36	0	108
T37	0	108
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	108
T44	0	108
T45	0	108
T46	0	108

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	50
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T45	0	1
T46	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2018953
T16	1037	379
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2020370
T16	1037	380
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	54
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T84	0	2
T85	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	50
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T45	0	1
T46	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	50
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T45	0	1
T46	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	50
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T45	0	1
T46	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	5350
T16	1037	107
T17	17445	0
T18	414	0
T19	0	107
T20	0	107
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	107
T36	0	107
T37	0	107
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	107
T44	0	107
T45	0	107
T46	0	107

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	2423732	2250
T16	1037	45
T17	17445	0
T18	414	0
T19	0	45
T20	0	45
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	45
T36	0	45
T37	0	45
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	45
T44	0	45
T45	0	45
T46	0	45

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T38
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T17,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T21,T22
1	0	Covered	T16,T17,T18
1	1	Covered	T17,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T21,T22
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T21,T22
0	1	Not Covered
1	0	Covered	T84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T21,T22
1	-	Not Covered

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T21,T22
DetectSt	168	Covered	T17,T21,T22
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T17,T21,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T21,T22
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T17,T21,T22
IdleSt->DebounceSt	148	Covered	T17,T21,T22
StableSt->IdleSt	206	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T21,T22
0	1	Covered	T17,T21,T22
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T17,T21,T22
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T21,T22
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T21,T22
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T17,T21,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T84,T85
StableSt	-	-	-	-	-	-	0	Covered	T17,T21,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	4554	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	1858	0	0
DetectedPulseOut_A	2423732	52	0	0
DisabledIdleSt_A	2423732	2020647	0	0
DisabledNoDetection_A	2423732	2022014	0	0
EnterDebounceSt_A	2423732	52	0	0
EnterDetectSt_A	2423732	52	0	0
EnterStableSt_A	2423732	52	0	0
PulseIsPulse_A	2423732	52	0	0
StayInStableSt	2423732	1756	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	0	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	104
T17	17445	2
T18	414	0
T21	17445	2
T22	17445	2
T23	17445	2
T29	0	2
T35	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	2
T112	0	2
T113	0	2
T114	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	4554
T17	17445	90
T18	414	0
T21	17445	90
T22	17445	90
T23	17445	90
T29	0	90
T35	0	90
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	27
T112	0	90
T113	0	90
T114	0	90

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031861
T16	1037	636
T17	17445	15014
T18	414	13
T21	17445	15014
T22	17445	15014
T23	17445	15014
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	1858
T17	17445	37
T18	414	0
T21	17445	37
T22	17445	37
T23	17445	37
T29	0	37
T35	0	37
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	4
T112	0	37
T113	0	37
T114	0	37

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	52
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T29	0	1
T35	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	1
T112	0	1
T113	0	1
T114	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2020647
T16	1037	636
T17	17445	14791
T18	414	13
T21	17445	14791
T22	17445	14791
T23	17445	14791
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2022014
T16	1037	637
T17	17445	14799
T18	414	14
T21	17445	14799
T22	17445	14799
T23	17445	14799
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	52
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T29	0	1
T35	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	1
T112	0	1
T113	0	1
T114	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	52
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T29	0	1
T35	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	1
T112	0	1
T113	0	1
T114	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	52
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T29	0	1
T35	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	1
T112	0	1
T113	0	1
T114	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	52
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T29	0	1
T35	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	1
T112	0	1
T113	0	1
T114	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	1756
T17	17445	35
T18	414	0
T21	17445	35
T22	17445	35
T23	17445	35
T29	0	35
T35	0	35
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	3
T112	0	35
T113	0	35
T114	0	35

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T38
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T84,T85

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T84,T85

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T84,T85

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T84,T85
1	0	Covered	T17,T18,T21
1	1	Covered	T84,T85

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T84,T85
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T84,T85
0	1	Not Covered
1	0	Covered	T84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T84,T85
1	-	Not Covered

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T84,T85
DetectSt	168	Covered	T84,T85
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T84,T85

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T84,T85
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T84,T85
IdleSt->DebounceSt	148	Covered	T84,T85
StableSt->IdleSt	206	Covered	T84,T85

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T84,T85
0	1	Covered	T84,T85
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T84,T85
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T84,T85
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T84,T85
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T84,T85
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T84,T85
StableSt	-	-	-	-	-	-	0	Covered	T84,T85
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	4	0	0
CntIncr_A	2423732	54	0	0
CntNoWrap_A	2423732	2031961	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	6	0	0
DetectedPulseOut_A	2423732	2	0	0
DisabledIdleSt_A	2423732	2031899	0	0
DisabledNoDetection_A	2423732	2033316	0	0
EnterDebounceSt_A	2423732	2	0	0
EnterDetectSt_A	2423732	2	0	0
EnterStableSt_A	2423732	2	0	0
PulseIsPulse_A	2423732	2	0	0
StayInStableSt	2423732	4	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	1806	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	0	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	4
T35	17445	0
T84	7721	2
T85	7721	2
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	54
T35	17445	0
T84	7721	27
T85	7721	27
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031961
T16	1037	636
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	6
T35	17445	0
T84	7721	3
T85	7721	3
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	2
T35	17445	0
T84	7721	1
T85	7721	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2031899
T16	1037	636
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2033316
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	2
T35	17445	0
T84	7721	1
T85	7721	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	2
T35	17445	0
T84	7721	1
T85	7721	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	2
T35	17445	0
T84	7721	1
T85	7721	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	2
T35	17445	0
T84	7721	1
T85	7721	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	4
T35	17445	0
T84	7721	2
T85	7721	2
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	2423732	1806
T17	17445	19
T18	414	1
T21	17445	19
T22	17445	19
T23	17445	19
T24	0	2
T38	8403	0
T39	627	0
T40	414	1
T41	627	0
T42	503	4
T93	0	1
T94	0	1

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.50	100.00	75.00					u_sysrst_ctrl_ulp

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.50	100.00	75.00					u_sysrst_ctrl_ulp

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children