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Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.00 89.13 90.48 66.67 85.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.00 89.13 90.48 66.67 85.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_sysrst_ctrl_autoblock


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.89 93.48 88.89 83.33 90.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.89 93.48 88.89 83.33 90.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.50 100.00 75.00 u_sysrst_ctrl_ulp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.81 93.48 88.89 83.33 90.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.81 93.48 88.89 83.33 90.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.50 100.00 75.00 u_sysrst_ctrl_ulp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.13 93.02 86.67 83.33 88.89 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.13 93.02 86.67 83.33 88.89 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.50 100.00 75.00 u_sysrst_ctrl_ulp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.68 89.13 80.95 66.67 85.00 86.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.68 89.13 80.95 66.67 85.00 86.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.85 89.13 80.95 66.67 85.00 87.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.85 89.13 80.95 66.67 85.00 87.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
TOTAL464189.13
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125322784.38
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 0 1
164 0 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT16,T17,T18
11CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT39,T41,T83

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT16,T17,T18 VC_COV_UNR
1CoveredT39,T41,T83

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT39,T41,T83

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT39,T41,T83
10CoveredT16,T17,T18
11CoveredT39,T41,T83

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT39,T41,T83
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT39,T41,T83
01CoveredT39,T41,T83
10CoveredT84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT39,T41,T83
1-CoveredT39,T41,T83

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 4 66.67
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T39,T41,T83
DetectSt 168 Covered T39,T41,T83
IdleSt 163 Covered T16,T17,T18
StableSt 191 Covered T39,T41,T83


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T39,T41,T83
DebounceSt->IdleSt 163 Not Covered
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T39,T41,T83
IdleSt->DebounceSt 148 Covered T39,T41,T83
StableSt->IdleSt 206 Covered T39,T41,T83



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
Line No.TotalCoveredPercent
Branches 20 17 85.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 7 70.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T39,T41,T83
0 1 Covered T39,T41,T83
0 0 Excluded T16,T17,T18 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T39,T41,T83
0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T39,T41,T83
IdleSt 0 - - - - - - Covered T16,T17,T18
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T39,T41,T83
DebounceSt - 0 1 0 - - - Not Covered
DebounceSt - 0 0 - - - - Covered T39,T41,T83
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T39,T41,T83
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T39,T41,T83
StableSt - - - - - - 0 Covered T39,T41,T83
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 2423732 204 0 0
CntIncr_A 2423732 4090 0 0
CntNoWrap_A 2423732 2031761 0 0
DetectStDropOut_A 2423732 0 0 0
DetectedOut_A 2423732 408 0 0
DetectedPulseOut_A 2423732 102 0 0
DisabledIdleSt_A 2423732 2023105 0 0
DisabledNoDetection_A 2423732 2024522 0 0
EnterDebounceSt_A 2423732 102 0 0
EnterDetectSt_A 2423732 102 0 0
EnterStableSt_A 2423732 102 0 0
PulseIsPulse_A 2423732 102 0 0
StayInStableSt 2423732 306 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 2423732 3358 0 0
gen_low_level_sva.LowLevelEvent_A 2423732 2033382 0 0
gen_not_sticky_sva.StableStDropOut_A 2423732 100 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 204 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T24 817 0 0 0
T39 627 4 0 0
T40 414 0 0 0
T41 627 4 0 0
T42 503 0 0 0
T83 0 4 0 0
T84 0 2 0 0
T85 0 2 0 0
T87 0 4 0 0
T88 0 4 0 0
T89 0 4 0 0
T90 0 4 0 0
T91 0 4 0 0
T93 414 0 0 0
T94 414 0 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 4090 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T24 817 0 0 0
T39 627 81 0 0
T40 414 0 0 0
T41 627 81 0 0
T42 503 0 0 0
T83 0 81 0 0
T84 0 20 0 0
T85 0 20 0 0
T87 0 81 0 0
T88 0 81 0 0
T89 0 81 0 0
T90 0 81 0 0
T91 0 81 0 0
T93 414 0 0 0
T94 414 0 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2031761 0 0
T16 1037 636 0 0
T17 17445 15016 0 0
T18 414 13 0 0
T21 17445 15016 0 0
T22 17445 15016 0 0
T23 17445 15016 0 0
T38 8403 2 0 0
T39 627 222 0 0
T40 414 13 0 0
T41 627 222 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 408 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T24 817 0 0 0
T39 627 8 0 0
T40 414 0 0 0
T41 627 8 0 0
T42 503 0 0 0
T83 0 8 0 0
T84 0 4 0 0
T85 0 4 0 0
T87 0 8 0 0
T88 0 8 0 0
T89 0 8 0 0
T90 0 8 0 0
T91 0 8 0 0
T93 414 0 0 0
T94 414 0 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 102 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T24 817 0 0 0
T39 627 2 0 0
T40 414 0 0 0
T41 627 2 0 0
T42 503 0 0 0
T83 0 2 0 0
T84 0 1 0 0
T85 0 1 0 0
T87 0 2 0 0
T88 0 2 0 0
T89 0 2 0 0
T90 0 2 0 0
T91 0 2 0 0
T93 414 0 0 0
T94 414 0 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2023105 0 0
T16 1037 636 0 0
T17 17445 15016 0 0
T18 414 13 0 0
T21 17445 15016 0 0
T22 17445 15016 0 0
T23 17445 15016 0 0
T38 8403 2 0 0
T39 627 50 0 0
T40 414 13 0 0
T41 627 50 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2024522 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 51 0 0
T40 414 14 0 0
T41 627 51 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 102 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T24 817 0 0 0
T39 627 2 0 0
T40 414 0 0 0
T41 627 2 0 0
T42 503 0 0 0
T83 0 2 0 0
T84 0 1 0 0
T85 0 1 0 0
T87 0 2 0 0
T88 0 2 0 0
T89 0 2 0 0
T90 0 2 0 0
T91 0 2 0 0
T93 414 0 0 0
T94 414 0 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 102 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T24 817 0 0 0
T39 627 2 0 0
T40 414 0 0 0
T41 627 2 0 0
T42 503 0 0 0
T83 0 2 0 0
T84 0 1 0 0
T85 0 1 0 0
T87 0 2 0 0
T88 0 2 0 0
T89 0 2 0 0
T90 0 2 0 0
T91 0 2 0 0
T93 414 0 0 0
T94 414 0 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 102 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T24 817 0 0 0
T39 627 2 0 0
T40 414 0 0 0
T41 627 2 0 0
T42 503 0 0 0
T83 0 2 0 0
T84 0 1 0 0
T85 0 1 0 0
T87 0 2 0 0
T88 0 2 0 0
T89 0 2 0 0
T90 0 2 0 0
T91 0 2 0 0
T93 414 0 0 0
T94 414 0 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 102 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T24 817 0 0 0
T39 627 2 0 0
T40 414 0 0 0
T41 627 2 0 0
T42 503 0 0 0
T83 0 2 0 0
T84 0 1 0 0
T85 0 1 0 0
T87 0 2 0 0
T88 0 2 0 0
T89 0 2 0 0
T90 0 2 0 0
T91 0 2 0 0
T93 414 0 0 0
T94 414 0 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 306 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T24 817 0 0 0
T39 627 6 0 0
T40 414 0 0 0
T41 627 6 0 0
T42 503 0 0 0
T83 0 6 0 0
T84 0 3 0 0
T85 0 3 0 0
T87 0 6 0 0
T88 0 6 0 0
T89 0 6 0 0
T90 0 6 0 0
T91 0 6 0 0
T93 414 0 0 0
T94 414 0 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 3358 0 0
T16 1037 5 0 0
T17 17445 22 0 0
T18 414 1 0 0
T21 17445 22 0 0
T22 17445 22 0 0
T23 17445 22 0 0
T38 8403 0 0 0
T39 627 3 0 0
T40 414 1 0 0
T41 627 3 0 0
T42 0 7 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2033382 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 100 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T24 817 0 0 0
T39 627 2 0 0
T40 414 0 0 0
T41 627 2 0 0
T42 503 0 0 0
T83 0 2 0 0
T87 0 2 0 0
T88 0 2 0 0
T89 0 2 0 0
T90 0 2 0 0
T91 0 2 0 0
T93 414 0 0 0
T94 414 0 0 0
T116 0 2 0 0
T117 0 2 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
Line No.TotalCoveredPercent
TOTAL464393.48
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125322990.62
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
TotalCoveredPercent
Conditions181688.89
Logical181688.89
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT16,T17,T18
11CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT16,T17,T18 VC_COV_UNR
1CoveredT16,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT16,T19,T20
10CoveredT16,T17,T18
11CoveredT16,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT16,T19,T20
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT16,T19,T20
01Unreachable
10CoveredT16,T19,T20

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T16,T19,T20
DetectSt 168 Covered T16,T19,T20
IdleSt 163 Covered T16,T17,T18
StableSt 191 Covered T16,T19,T20


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T16,T19,T20
DebounceSt->IdleSt 163 Covered T84,T85
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T16,T19,T20
IdleSt->DebounceSt 148 Covered T16,T19,T20
StableSt->IdleSt 206 Covered T16,T19,T20



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T16,T19,T20
0 1 Covered T16,T19,T20
0 0 Excluded T16,T17,T18 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T16,T19,T20
0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T16,T19,T20
IdleSt 0 - - - - - - Covered T16,T17,T18
DebounceSt - 1 - - - - - Covered T84,T85
DebounceSt - 0 1 1 - - - Covered T16,T19,T20
DebounceSt - 0 1 0 - - - Not Covered
DebounceSt - 0 0 - - - - Covered T16,T19,T20
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T16,T19,T20
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T16,T19,T20
StableSt - - - - - - 0 Covered T16,T19,T20
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 2423732 104 0 0
CntIncr_A 2423732 2002 0 0
CntNoWrap_A 2423732 2031861 0 0
DetectStDropOut_A 2423732 0 0 0
DetectedOut_A 2423732 5500 0 0
DetectedPulseOut_A 2423732 50 0 0
DisabledIdleSt_A 2423732 2018953 0 0
DisabledNoDetection_A 2423732 2020370 0 0
EnterDebounceSt_A 2423732 54 0 0
EnterDetectSt_A 2423732 50 0 0
EnterStableSt_A 2423732 50 0 0
PulseIsPulse_A 2423732 50 0 0
StayInStableSt 2423732 5450 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 2423732 3358 0 0
gen_low_level_sva.LowLevelEvent_A 2423732 2033382 0 0
gen_sticky_sva.StableStDropOut_A 2423732 4750 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 104 0 0
T16 1037 2 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 2 0 0
T20 0 2 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 2 0 0
T36 0 2 0 0
T37 0 2 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 2 0 0
T44 0 2 0 0
T84 0 2 0 0
T85 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2002 0 0
T16 1037 37 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 37 0 0
T20 0 37 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 37 0 0
T36 0 37 0 0
T37 0 37 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 37 0 0
T44 0 37 0 0
T84 0 76 0 0
T85 0 76 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2031861 0 0
T16 1037 634 0 0
T17 17445 15016 0 0
T18 414 13 0 0
T21 17445 15016 0 0
T22 17445 15016 0 0
T23 17445 15016 0 0
T38 8403 2 0 0
T39 627 226 0 0
T40 414 13 0 0
T41 627 226 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 5500 0 0
T16 1037 110 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 110 0 0
T20 0 110 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 110 0 0
T36 0 110 0 0
T37 0 110 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 110 0 0
T44 0 110 0 0
T45 0 110 0 0
T46 0 110 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 50 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2018953 0 0
T16 1037 379 0 0
T17 17445 15016 0 0
T18 414 13 0 0
T21 17445 15016 0 0
T22 17445 15016 0 0
T23 17445 15016 0 0
T38 8403 2 0 0
T39 627 226 0 0
T40 414 13 0 0
T41 627 226 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2020370 0 0
T16 1037 380 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 54 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T84 0 2 0 0
T85 0 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 50 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 50 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 50 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 5450 0 0
T16 1037 109 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 109 0 0
T20 0 109 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 109 0 0
T36 0 109 0 0
T37 0 109 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 109 0 0
T44 0 109 0 0
T45 0 109 0 0
T46 0 109 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 3358 0 0
T16 1037 5 0 0
T17 17445 22 0 0
T18 414 1 0 0
T21 17445 22 0 0
T22 17445 22 0 0
T23 17445 22 0 0
T38 8403 0 0 0
T39 627 3 0 0
T40 414 1 0 0
T41 627 3 0 0
T42 0 7 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2033382 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

gen_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 4750 0 0
T16 1037 95 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 95 0 0
T20 0 95 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 95 0 0
T36 0 95 0 0
T37 0 95 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 95 0 0
T44 0 95 0 0
T45 0 95 0 0
T46 0 95 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
Line No.TotalCoveredPercent
TOTAL464393.48
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125322990.62
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
TotalCoveredPercent
Conditions181688.89
Logical181688.89
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT16,T17,T18
11CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT16,T17,T18 VC_COV_UNR
1CoveredT16,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT16,T19,T20
10CoveredT16,T17,T18
11CoveredT16,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT16,T19,T20
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT16,T19,T20
01Unreachable
10CoveredT16,T19,T20

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T16,T19,T20
DetectSt 168 Covered T16,T19,T20
IdleSt 163 Covered T16,T17,T18
StableSt 191 Covered T16,T19,T20


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T16,T19,T20
DebounceSt->IdleSt 163 Covered T84,T85
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T16,T19,T20
IdleSt->DebounceSt 148 Covered T16,T19,T20
StableSt->IdleSt 206 Covered T16,T19,T20



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
Line No.TotalCoveredPercent
Branches 20 18 90.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T16,T19,T20
0 1 Covered T16,T19,T20
0 0 Excluded T16,T17,T18 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T16,T19,T20
0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T16,T19,T20
IdleSt 0 - - - - - - Covered T16,T17,T18
DebounceSt - 1 - - - - - Covered T84,T85
DebounceSt - 0 1 1 - - - Covered T16,T19,T20
DebounceSt - 0 1 0 - - - Not Covered
DebounceSt - 0 0 - - - - Covered T16,T19,T20
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T16,T19,T20
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T16,T19,T20
StableSt - - - - - - 0 Covered T16,T19,T20
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 2423732 104 0 0
CntIncr_A 2423732 3600 0 0
CntNoWrap_A 2423732 2031861 0 0
DetectStDropOut_A 2423732 0 0 0
DetectedOut_A 2423732 5800 0 0
DetectedPulseOut_A 2423732 50 0 0
DisabledIdleSt_A 2423732 2018953 0 0
DisabledNoDetection_A 2423732 2020370 0 0
EnterDebounceSt_A 2423732 54 0 0
EnterDetectSt_A 2423732 50 0 0
EnterStableSt_A 2423732 50 0 0
PulseIsPulse_A 2423732 50 0 0
StayInStableSt 2423732 5750 0 0
gen_high_level_sva.HighLevelEvent_A 2423732 2033382 0 0
gen_sticky_sva.StableStDropOut_A 2423732 2600 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 104 0 0
T16 1037 2 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 2 0 0
T20 0 2 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 2 0 0
T36 0 2 0 0
T37 0 2 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 2 0 0
T44 0 2 0 0
T84 0 2 0 0
T85 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 3600 0 0
T16 1037 69 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 69 0 0
T20 0 69 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 69 0 0
T36 0 69 0 0
T37 0 69 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 69 0 0
T44 0 69 0 0
T84 0 75 0 0
T85 0 75 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2031861 0 0
T16 1037 634 0 0
T17 17445 15016 0 0
T18 414 13 0 0
T21 17445 15016 0 0
T22 17445 15016 0 0
T23 17445 15016 0 0
T38 8403 2 0 0
T39 627 226 0 0
T40 414 13 0 0
T41 627 226 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 5800 0 0
T16 1037 116 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 116 0 0
T20 0 116 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 116 0 0
T36 0 116 0 0
T37 0 116 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 116 0 0
T44 0 116 0 0
T45 0 116 0 0
T46 0 116 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 50 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2018953 0 0
T16 1037 379 0 0
T17 17445 15016 0 0
T18 414 13 0 0
T21 17445 15016 0 0
T22 17445 15016 0 0
T23 17445 15016 0 0
T38 8403 2 0 0
T39 627 226 0 0
T40 414 13 0 0
T41 627 226 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2020370 0 0
T16 1037 380 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 54 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T84 0 2 0 0
T85 0 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 50 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 50 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 50 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 5750 0 0
T16 1037 115 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 115 0 0
T20 0 115 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 115 0 0
T36 0 115 0 0
T37 0 115 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 115 0 0
T44 0 115 0 0
T45 0 115 0 0
T46 0 115 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2033382 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

gen_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2600 0 0
T16 1037 52 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 52 0 0
T20 0 52 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 52 0 0
T36 0 52 0 0
T37 0 52 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 52 0 0
T44 0 52 0 0
T45 0 52 0 0
T46 0 52 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
Line No.TotalCoveredPercent
TOTAL434093.02
CONT_ASSIGN6011100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125322990.62
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
79 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
TotalCoveredPercent
Conditions151386.67
Logical151386.67
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT16,T17,T18 VC_COV_UNR
1CoveredT16,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT16,T19,T20
10CoveredT16,T17,T18
11CoveredT16,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT16,T19,T20
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT16,T19,T20
01Unreachable
10CoveredT16,T19,T20

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T16,T19,T20
DetectSt 168 Covered T16,T19,T20
IdleSt 163 Covered T16,T17,T18
StableSt 191 Covered T16,T19,T20


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T16,T19,T20
DebounceSt->IdleSt 163 Covered T84,T85
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T16,T19,T20
IdleSt->DebounceSt 148 Covered T16,T19,T20
StableSt->IdleSt 206 Covered T16,T19,T20



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
Line No.TotalCoveredPercent
Branches 18 16 88.89
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 8 80.00
IF 219 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T16,T19,T20
0 1 Covered T16,T19,T20
0 0 Excluded T16,T17,T18 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T16,T19,T20
0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T16,T19,T20
IdleSt 0 - - - - - - Covered T16,T17,T18
DebounceSt - 1 - - - - - Covered T84,T85
DebounceSt - 0 1 1 - - - Covered T16,T19,T20
DebounceSt - 0 1 0 - - - Not Covered
DebounceSt - 0 0 - - - - Covered T16,T19,T20
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T16,T19,T20
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T16,T19,T20
StableSt - - - - - - 0 Covered T16,T19,T20
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 2423732 104 0 0
CntIncr_A 2423732 5006 0 0
CntNoWrap_A 2423732 2031861 0 0
DetectStDropOut_A 2423732 0 0 0
DetectedOut_A 2423732 5400 0 0
DetectedPulseOut_A 2423732 50 0 0
DisabledIdleSt_A 2423732 2018953 0 0
DisabledNoDetection_A 2423732 2020370 0 0
EnterDebounceSt_A 2423732 54 0 0
EnterDetectSt_A 2423732 50 0 0
EnterStableSt_A 2423732 50 0 0
PulseIsPulse_A 2423732 50 0 0
StayInStableSt 2423732 5350 0 0
gen_high_event_sva.HighLevelEvent_A 2423732 2033382 0 0
gen_high_level_sva.HighLevelEvent_A 2423732 2033382 0 0
gen_sticky_sva.StableStDropOut_A 2423732 2250 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 104 0 0
T16 1037 2 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 2 0 0
T20 0 2 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 2 0 0
T36 0 2 0 0
T37 0 2 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 2 0 0
T44 0 2 0 0
T84 0 2 0 0
T85 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 5006 0 0
T16 1037 97 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 97 0 0
T20 0 97 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 97 0 0
T36 0 97 0 0
T37 0 97 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 97 0 0
T44 0 97 0 0
T84 0 78 0 0
T85 0 78 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2031861 0 0
T16 1037 634 0 0
T17 17445 15016 0 0
T18 414 13 0 0
T21 17445 15016 0 0
T22 17445 15016 0 0
T23 17445 15016 0 0
T38 8403 2 0 0
T39 627 226 0 0
T40 414 13 0 0
T41 627 226 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 5400 0 0
T16 1037 108 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 108 0 0
T20 0 108 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 108 0 0
T36 0 108 0 0
T37 0 108 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 108 0 0
T44 0 108 0 0
T45 0 108 0 0
T46 0 108 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 50 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2018953 0 0
T16 1037 379 0 0
T17 17445 15016 0 0
T18 414 13 0 0
T21 17445 15016 0 0
T22 17445 15016 0 0
T23 17445 15016 0 0
T38 8403 2 0 0
T39 627 226 0 0
T40 414 13 0 0
T41 627 226 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2020370 0 0
T16 1037 380 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 54 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T84 0 2 0 0
T85 0 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 50 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 50 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 50 0 0
T16 1037 1 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 5350 0 0
T16 1037 107 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 107 0 0
T20 0 107 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 107 0 0
T36 0 107 0 0
T37 0 107 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 107 0 0
T44 0 107 0 0
T45 0 107 0 0
T46 0 107 0 0

gen_high_event_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2033382 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2033382 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

gen_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2250 0 0
T16 1037 45 0 0
T17 17445 0 0 0
T18 414 0 0 0
T19 0 45 0 0
T20 0 45 0 0
T21 17445 0 0 0
T22 17445 0 0 0
T23 17445 0 0 0
T32 0 45 0 0
T36 0 45 0 0
T37 0 45 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T43 0 45 0 0
T44 0 45 0 0
T45 0 45 0 0
T46 0 45 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL464189.13
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125322784.38
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 0 1
164 0 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211780.95
Logical211780.95
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT16,T17,T38
11CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT17,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT16,T17,T18 VC_COV_UNR
1CoveredT17,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT17,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT17,T21,T22
10CoveredT16,T17,T18
11CoveredT17,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT17,T21,T22
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT17,T21,T22
01Not Covered
10CoveredT84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT17,T21,T22
1-Not Covered

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 4 66.67
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T17,T21,T22
DetectSt 168 Covered T17,T21,T22
IdleSt 163 Covered T16,T17,T18
StableSt 191 Covered T17,T21,T22


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T17,T21,T22
DebounceSt->IdleSt 163 Not Covered
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T17,T21,T22
IdleSt->DebounceSt 148 Covered T17,T21,T22
StableSt->IdleSt 206 Covered T17,T21,T22



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 17 85.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 7 70.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T17,T21,T22
0 1 Covered T17,T21,T22
0 0 Excluded T16,T17,T18 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T17,T21,T22
0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T17,T21,T22
IdleSt 0 - - - - - - Covered T16,T17,T18
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T17,T21,T22
DebounceSt - 0 1 0 - - - Not Covered
DebounceSt - 0 0 - - - - Covered T17,T21,T22
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T17,T21,T22
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T84,T85
StableSt - - - - - - 0 Covered T17,T21,T22
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 13 86.67
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 13 86.67




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 2423732 104 0 0
CntIncr_A 2423732 4554 0 0
CntNoWrap_A 2423732 2031861 0 0
DetectStDropOut_A 2423732 0 0 0
DetectedOut_A 2423732 1858 0 0
DetectedPulseOut_A 2423732 52 0 0
DisabledIdleSt_A 2423732 2020647 0 0
DisabledNoDetection_A 2423732 2022014 0 0
EnterDebounceSt_A 2423732 52 0 0
EnterDetectSt_A 2423732 52 0 0
EnterStableSt_A 2423732 52 0 0
PulseIsPulse_A 2423732 52 0 0
StayInStableSt 2423732 1756 0 0
gen_high_level_sva.HighLevelEvent_A 2423732 2033382 0 0
gen_not_sticky_sva.StableStDropOut_A 2423732 0 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 104 0 0
T17 17445 2 0 0
T18 414 0 0 0
T21 17445 2 0 0
T22 17445 2 0 0
T23 17445 2 0 0
T29 0 2 0 0
T35 0 2 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 2 0 0
T112 0 2 0 0
T113 0 2 0 0
T114 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 4554 0 0
T17 17445 90 0 0
T18 414 0 0 0
T21 17445 90 0 0
T22 17445 90 0 0
T23 17445 90 0 0
T29 0 90 0 0
T35 0 90 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 27 0 0
T112 0 90 0 0
T113 0 90 0 0
T114 0 90 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2031861 0 0
T16 1037 636 0 0
T17 17445 15014 0 0
T18 414 13 0 0
T21 17445 15014 0 0
T22 17445 15014 0 0
T23 17445 15014 0 0
T38 8403 2 0 0
T39 627 226 0 0
T40 414 13 0 0
T41 627 226 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 1858 0 0
T17 17445 37 0 0
T18 414 0 0 0
T21 17445 37 0 0
T22 17445 37 0 0
T23 17445 37 0 0
T29 0 37 0 0
T35 0 37 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 4 0 0
T112 0 37 0 0
T113 0 37 0 0
T114 0 37 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 52 0 0
T17 17445 1 0 0
T18 414 0 0 0
T21 17445 1 0 0
T22 17445 1 0 0
T23 17445 1 0 0
T29 0 1 0 0
T35 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 1 0 0
T112 0 1 0 0
T113 0 1 0 0
T114 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2020647 0 0
T16 1037 636 0 0
T17 17445 14791 0 0
T18 414 13 0 0
T21 17445 14791 0 0
T22 17445 14791 0 0
T23 17445 14791 0 0
T38 8403 2 0 0
T39 627 226 0 0
T40 414 13 0 0
T41 627 226 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2022014 0 0
T16 1037 637 0 0
T17 17445 14799 0 0
T18 414 14 0 0
T21 17445 14799 0 0
T22 17445 14799 0 0
T23 17445 14799 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 52 0 0
T17 17445 1 0 0
T18 414 0 0 0
T21 17445 1 0 0
T22 17445 1 0 0
T23 17445 1 0 0
T29 0 1 0 0
T35 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 1 0 0
T112 0 1 0 0
T113 0 1 0 0
T114 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 52 0 0
T17 17445 1 0 0
T18 414 0 0 0
T21 17445 1 0 0
T22 17445 1 0 0
T23 17445 1 0 0
T29 0 1 0 0
T35 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 1 0 0
T112 0 1 0 0
T113 0 1 0 0
T114 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 52 0 0
T17 17445 1 0 0
T18 414 0 0 0
T21 17445 1 0 0
T22 17445 1 0 0
T23 17445 1 0 0
T29 0 1 0 0
T35 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 1 0 0
T112 0 1 0 0
T113 0 1 0 0
T114 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 52 0 0
T17 17445 1 0 0
T18 414 0 0 0
T21 17445 1 0 0
T22 17445 1 0 0
T23 17445 1 0 0
T29 0 1 0 0
T35 0 1 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 1 0 0
T112 0 1 0 0
T113 0 1 0 0
T114 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 1756 0 0
T17 17445 35 0 0
T18 414 0 0 0
T21 17445 35 0 0
T22 17445 35 0 0
T23 17445 35 0 0
T29 0 35 0 0
T35 0 35 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 0 0 0
T41 627 0 0 0
T42 503 0 0 0
T84 0 3 0 0
T112 0 35 0 0
T113 0 35 0 0
T114 0 35 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2033382 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 0 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464189.13
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125322784.38
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 0 1
164 0 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211780.95
Logical211780.95
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT16,T17,T38
10CoveredT16,T17,T18
11CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT84,T85

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT16,T17,T18 VC_COV_UNR
1CoveredT84,T85

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT84,T85

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT84,T85
10CoveredT17,T18,T21
11CoveredT84,T85

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT84,T85
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT84,T85
01Not Covered
10CoveredT84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT84,T85
1-Not Covered

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 4 66.67
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T84,T85
DetectSt 168 Covered T84,T85
IdleSt 163 Covered T16,T17,T18
StableSt 191 Covered T84,T85


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T84,T85
DebounceSt->IdleSt 163 Not Covered
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T84,T85
IdleSt->DebounceSt 148 Covered T84,T85
StableSt->IdleSt 206 Covered T84,T85



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 17 85.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 7 70.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T84,T85
0 1 Covered T84,T85
0 0 Excluded T16,T17,T18 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T84,T85
0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T84,T85
IdleSt 0 - - - - - - Covered T16,T17,T18
DebounceSt - 1 - - - - - Not Covered
DebounceSt - 0 1 1 - - - Covered T84,T85
DebounceSt - 0 1 0 - - - Not Covered
DebounceSt - 0 0 - - - - Covered T84,T85
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T84,T85
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T84,T85
StableSt - - - - - - 0 Covered T84,T85
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 14 87.50
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 14 87.50




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 2423732 4 0 0
CntIncr_A 2423732 54 0 0
CntNoWrap_A 2423732 2031961 0 0
DetectStDropOut_A 2423732 0 0 0
DetectedOut_A 2423732 6 0 0
DetectedPulseOut_A 2423732 2 0 0
DisabledIdleSt_A 2423732 2031899 0 0
DisabledNoDetection_A 2423732 2033316 0 0
EnterDebounceSt_A 2423732 2 0 0
EnterDetectSt_A 2423732 2 0 0
EnterStableSt_A 2423732 2 0 0
PulseIsPulse_A 2423732 2 0 0
StayInStableSt 2423732 4 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 2423732 1806 0 0
gen_low_level_sva.LowLevelEvent_A 2423732 2033382 0 0
gen_not_sticky_sva.StableStDropOut_A 2423732 0 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 4 0 0
T35 17445 0 0 0
T84 7721 2 0 0
T85 7721 2 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 54 0 0
T35 17445 0 0 0
T84 7721 27 0 0
T85 7721 27 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2031961 0 0
T16 1037 636 0 0
T17 17445 15016 0 0
T18 414 13 0 0
T21 17445 15016 0 0
T22 17445 15016 0 0
T23 17445 15016 0 0
T38 8403 2 0 0
T39 627 226 0 0
T40 414 13 0 0
T41 627 226 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 6 0 0
T35 17445 0 0 0
T84 7721 3 0 0
T85 7721 3 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2 0 0
T35 17445 0 0 0
T84 7721 1 0 0
T85 7721 1 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2031899 0 0
T16 1037 636 0 0
T17 17445 15016 0 0
T18 414 13 0 0
T21 17445 15016 0 0
T22 17445 15016 0 0
T23 17445 15016 0 0
T38 8403 2 0 0
T39 627 226 0 0
T40 414 13 0 0
T41 627 226 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2033316 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2 0 0
T35 17445 0 0 0
T84 7721 1 0 0
T85 7721 1 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2 0 0
T35 17445 0 0 0
T84 7721 1 0 0
T85 7721 1 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2 0 0
T35 17445 0 0 0
T84 7721 1 0 0
T85 7721 1 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2 0 0
T35 17445 0 0 0
T84 7721 1 0 0
T85 7721 1 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 4 0 0
T35 17445 0 0 0
T84 7721 2 0 0
T85 7721 2 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T110 503 0 0 0
T111 817 0 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 1806 0 0
T17 17445 19 0 0
T18 414 1 0 0
T21 17445 19 0 0
T22 17445 19 0 0
T23 17445 19 0 0
T24 0 2 0 0
T38 8403 0 0 0
T39 627 0 0 0
T40 414 1 0 0
T41 627 0 0 0
T42 503 4 0 0
T93 0 1 0 0
T94 0 1 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 2033382 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2423732 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%