Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T18,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T17,T18,T21
1	1	Covered	T17,T18,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T17,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T18,T21
1	1	Covered	T17,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T21,T22
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T21,T22
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T21,T22
1	-	Covered	T17,T21,T22

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T21,T22
DetectSt	168	Covered	T17,T21,T22
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T17,T21,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T21,T22
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T17,T21,T22
IdleSt->DebounceSt	148	Covered	T17,T21,T22
StableSt->IdleSt	206	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T21,T22
0	1	Covered	T17,T21,T22
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T17,T21,T22
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T17,T18,T21
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T21,T22
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T21,T22
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T17,T21,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T21,T22
StableSt	-	-	-	-	-	-	0	Covered	T17,T21,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	304	0	0
CntIncr_A	2423732	10554	0	0
CntNoWrap_A	2423732	2031661	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	5256	0	0
DetectedPulseOut_A	2423732	152	0	0
DisabledIdleSt_A	2423732	2000049	0	0
DisabledNoDetection_A	2423732	2001366	0	0
EnterDebounceSt_A	2423732	152	0	0
EnterDetectSt_A	2423732	152	0	0
EnterStableSt_A	2423732	152	0	0
PulseIsPulse_A	2423732	152	0	0
StayInStableSt	2423732	5054	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	100	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	304
T17	17445	2
T18	414	0
T21	17445	2
T22	17445	2
T23	17445	2
T24	0	4
T25	0	4
T26	0	4
T28	0	4
T29	0	2
T30	0	4
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	10554
T17	17445	90
T18	414	0
T21	17445	90
T22	17445	90
T23	17445	90
T24	0	120
T25	0	120
T26	0	120
T28	0	120
T29	0	90
T30	0	120
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031661
T16	1037	636
T17	17445	15014
T18	414	13
T21	17445	15014
T22	17445	15014
T23	17445	15014
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	5256
T17	17445	2
T18	414	0
T21	17445	2
T22	17445	2
T23	17445	2
T24	0	103
T25	0	103
T26	0	103
T28	0	103
T29	0	2
T30	0	103
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	152
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	2
T25	0	2
T26	0	2
T28	0	2
T29	0	1
T30	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2000049
T16	1037	636
T17	17445	14791
T18	414	13
T21	17445	14791
T22	17445	14791
T23	17445	14791
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2001366
T16	1037	637
T17	17445	14799
T18	414	14
T21	17445	14799
T22	17445	14799
T23	17445	14799
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	152
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	2
T25	0	2
T26	0	2
T28	0	2
T29	0	1
T30	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	152
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	2
T25	0	2
T26	0	2
T28	0	2
T29	0	1
T30	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	152
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	2
T25	0	2
T26	0	2
T28	0	2
T29	0	1
T30	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	152
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	2
T25	0	2
T26	0	2
T28	0	2
T29	0	1
T30	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	5054
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	100
T25	0	100
T26	0	100
T28	0	100
T29	0	1
T30	0	100
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	2423732	100
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	1
T25	0	1
T26	0	1
T28	0	1
T29	0	1
T30	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T18,T21
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T21
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T17,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T18,T21
1	1	Covered	T17,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T21,T22
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T21,T22
0	1	Not Covered
1	0	Covered	T84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T21,T22
1	-	Not Covered

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T21,T22
DetectSt	168	Covered	T17,T21,T22
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T17,T21,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T21,T22
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T17,T21,T22
IdleSt->DebounceSt	148	Covered	T17,T21,T22
StableSt->IdleSt	206	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T21,T22
0	1	Covered	T17,T21,T22
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T17,T21,T22
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T21,T22
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T21,T22
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T17,T21,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T84,T85
StableSt	-	-	-	-	-	-	0	Covered	T17,T21,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	4554	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	1860	0	0
DetectedPulseOut_A	2423732	52	0	0
DisabledIdleSt_A	2423732	2020645	0	0
DisabledNoDetection_A	2423732	2022012	0	0
EnterDebounceSt_A	2423732	52	0	0
EnterDetectSt_A	2423732	52	0	0
EnterStableSt_A	2423732	52	0	0
PulseIsPulse_A	2423732	52	0	0
StayInStableSt	2423732	1758	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	2518	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	0	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	104
T17	17445	2
T18	414	0
T21	17445	2
T22	17445	2
T23	17445	2
T29	0	2
T35	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	2
T112	0	2
T113	0	2
T114	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	4554
T17	17445	90
T18	414	0
T21	17445	90
T22	17445	90
T23	17445	90
T29	0	90
T35	0	90
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	27
T112	0	90
T113	0	90
T114	0	90

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031861
T16	1037	636
T17	17445	15014
T18	414	13
T21	17445	15014
T22	17445	15014
T23	17445	15014
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	1860
T17	17445	37
T18	414	0
T21	17445	37
T22	17445	37
T23	17445	37
T29	0	37
T35	0	37
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	5
T112	0	37
T113	0	37
T114	0	37

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	52
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T29	0	1
T35	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	1
T112	0	1
T113	0	1
T114	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2020645
T16	1037	636
T17	17445	14791
T18	414	13
T21	17445	14791
T22	17445	14791
T23	17445	14791
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2022012
T16	1037	637
T17	17445	14799
T18	414	14
T21	17445	14799
T22	17445	14799
T23	17445	14799
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	52
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T29	0	1
T35	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	1
T112	0	1
T113	0	1
T114	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	52
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T29	0	1
T35	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	1
T112	0	1
T113	0	1
T114	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	52
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T29	0	1
T35	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	1
T112	0	1
T113	0	1
T114	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	52
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T29	0	1
T35	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	1
T112	0	1
T113	0	1
T114	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	1758
T17	17445	35
T18	414	0
T21	17445	35
T22	17445	35
T23	17445	35
T29	0	35
T35	0	35
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	4
T112	0	35
T113	0	35
T114	0	35

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	2423732	2518
T17	17445	25
T18	414	0
T21	17445	25
T22	17445	25
T23	17445	25
T24	0	1
T25	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	2
T47	0	6
T53	0	2
T115	0	2

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T18,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T17,T18,T21
1	1	Covered	T17,T18,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T24,T25,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T24,T25,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T24,T25,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T17,T18,T21
1	1	Covered	T24,T25,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T26
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T26
0	1	Covered	T24,T25,T26
1	0	Covered	T84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T25,T26
1	-	Covered	T24,T25,T26

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T25,T26
DetectSt	168	Covered	T24,T25,T26
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T24,T25,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T25,T26
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T24,T25,T26
IdleSt->DebounceSt	148	Covered	T24,T25,T26
StableSt->IdleSt	206	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T25,T26
0	1	Covered	T24,T25,T26
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T25,T26
IdleSt	0	-	-	-	-	-	-	Covered	T17,T18,T21
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T25,T26
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T25,T26
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T24,T25,T26
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T25,T26
StableSt	-	-	-	-	-	-	0	Covered	T24,T25,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	204	0	0
CntIncr_A	2423732	6054	0	0
CntNoWrap_A	2423732	2031761	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	4110	0	0
DetectedPulseOut_A	2423732	102	0	0
DisabledIdleSt_A	2423732	2011295	0	0
DisabledNoDetection_A	2423732	2012662	0	0
EnterDebounceSt_A	2423732	102	0	0
EnterDetectSt_A	2423732	102	0	0
EnterStableSt_A	2423732	102	0	0
PulseIsPulse_A	2423732	102	0	0
StayInStableSt	2423732	3958	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	50	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	204
T24	817	4
T25	817	4
T26	817	4
T28	817	4
T29	17445	0
T30	0	4
T47	494	0
T53	503	0
T84	0	2
T85	0	2
T94	414	0
T111	0	4
T115	423	0
T118	0	4
T119	0	4
T120	423	0

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	6054
T24	817	120
T25	817	120
T26	817	120
T28	817	120
T29	17445	0
T30	0	120
T47	494	0
T53	503	0
T84	0	27
T85	0	27
T94	414	0
T111	0	120
T115	423	0
T118	0	120
T119	0	120
T120	423	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031761
T16	1037	636
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	4110
T24	817	82
T25	817	82
T26	817	82
T28	817	82
T29	17445	0
T30	0	82
T47	494	0
T53	503	0
T84	0	5
T85	0	5
T94	414	0
T111	0	82
T115	423	0
T118	0	82
T119	0	82
T120	423	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	102
T24	817	2
T25	817	2
T26	817	2
T28	817	2
T29	17445	0
T30	0	2
T47	494	0
T53	503	0
T84	0	1
T85	0	1
T94	414	0
T111	0	2
T115	423	0
T118	0	2
T119	0	2
T120	423	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2011295
T16	1037	636
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2012662
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	102
T24	817	2
T25	817	2
T26	817	2
T28	817	2
T29	17445	0
T30	0	2
T47	494	0
T53	503	0
T84	0	1
T85	0	1
T94	414	0
T111	0	2
T115	423	0
T118	0	2
T119	0	2
T120	423	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	102
T24	817	2
T25	817	2
T26	817	2
T28	817	2
T29	17445	0
T30	0	2
T47	494	0
T53	503	0
T84	0	1
T85	0	1
T94	414	0
T111	0	2
T115	423	0
T118	0	2
T119	0	2
T120	423	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	102
T24	817	2
T25	817	2
T26	817	2
T28	817	2
T29	17445	0
T30	0	2
T47	494	0
T53	503	0
T84	0	1
T85	0	1
T94	414	0
T111	0	2
T115	423	0
T118	0	2
T119	0	2
T120	423	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	102
T24	817	2
T25	817	2
T26	817	2
T28	817	2
T29	17445	0
T30	0	2
T47	494	0
T53	503	0
T84	0	1
T85	0	1
T94	414	0
T111	0	2
T115	423	0
T118	0	2
T119	0	2
T120	423	0

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	3958
T24	817	79
T25	817	79
T26	817	79
T28	817	79
T29	17445	0
T30	0	79
T47	494	0
T53	503	0
T84	0	4
T85	0	4
T94	414	0
T111	0	79
T115	423	0
T118	0	79
T119	0	79
T120	423	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	2423732	50
T24	817	1
T25	817	1
T26	817	1
T28	817	1
T29	17445	0
T30	0	1
T47	494	0
T53	503	0
T94	414	0
T111	0	1
T115	423	0
T118	0	1
T119	0	1
T120	423	0
T121	0	1
T122	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T17,T18,T21
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T21
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T24,T25,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T24,T25,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T84,T85

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T17,T18,T21
1	1	Covered	T24,T25,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T84,T85
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T84,T85
0	1	Not Covered
1	0	Covered	T84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T84,T85
1	-	Not Covered

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T25,T26
DetectSt	168	Covered	T84,T85
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T84,T85

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T84,T85
DebounceSt->IdleSt	163	Covered	T24,T25,T26
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T84,T85
IdleSt->DebounceSt	148	Covered	T24,T25,T26
StableSt->IdleSt	206	Covered	T84,T85

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T25,T26
0	1	Covered	T24,T25,T26
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T84,T85
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T25,T26
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T25,T26
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T25,T26
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T84,T85
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T84,T85
StableSt	-	-	-	-	-	-	0	Covered	T84,T85
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	54	0	0
CntIncr_A	2423732	3054	0	0
CntNoWrap_A	2423732	2031911	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	6	0	0
DetectedPulseOut_A	2423732	2	0	0
DisabledIdleSt_A	2423732	2011297	0	0
DisabledNoDetection_A	2423732	2012664	0	0
EnterDebounceSt_A	2423732	52	0	0
EnterDetectSt_A	2423732	2	0	0
EnterStableSt_A	2423732	2	0	0
PulseIsPulse_A	2423732	2	0	0
StayInStableSt	2423732	4	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	2668	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	0	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	54
T24	817	1
T25	817	1
T26	817	1
T28	817	1
T29	17445	0
T30	0	1
T47	494	0
T53	503	0
T84	0	2
T85	0	2
T94	414	0
T111	0	1
T115	423	0
T118	0	1
T119	0	1
T120	423	0

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	3054
T24	817	60
T25	817	60
T26	817	60
T28	817	60
T29	17445	0
T30	0	60
T47	494	0
T53	503	0
T84	0	27
T85	0	27
T94	414	0
T111	0	60
T115	423	0
T118	0	60
T119	0	60
T120	423	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031911
T16	1037	636
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	6
T35	17445	0
T84	7721	3
T85	7721	3
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	2
T35	17445	0
T84	7721	1
T85	7721	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2011297
T16	1037	636
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2012664
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	52
T24	817	1
T25	817	1
T26	817	1
T28	817	1
T29	17445	0
T30	0	1
T47	494	0
T53	503	0
T84	0	1
T85	0	1
T94	414	0
T111	0	1
T115	423	0
T118	0	1
T119	0	1
T120	423	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	2
T35	17445	0
T84	7721	1
T85	7721	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	2
T35	17445	0
T84	7721	1
T85	7721	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	2
T35	17445	0
T84	7721	1
T85	7721	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	4
T35	17445	0
T84	7721	2
T85	7721	2
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	2423732	2668
T17	17445	25
T18	414	1
T21	17445	25
T22	17445	25
T23	17445	25
T24	0	1
T38	8403	0
T39	627	0
T40	414	1
T41	627	0
T42	503	4
T93	0	1
T94	0	1

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T17,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T17,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T21,T22
1	0	Covered	T16,T17,T18
1	1	Covered	T17,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T21,T22
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T21,T22
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T21,T22
1	-	Covered	T17,T21,T22

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T21,T22
DetectSt	168	Covered	T17,T21,T22
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T17,T21,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T21,T22
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T17,T21,T22
IdleSt->DebounceSt	148	Covered	T17,T21,T22
StableSt->IdleSt	206	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T21,T22
0	1	Covered	T17,T21,T22
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T17,T21,T22
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T21,T22
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T21,T22
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T17,T21,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T21,T22
StableSt	-	-	-	-	-	-	0	Covered	T17,T21,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	304	0	0
CntIncr_A	2423732	10554	0	0
CntNoWrap_A	2423732	2031661	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	5258	0	0
DetectedPulseOut_A	2423732	152	0	0
DisabledIdleSt_A	2423732	2000047	0	0
DisabledNoDetection_A	2423732	2001364	0	0
EnterDebounceSt_A	2423732	152	0	0
EnterDetectSt_A	2423732	152	0	0
EnterStableSt_A	2423732	152	0	0
PulseIsPulse_A	2423732	152	0	0
StayInStableSt	2423732	5106	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	150	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	304
T17	17445	2
T18	414	0
T21	17445	2
T22	17445	2
T23	17445	2
T24	0	4
T25	0	4
T26	0	4
T28	0	4
T29	0	2
T30	0	4
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	10554
T17	17445	90
T18	414	0
T21	17445	90
T22	17445	90
T23	17445	90
T24	0	120
T25	0	120
T26	0	120
T28	0	120
T29	0	90
T30	0	120
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031661
T16	1037	636
T17	17445	15014
T18	414	13
T21	17445	15014
T22	17445	15014
T23	17445	15014
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	5258
T17	17445	3
T18	414	0
T21	17445	3
T22	17445	3
T23	17445	3
T24	0	102
T25	0	102
T26	0	102
T28	0	102
T29	0	3
T30	0	102
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	152
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	2
T25	0	2
T26	0	2
T28	0	2
T29	0	1
T30	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2000047
T16	1037	636
T17	17445	14791
T18	414	13
T21	17445	14791
T22	17445	14791
T23	17445	14791
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2001364
T16	1037	637
T17	17445	14799
T18	414	14
T21	17445	14799
T22	17445	14799
T23	17445	14799
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	152
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	2
T25	0	2
T26	0	2
T28	0	2
T29	0	1
T30	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	152
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	2
T25	0	2
T26	0	2
T28	0	2
T29	0	1
T30	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	152
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	2
T25	0	2
T26	0	2
T28	0	2
T29	0	1
T30	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	152
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	2
T25	0	2
T26	0	2
T28	0	2
T29	0	1
T30	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	5106
T17	17445	2
T18	414	0
T21	17445	2
T22	17445	2
T23	17445	2
T24	0	100
T25	0	100
T26	0	100
T28	0	100
T29	0	2
T30	0	100
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	2423732	150
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	2
T25	0	2
T26	0	2
T28	0	2
T29	0	1
T30	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T84,T85

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T84,T85

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T84,T85

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T84,T85
1	0	Covered	T16,T17,T18
1	1	Covered	T84,T85

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T84,T85
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T84,T85
0	1	Not Covered
1	0	Covered	T84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T84,T85
1	-	Not Covered

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T84,T85
DetectSt	168	Covered	T84,T85
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T84,T85

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T84,T85
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T84,T85
IdleSt->DebounceSt	148	Covered	T84,T85
StableSt->IdleSt	206	Covered	T84,T85

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T84,T85
0	1	Covered	T84,T85
0	0	Excluded	T16,T17,T18	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T84,T85
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T84,T85
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T84,T85
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T84,T85
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T84,T85
StableSt	-	-	-	-	-	-	0	Covered	T84,T85
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	4	0	0
CntIncr_A	2423732	54	0	0
CntNoWrap_A	2423732	2031961	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	8	0	0
DetectedPulseOut_A	2423732	2	0	0
DisabledIdleSt_A	2423732	2031897	0	0
DisabledNoDetection_A	2423732	2033314	0	0
EnterDebounceSt_A	2423732	2	0	0
EnterDetectSt_A	2423732	2	0	0
EnterStableSt_A	2423732	2	0	0
PulseIsPulse_A	2423732	2	0	0
StayInStableSt	2423732	6	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	3358	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	0	0	0

CntClr_A

Name	Attempts	Real Successes
Total	2423732	4
T35	17445	0
T84	7721	2
T85	7721	2
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

CntIncr_A

Name	Attempts	Real Successes
Total	2423732	54
T35	17445	0
T84	7721	27
T85	7721	27
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	2423732	2031961
T16	1037	636
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	2423732	8
T35	17445	0
T84	7721	4
T85	7721	4
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	2423732	2
T35	17445	0
T84	7721	1
T85	7721	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	2423732	2031897
T16	1037	636
T17	17445	15016
T18	414	13
T21	17445	15016
T22	17445	15016
T23	17445	15016
T38	8403	2
T39	627	226
T40	414	13
T41	627	226

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	2423732	2033314
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	2423732	2
T35	17445	0
T84	7721	1
T85	7721	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	2423732	2
T35	17445	0
T84	7721	1
T85	7721	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	2423732	2
T35	17445	0
T84	7721	1
T85	7721	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	2423732	2
T35	17445	0
T84	7721	1
T85	7721	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

StayInStableSt

Name	Attempts	Real Successes
Total	2423732	6
T35	17445	0
T84	7721	3
T85	7721	3
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	2423732	3358
T16	1037	5
T17	17445	22
T18	414	1
T21	17445	22
T22	17445	22
T23	17445	22
T38	8403	0
T39	627	3
T40	414	1
T41	627	3
T42	0	7

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	2423732	2033382
T16	1037	637
T17	17445	15025
T18	414	14
T21	17445	15025
T22	17445	15025
T23	17445	15025
T38	8403	3
T39	627	227
T40	414	14
T41	627	227

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children