Module Definition
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Module : sysrst_ctrl_detect
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.75 96.43 91.86 100.00 95.45 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h 81.68 89.13 80.95 66.67 85.00 86.67
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h 81.68 89.13 80.95 66.67 85.00 86.67
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h 81.68 89.13 80.95 66.67 85.00 86.67
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l 81.85 89.13 80.95 66.67 85.00 87.50
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l 81.85 89.13 80.95 66.67 85.00 87.50
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l 81.85 89.13 80.95 66.67 85.00 87.50
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l 81.85 89.13 80.95 66.67 85.00 87.50
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h 84.92 89.13 90.48 66.67 85.00 93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h 84.92 89.13 90.48 66.67 85.00 93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h 84.92 89.13 90.48 66.67 85.00 93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h 84.92 89.13 90.48 66.67 85.00 93.33
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect 85.00 89.13 90.48 66.67 85.00 93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l 85.00 89.13 90.48 66.67 85.00 93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l 85.00 89.13 90.48 66.67 85.00 93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l 86.62 91.30 80.95 83.33 90.00 87.50
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present 89.13 93.02 86.67 83.33 88.89 93.75
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open 89.81 93.48 88.89 83.33 90.00 93.33
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb 89.89 93.48 88.89 83.33 90.00 93.75
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect 95.37 97.83 90.48 100.00 95.24 93.33
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect 95.37 97.83 90.48 100.00 95.24 93.33
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect 97.71 100.00 95.24 100.00 100.00 93.33
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre 97.99 100.00 94.74 100.00 95.24 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre 97.99 100.00 94.74 100.00 95.24 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre 97.99 100.00 94.74 100.00 95.24 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre 97.99 100.00 94.74 100.00 95.24 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect 99.05 100.00 95.24 100.00 100.00 100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
SCORELINE
85.00 89.13
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORELINE
89.89 93.48
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORELINE
81.85 89.13
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORELINE
85.00 89.13
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORELINE
85.00 89.13
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORELINE
81.85 89.13
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORELINE
81.85 89.13
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORELINE
86.62 91.30
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORELINE
81.85 89.13
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
219 1 1
220 1 1
222 1 1


Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
SCORELINE
89.81 93.48
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORELINE
81.68 89.13
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORELINE
81.68 89.13
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORELINE
81.68 89.13
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORELINE
84.92 89.13
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORELINE
84.92 89.13
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORELINE
84.92 89.13
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORELINE
84.92 89.13
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Line No.TotalCoveredPercent
TOTAL464393.48
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125322990.62
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
219 1 1
220 1 1
222 1 1


Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
SCORELINE
89.13 93.02
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Line No.TotalCoveredPercent
TOTAL434093.02
CONT_ASSIGN6011100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125322990.62
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
79 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
219 1 1
220 1 1
222 1 1


Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
SCORELINE
97.99 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORELINE
97.99 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORELINE
97.99 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORELINE
97.99 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Line No.TotalCoveredPercent
TOTAL4343100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
79 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
MISSING_ELSE
205 1 1
206 1 1
209 1 1
219 1 1
220 1 1
222 1 1


Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
SCORELINE
95.37 97.83
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORELINE
97.71 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORELINE
95.37 97.83
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORELINE
99.05 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
MISSING_ELSE
205 1 1
206 1 1
209 1 1
219 1 1
220 1 1
222 1 1


Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
SCORECOND
95.37 90.48
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORECOND
97.71 95.24
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORECOND
95.37 90.48
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORECOND
99.05 95.24
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

TotalCoveredPercent
Conditions2222100.00
Logical2222100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT17,T21,T22
1CoveredT16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT17,T21,T22
10CoveredT16,T17,T18
11CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT17,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT17,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT17,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT17,T21,T22
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT17,T21,T22
01CoveredT84,T85
10CoveredT84,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT17,T21,T22
01CoveredT17,T21,T22
10CoveredT84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT17,T21,T22
1-CoveredT17,T21,T22

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
SCORECOND
85.00 90.48
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORECOND
81.85 80.95
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORECOND
85.00 90.48
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORECOND
85.00 90.48
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORECOND
81.85 80.95
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORECOND
81.85 80.95
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORECOND
86.62 80.95
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORECOND
81.85 80.95
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT16,T17,T18
11CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT17,T39,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT17,T39,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT17,T39,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT17,T39,T21
10CoveredT16,T17,T18
11CoveredT17,T39,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT17,T39,T21
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT17,T39,T21
01CoveredT17,T39,T21
10CoveredT84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT17,T39,T21
1-CoveredT17,T39,T21

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
SCORECOND
97.99 94.74
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORECOND
97.99 94.74
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORECOND
97.99 94.74
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORECOND
97.99 94.74
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

TotalCoveredPercent
Conditions191894.74
Logical191894.74
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT84,T85
1CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT84,T85,T86

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT84,T85,T86

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT84,T85,T86

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT84,T85
10CoveredT84,T85
11CoveredT84,T85,T86

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT84,T85,T86
01CoveredT84,T85
10CoveredT84,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT84,T85,T86
01CoveredT84,T85
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT84,T85,T86
1-CoveredT84,T85

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
SCORECOND
89.13 86.67
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

TotalCoveredPercent
Conditions161487.50
Logical161487.50
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT16,T19,T20
10CoveredT16,T17,T18
11CoveredT16,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT16,T19,T20
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT16,T19,T20
01Unreachable
10CoveredT16,T19,T20

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
SCORECOND
81.68 80.95
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORECOND
81.68 80.95
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORECOND
81.68 80.95
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORECOND
84.92 90.48
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORECOND
84.92 90.48
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORECOND
84.92 90.48
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORECOND
84.92 90.48
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT16,T17,T18
11CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT17,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT17,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT17,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT17,T21,T22
10CoveredT16,T17,T18
11CoveredT17,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT17,T21,T22
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT17,T21,T22
01CoveredT17,T21,T22
10CoveredT84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT17,T21,T22
1-CoveredT17,T21,T22

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
SCORECOND
89.81 88.89
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

TotalCoveredPercent
Conditions191789.47
Logical191789.47
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT16,T17,T18
11CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT16,T19,T20
10CoveredT16,T17,T18
11CoveredT16,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT16,T19,T20
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT16,T19,T20
01Unreachable
10CoveredT16,T19,T20

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
SCORECOND
89.89 88.89
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

TotalCoveredPercent
Conditions191789.47
Logical191789.47
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT16,T17,T18
11CoveredT16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT16,T17,T18
1CoveredT16,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT16,T19,T20
10CoveredT16,T17,T18
11CoveredT16,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT16,T19,T20
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------
-1--2-StatusTests
00CoveredT16,T19,T20
01Unreachable
10CoveredT16,T19,T20

FSM Coverage for Module : sysrst_ctrl_detect
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T17,T39,T21
DetectSt 168 Covered T17,T39,T21
IdleSt 163 Covered T16,T17,T18
StableSt 191 Covered T17,T39,T21


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T17,T39,T21
DebounceSt->IdleSt 163 Covered T17,T21,T22
DetectSt->IdleSt 186 Covered T84,T85
DetectSt->StableSt 191 Covered T17,T39,T21
IdleSt->DebounceSt 148 Covered T17,T39,T21
StableSt->IdleSt 206 Covered T17,T39,T21



Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
SCOREBRANCH
85.00 85.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCOREBRANCH
81.85 85.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCOREBRANCH
85.00 85.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCOREBRANCH
85.00 85.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCOREBRANCH
81.85 85.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCOREBRANCH
81.85 85.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCOREBRANCH
86.62 90.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCOREBRANCH
81.85 85.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCOREBRANCH
89.89 90.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCOREBRANCH
89.81 90.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCOREBRANCH
81.68 85.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCOREBRANCH
81.68 85.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCOREBRANCH
81.68 85.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCOREBRANCH
84.92 85.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCOREBRANCH
84.92 85.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCOREBRANCH
84.92 85.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCOREBRANCH
84.92 85.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCOREBRANCH
95.37 95.24
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCOREBRANCH
97.71 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCOREBRANCH
95.37 95.24
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCOREBRANCH
99.05 100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Line No.TotalCoveredPercent
Branches 23 22 95.65
TERNARY 92 3 3 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 12 11 91.67
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTests
1 - Covered T17,T39,T21
0 1 Covered T17,T39,T21
0 0 Covered T16,T17,T18


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T17,T39,T21
0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
IdleSt 1 - - - - - - Covered T17,T39,T21
IdleSt 0 - - - - - - Covered T16,T17,T18
DebounceSt - 1 - - - - - Covered T84,T85
DebounceSt - 0 1 1 - - - Covered T17,T39,T21
DebounceSt - 0 1 0 - - - Covered T17,T21,T22
DebounceSt - 0 0 - - - - Covered T17,T39,T21
DetectSt - - - - 1 - - Covered T84,T85
DetectSt - - - - 0 1 - Covered T17,T39,T21
DetectSt - - - - 0 0 - Covered T17,T21,T22
StableSt - - - - - - 1 Covered T17,T39,T21
StableSt - - - - - - 0 Covered T17,T39,T21
default - - - - - - - Not Covered


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
SCOREBRANCH
89.13 88.89
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCOREBRANCH
97.99 95.24
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCOREBRANCH
97.99 95.24
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCOREBRANCH
97.99 95.24
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCOREBRANCH
97.99 95.24
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 92 3 3 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 12 11 91.67
IF 219 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTests
1 - Covered T16,T19,T20
0 1 Covered T16,T19,T20
0 0 Covered T16,T17,T18


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T16,T19,T20
0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
IdleSt 1 - - - - - - Covered T16,T19,T20
IdleSt 0 - - - - - - Covered T16,T17,T18
DebounceSt - 1 - - - - - Covered T84,T85
DebounceSt - 0 1 1 - - - Covered T16,T19,T20
DebounceSt - 0 1 0 - - - Covered T84,T85
DebounceSt - 0 0 - - - - Covered T16,T19,T20
DetectSt - - - - 1 - - Covered T84,T85
DetectSt - - - - 0 1 - Covered T16,T19,T20
DetectSt - - - - 0 0 - Covered T84,T85,T86
StableSt - - - - - - 1 Covered T16,T19,T20
StableSt - - - - - - 0 Covered T16,T19,T20
default - - - - - - - Not Covered


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T16,T17,T18


Assert Coverage for Module : sysrst_ctrl_detect
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 19 19 100.00 19 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 19 19 100.00 19 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 63017032 4594 0 0
CntIncr_A 63017032 222867 0 0
CntNoWrap_A 63017032 52826496 0 0
DetectStDropOut_A 63017032 10 0 0
DetectedOut_A 63017032 106524 0 0
DetectedPulseOut_A 63017032 2143 0 0
DisabledIdleSt_A 63017032 50610382 0 0
DisabledNoDetection_A 63017032 50643559 0 0
EnterDebounceSt_A 63017032 2419 0 0
EnterDetectSt_A 63017032 2175 0 0
EnterStableSt_A 63017032 2143 0 0
PulseIsPulse_A 63017032 2143 0 0
StayInStableSt 63017032 104026 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 21813588 25100 0 0
gen_high_event_sva.HighLevelEvent_A 12118660 10166910 0 0
gen_high_level_sva.HighLevelEvent_A 41203444 34567494 0 0
gen_low_level_sva.LowLevelEvent_A 21813588 18300438 0 0
gen_not_sticky_sva.StableStDropOut_A 55745836 1600 0 0
gen_sticky_sva.StableStDropOut_A 7271196 9600 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63017032 4594 0 0
T17 17445 4 0 0
T18 414 0 0 0
T21 34890 4 0 0
T22 34890 4 0 0
T23 34890 4 0 0
T24 817 0 0 0
T29 0 4 0 0
T35 17445 4 0 0
T38 8403 0 0 0
T39 1254 4 0 0
T40 828 0 0 0
T41 1254 4 0 0
T42 1006 0 0 0
T83 0 4 0 0
T84 7721 26 0 0
T85 7721 18 0 0
T86 0 2 0 0
T87 0 4 0 0
T88 0 4 0 0
T89 0 4 0 0
T90 0 4 0 0
T91 0 4 0 0
T92 0 2 0 0
T93 414 0 0 0
T94 414 0 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T112 0 4 0 0
T113 0 4 0 0
T114 0 4 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63017032 222867 0 0
T17 17445 170 0 0
T18 414 0 0 0
T21 34890 170 0 0
T22 34890 170 0 0
T23 34890 170 0 0
T24 817 0 0 0
T29 0 170 0 0
T35 17445 170 0 0
T38 8403 0 0 0
T39 1254 81 0 0
T40 828 0 0 0
T41 1254 81 0 0
T42 1006 0 0 0
T83 0 81 0 0
T84 7721 838 0 0
T85 7721 624 0 0
T86 0 21 0 0
T87 0 81 0 0
T88 0 81 0 0
T89 0 81 0 0
T90 0 81 0 0
T91 0 81 0 0
T92 0 21 0 0
T93 414 0 0 0
T94 414 0 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T112 0 170 0 0
T113 0 170 0 0
T114 0 170 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63017032 52826496 0 0
T16 26962 16530 0 0
T17 453570 390377 0 0
T18 10764 338 0 0
T21 453570 390377 0 0
T22 453570 390377 0 0
T23 453570 390377 0 0
T38 218478 52 0 0
T39 16302 5872 0 0
T40 10764 338 0 0
T41 16302 5872 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63017032 10 0 0
T35 87225 0 0 0
T84 38605 5 0 0
T85 38605 5 0 0
T95 2470 0 0 0
T96 2115 0 0 0
T97 2470 0 0 0
T98 87225 0 0 0
T99 2615 0 0 0
T110 2515 0 0 0
T111 4085 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63017032 106524 0 0
T17 17445 152 0 0
T18 414 0 0 0
T21 34890 152 0 0
T22 34890 152 0 0
T23 34890 152 0 0
T24 817 0 0 0
T29 0 152 0 0
T35 17445 152 0 0
T38 8403 0 0 0
T39 1254 8 0 0
T40 828 0 0 0
T41 1254 8 0 0
T42 1006 0 0 0
T83 0 8 0 0
T84 7721 443 0 0
T85 7721 365 0 0
T86 0 80 0 0
T87 0 8 0 0
T88 0 8 0 0
T89 0 8 0 0
T90 0 8 0 0
T91 0 8 0 0
T92 0 80 0 0
T93 414 0 0 0
T94 414 0 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T112 0 152 0 0
T113 0 152 0 0
T114 0 152 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63017032 2143 0 0
T17 17445 2 0 0
T18 414 0 0 0
T21 34890 2 0 0
T22 34890 2 0 0
T23 34890 2 0 0
T24 817 0 0 0
T29 0 2 0 0
T35 17445 2 0 0
T38 8403 0 0 0
T39 1254 2 0 0
T40 828 0 0 0
T41 1254 2 0 0
T42 1006 0 0 0
T83 0 2 0 0
T84 7721 7 0 0
T85 7721 6 0 0
T86 0 1 0 0
T87 0 2 0 0
T88 0 2 0 0
T89 0 2 0 0
T90 0 2 0 0
T91 0 2 0 0
T92 0 1 0 0
T93 414 0 0 0
T94 414 0 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T112 0 2 0 0
T113 0 2 0 0
T114 0 2 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63017032 50610382 0 0
T16 26962 15765 0 0
T17 453570 370795 0 0
T18 10764 338 0 0
T21 453570 370795 0 0
T22 453570 370795 0 0
T23 453570 370795 0 0
T38 218478 52 0 0
T39 16302 5700 0 0
T40 10764 338 0 0
T41 16302 5700 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63017032 50643559 0 0
T16 26962 15791 0 0
T17 453570 371000 0 0
T18 10764 364 0 0
T21 453570 371000 0 0
T22 453570 371000 0 0
T23 453570 371000 0 0
T38 218478 78 0 0
T39 16302 5726 0 0
T40 10764 364 0 0
T41 16302 5726 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63017032 2419 0 0
T17 17445 2 0 0
T18 414 0 0 0
T21 34890 2 0 0
T22 34890 2 0 0
T23 34890 2 0 0
T24 817 0 0 0
T29 0 2 0 0
T35 17445 2 0 0
T38 8403 0 0 0
T39 1254 2 0 0
T40 828 0 0 0
T41 1254 2 0 0
T42 1006 0 0 0
T83 0 2 0 0
T84 7721 15 0 0
T85 7721 10 0 0
T86 0 1 0 0
T87 0 2 0 0
T88 0 2 0 0
T89 0 2 0 0
T90 0 2 0 0
T91 0 2 0 0
T92 0 1 0 0
T93 414 0 0 0
T94 414 0 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T112 0 2 0 0
T113 0 2 0 0
T114 0 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63017032 2175 0 0
T17 17445 2 0 0
T18 414 0 0 0
T21 34890 2 0 0
T22 34890 2 0 0
T23 34890 2 0 0
T24 817 0 0 0
T29 0 2 0 0
T35 17445 2 0 0
T38 8403 0 0 0
T39 1254 2 0 0
T40 828 0 0 0
T41 1254 2 0 0
T42 1006 0 0 0
T83 0 2 0 0
T84 7721 11 0 0
T85 7721 8 0 0
T86 0 1 0 0
T87 0 2 0 0
T88 0 2 0 0
T89 0 2 0 0
T90 0 2 0 0
T91 0 2 0 0
T92 0 1 0 0
T93 414 0 0 0
T94 414 0 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T112 0 2 0 0
T113 0 2 0 0
T114 0 2 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63017032 2143 0 0
T17 17445 2 0 0
T18 414 0 0 0
T21 34890 2 0 0
T22 34890 2 0 0
T23 34890 2 0 0
T24 817 0 0 0
T29 0 2 0 0
T35 17445 2 0 0
T38 8403 0 0 0
T39 1254 2 0 0
T40 828 0 0 0
T41 1254 2 0 0
T42 1006 0 0 0
T83 0 2 0 0
T84 7721 7 0 0
T85 7721 6 0 0
T86 0 1 0 0
T87 0 2 0 0
T88 0 2 0 0
T89 0 2 0 0
T90 0 2 0 0
T91 0 2 0 0
T92 0 1 0 0
T93 414 0 0 0
T94 414 0 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T112 0 2 0 0
T113 0 2 0 0
T114 0 2 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 63017032 2143 0 0
T17 17445 2 0 0
T18 414 0 0 0
T21 34890 2 0 0
T22 34890 2 0 0
T23 34890 2 0 0
T24 817 0 0 0
T29 0 2 0 0
T35 17445 2 0 0
T38 8403 0 0 0
T39 1254 2 0 0
T40 828 0 0 0
T41 1254 2 0 0
T42 1006 0 0 0
T83 0 2 0 0
T84 7721 7 0 0
T85 7721 6 0 0
T86 0 1 0 0
T87 0 2 0 0
T88 0 2 0 0
T89 0 2 0 0
T90 0 2 0 0
T91 0 2 0 0
T92 0 1 0 0
T93 414 0 0 0
T94 414 0 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T112 0 2 0 0
T113 0 2 0 0
T114 0 2 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 63017032 104026 0 0
T17 17445 150 0 0
T18 414 0 0 0
T21 34890 150 0 0
T22 34890 150 0 0
T23 34890 150 0 0
T24 817 0 0 0
T29 0 150 0 0
T35 17445 150 0 0
T38 8403 0 0 0
T39 1254 6 0 0
T40 828 0 0 0
T41 1254 6 0 0
T42 1006 0 0 0
T83 0 6 0 0
T84 7721 436 0 0
T85 7721 359 0 0
T86 0 78 0 0
T87 0 6 0 0
T88 0 6 0 0
T89 0 6 0 0
T90 0 6 0 0
T91 0 6 0 0
T92 0 78 0 0
T93 414 0 0 0
T94 414 0 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 0 0 0
T99 523 0 0 0
T112 0 150 0 0
T113 0 150 0 0
T114 0 150 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21813588 25100 0 0
T16 4148 20 0 0
T17 157005 204 0 0
T18 3726 6 0 0
T21 157005 204 0 0
T22 157005 204 0 0
T23 157005 204 0 0
T24 0 7 0 0
T25 0 2 0 0
T38 75627 0 0 0
T39 5643 9 0 0
T40 3726 6 0 0
T41 5643 9 0 0
T42 2515 42 0 0
T47 0 22 0 0
T53 0 10 0 0
T93 0 3 0 0
T94 0 3 0 0
T115 0 5 0 0

gen_high_event_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12118660 10166910 0 0
T16 5185 3185 0 0
T17 87225 75125 0 0
T18 2070 70 0 0
T21 87225 75125 0 0
T22 87225 75125 0 0
T23 87225 75125 0 0
T38 42015 15 0 0
T39 3135 1135 0 0
T40 2070 70 0 0
T41 3135 1135 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 41203444 34567494 0 0
T16 17629 10829 0 0
T17 296565 255425 0 0
T18 7038 238 0 0
T21 296565 255425 0 0
T22 296565 255425 0 0
T23 296565 255425 0 0
T38 142851 51 0 0
T39 10659 3859 0 0
T40 7038 238 0 0
T41 10659 3859 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 21813588 18300438 0 0
T16 9333 5733 0 0
T17 157005 135225 0 0
T18 3726 126 0 0
T21 157005 135225 0 0
T22 157005 135225 0 0
T23 157005 135225 0 0
T38 75627 27 0 0
T39 5643 2043 0 0
T40 3726 126 0 0
T41 5643 2043 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55745836 1600 0 0
T17 17445 2 0 0
T18 414 0 0 0
T21 34890 2 0 0
T22 34890 2 0 0
T23 34890 2 0 0
T24 817 0 0 0
T29 0 2 0 0
T35 17445 2 0 0
T38 8403 0 0 0
T39 1254 2 0 0
T40 828 0 0 0
T41 1254 2 0 0
T42 1006 0 0 0
T83 0 2 0 0
T84 7721 5 0 0
T85 7721 0 0 0
T87 0 2 0 0
T88 0 2 0 0
T89 0 2 0 0
T90 0 2 0 0
T91 0 2 0 0
T93 414 0 0 0
T94 414 0 0 0
T95 494 0 0 0
T96 423 0 0 0
T97 494 0 0 0
T98 17445 2 0 0
T99 523 0 0 0
T112 0 2 0 0
T113 0 2 0 0
T114 0 2 0 0
T116 0 2 0 0
T117 0 2 0 0

gen_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7271196 9600 0 0
T16 3111 192 0 0
T17 52335 0 0 0
T18 1242 0 0 0
T19 0 192 0 0
T20 0 192 0 0
T21 52335 0 0 0
T22 52335 0 0 0
T23 52335 0 0 0
T32 0 192 0 0
T36 0 192 0 0
T37 0 192 0 0
T38 25209 0 0 0
T39 1881 0 0 0
T40 1242 0 0 0
T41 1881 0 0 0
T43 0 192 0 0
T44 0 192 0 0
T45 0 192 0 0
T46 0 192 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%