Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T17,T21
1	0	Covered	T16,T17,T21
1	1	Covered	T16,T19,T20

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T17,T21
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T17,T21

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	125837	0	0
SrcPulseCheck_M	2147483647	127146	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	125837
T17	4047448	80
T18	932720	0
T21	5059310	80
T22	5059310	80
T23	5059310	80
T24	408094	0
T27	0	144
T29	0	80
T31	0	144
T33	0	144
T34	0	144
T35	488486	0
T38	1949672	0
T39	1764100	16
T40	1165900	0
T41	1764100	16
T42	1413660	0
T83	0	16
T84	215076	159
T85	215076	15
T86	0	1
T87	0	16
T88	0	16
T89	0	16
T90	0	16
T91	0	16
T92	0	1
T93	233180	0
T94	233180	0
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	127146
T17	4047448	80
T18	932720	0
T21	5059310	80
T22	5059310	80
T23	5059310	80
T24	408094	0
T27	0	144
T29	0	80
T31	0	144
T33	0	144
T34	0	144
T35	17445	0
T38	1949672	0
T39	1764100	16
T40	1165900	0
T41	1764100	16
T42	1413660	0
T83	0	16
T84	7721	159
T85	7721	15
T86	0	1
T87	0	16
T88	0	16
T89	0	16
T90	0	16
T91	0	16
T92	0	1
T93	233180	0
T94	233180	0
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T54,T55,T13

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T54,T55,T13
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1932	0	0
SrcPulseCheck_M	754515696	1962	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1932
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T100	0	1
T101	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1962
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T100	0	1
T101	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T54,T55,T13

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T54,T55,T13
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1932	0	0
SrcPulseCheck_M	2727417	1932	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1932
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T100	0	1
T101	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1932
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T100	0	1
T101	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1147	0	0
SrcPulseCheck_M	754515696	1197	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1147
T16	1037	2
T17	17445	0
T18	414	0
T19	0	2
T20	0	2
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	2
T36	0	2
T37	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	2
T44	0	2
T84	0	1
T85	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1197
T16	130789	2
T17	488486	0
T18	116176	0
T19	0	2
T20	0	2
T21	488486	0
T22	488486	0
T23	488486	0
T32	0	2
T36	0	2
T37	0	2
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T43	0	2
T44	0	2
T84	0	1
T85	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1147	0	0
SrcPulseCheck_M	2727417	1147	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1147
T16	130789	2
T17	488486	0
T18	116176	0
T19	0	2
T20	0	2
T21	488486	0
T22	488486	0
T23	488486	0
T32	0	2
T36	0	2
T37	0	2
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T43	0	2
T44	0	2
T84	0	1
T85	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1147
T16	1037	2
T17	17445	0
T18	414	0
T19	0	2
T20	0	2
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	2
T36	0	2
T37	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	2
T44	0	2
T84	0	1
T85	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1012	0	0
SrcPulseCheck_M	754515696	1042	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1012
T16	1037	2
T17	17445	0
T18	414	0
T19	0	2
T20	0	2
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	2
T36	0	2
T37	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	2
T44	0	2
T84	0	1
T85	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1042
T16	130789	2
T17	488486	0
T18	116176	0
T19	0	2
T20	0	2
T21	488486	0
T22	488486	0
T23	488486	0
T32	0	2
T36	0	2
T37	0	2
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T43	0	2
T44	0	2
T84	0	1
T85	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1012	0	0
SrcPulseCheck_M	2727417	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1012
T16	130789	2
T17	488486	0
T18	116176	0
T19	0	2
T20	0	2
T21	488486	0
T22	488486	0
T23	488486	0
T32	0	2
T36	0	2
T37	0	2
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T43	0	2
T44	0	2
T84	0	1
T85	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1012
T16	1037	2
T17	17445	0
T18	414	0
T19	0	2
T20	0	2
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	2
T36	0	2
T37	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	2
T44	0	2
T84	0	1
T85	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1147	0	0
SrcPulseCheck_M	754515696	1177	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1147
T16	1037	2
T17	17445	0
T18	414	0
T19	0	2
T20	0	2
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	2
T36	0	2
T37	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	2
T44	0	2
T84	0	1
T85	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1177
T16	130789	2
T17	488486	0
T18	116176	0
T19	0	2
T20	0	2
T21	488486	0
T22	488486	0
T23	488486	0
T32	0	2
T36	0	2
T37	0	2
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T43	0	2
T44	0	2
T84	0	1
T85	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1147	0	0
SrcPulseCheck_M	2727417	1147	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1147
T16	130789	2
T17	488486	0
T18	116176	0
T19	0	2
T20	0	2
T21	488486	0
T22	488486	0
T23	488486	0
T32	0	2
T36	0	2
T37	0	2
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T43	0	2
T44	0	2
T84	0	1
T85	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1147
T16	1037	2
T17	17445	0
T18	414	0
T19	0	2
T20	0	2
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	2
T36	0	2
T37	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	2
T44	0	2
T84	0	1
T85	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1238	0	0
SrcPulseCheck_M	754515696	1268	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1238
T16	1037	2
T17	17445	0
T18	414	0
T19	0	2
T20	0	2
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	2
T36	0	2
T37	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	2
T44	0	2
T84	0	4
T85	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1268
T16	130789	2
T17	488486	0
T18	116176	0
T19	0	2
T20	0	2
T21	488486	0
T22	488486	0
T23	488486	0
T32	0	2
T36	0	2
T37	0	2
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T43	0	2
T44	0	2
T84	0	4
T85	0	4

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T16,T19,T20

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1238	0	0
SrcPulseCheck_M	2727417	1238	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1238
T16	130789	2
T17	488486	0
T18	116176	0
T19	0	2
T20	0	2
T21	488486	0
T22	488486	0
T23	488486	0
T32	0	2
T36	0	2
T37	0	2
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T43	0	2
T44	0	2
T84	0	4
T85	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1238
T16	1037	2
T17	17445	0
T18	414	0
T19	0	2
T20	0	2
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	2
T36	0	2
T37	0	2
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	2
T44	0	2
T84	0	4
T85	0	4

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T16,T19,T20
1	1	Covered	T54,T55,T13

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T19,T20
1	0	Covered	T54,T55,T13
1	1	Covered	T16,T19,T20

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	800	0	0
SrcPulseCheck_M	754515696	830	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	800
T16	1037	1
T17	17445	0
T18	414	0
T19	0	1
T20	0	1
T21	17445	0
T22	17445	0
T23	17445	0
T32	0	1
T36	0	1
T37	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T43	0	1
T44	0	1
T45	0	1
T46	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	830
T16	130789	1
T17	488486	0
T18	116176	0
T19	0	1
T20	0	1
T21	488486	0
T22	488486	0
T23	488486	0
T32	0	1
T36	0	1
T37	0	1
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T43	0	1
T44	0	1
T45	0	1
T46	0	1

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T17,T21
1	0	Covered	T16,T17,T21
1	1	Covered	T17,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T17,T21
1	0	Covered	T17,T21,T22
1	1	Covered	T16,T17,T21

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1510	0	0
SrcPulseCheck_M	754515696	1552	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1510
T16	1037	1
T17	17445	7
T18	414	0
T19	0	1
T20	0	1
T21	17445	7
T22	17445	7
T23	17445	7
T27	0	8
T29	0	7
T31	0	8
T38	8403	0
T39	627	0
T40	414	0
T41	627	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1552
T16	130789	1
T17	488486	7
T18	116176	0
T19	0	1
T20	0	1
T21	488486	7
T22	488486	7
T23	488486	7
T27	0	8
T29	0	7
T31	0	8
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	3105	0	0
SrcPulseCheck_M	754515696	3135	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	3105
T17	17445	20
T18	414	0
T21	17445	20
T22	17445	20
T23	17445	20
T29	0	20
T35	0	20
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T47	0	20
T95	0	20
T102	0	20
T103	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	3135
T17	488486	20
T18	116176	0
T21	488486	20
T22	488486	20
T23	488486	20
T29	0	20
T35	0	20
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T47	0	20
T95	0	20
T102	0	20
T103	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	3105	0	0
SrcPulseCheck_M	2727417	3105	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	3105
T17	488486	20
T18	116176	0
T21	488486	20
T22	488486	20
T23	488486	20
T29	0	20
T35	0	20
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T47	0	20
T95	0	20
T102	0	20
T103	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	3105
T17	17445	20
T18	414	0
T21	17445	20
T22	17445	20
T23	17445	20
T29	0	20
T35	0	20
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T47	0	20
T95	0	20
T102	0	20
T103	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	5170	0	0
SrcPulseCheck_M	754515696	5200	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	5170
T17	17445	41
T18	414	0
T21	17445	41
T22	17445	41
T23	17445	41
T29	0	41
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	20
T47	0	1
T53	0	20
T104	0	20
T105	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	5200
T17	488486	41
T18	116176	0
T21	488486	41
T22	488486	41
T23	488486	41
T29	0	41
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	20
T47	0	1
T53	0	20
T104	0	20
T105	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	5170	0	0
SrcPulseCheck_M	2727417	5170	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	5170
T17	488486	41
T18	116176	0
T21	488486	41
T22	488486	41
T23	488486	41
T29	0	41
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	20
T47	0	1
T53	0	20
T104	0	20
T105	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	5170
T17	17445	41
T18	414	0
T21	17445	41
T22	17445	41
T23	17445	41
T29	0	41
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	20
T47	0	1
T53	0	20
T104	0	20
T105	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	5967	0	0
SrcPulseCheck_M	754515696	5997	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	5967
T17	17445	46
T18	414	0
T21	17445	46
T22	17445	46
T23	17445	46
T27	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	20
T47	0	1
T53	0	20
T104	0	20
T105	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	5997
T17	488486	46
T18	116176	0
T21	488486	46
T22	488486	46
T23	488486	46
T27	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	20
T47	0	1
T53	0	20
T104	0	20
T105	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	5967	0	0
SrcPulseCheck_M	2727417	5967	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	5967
T17	488486	46
T18	116176	0
T21	488486	46
T22	488486	46
T23	488486	46
T27	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	20
T47	0	1
T53	0	20
T104	0	20
T105	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	5967
T17	17445	46
T18	414	0
T21	17445	46
T22	17445	46
T23	17445	46
T27	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	20
T47	0	1
T53	0	20
T104	0	20
T105	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	4925	0	0
SrcPulseCheck_M	754515696	4955	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	4925
T17	17445	40
T18	414	0
T21	17445	40
T22	17445	40
T23	17445	40
T29	0	40
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	20
T53	0	20
T104	0	20
T105	0	20
T106	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	4955
T17	488486	40
T18	116176	0
T21	488486	40
T22	488486	40
T23	488486	40
T29	0	40
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	20
T53	0	20
T104	0	20
T105	0	20
T106	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	4925	0	0
SrcPulseCheck_M	2727417	4925	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	4925
T17	488486	40
T18	116176	0
T21	488486	40
T22	488486	40
T23	488486	40
T29	0	40
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	20
T53	0	20
T104	0	20
T105	0	20
T106	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	4925
T17	17445	40
T18	414	0
T21	17445	40
T22	17445	40
T23	17445	40
T29	0	40
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	20
T53	0	20
T104	0	20
T105	0	20
T106	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1246	0	0
SrcPulseCheck_M	754515696	1276	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1246
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	1
T25	0	1
T26	0	1
T28	0	1
T29	0	1
T30	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1276
T17	488486	1
T18	116176	0
T21	488486	1
T22	488486	1
T23	488486	1
T24	0	1
T25	0	1
T26	0	1
T28	0	1
T29	0	1
T30	0	1
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1246	0	0
SrcPulseCheck_M	2727417	1246	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1246
T17	488486	1
T18	116176	0
T21	488486	1
T22	488486	1
T23	488486	1
T24	0	1
T25	0	1
T26	0	1
T28	0	1
T29	0	1
T30	0	1
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1246
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	1
T25	0	1
T26	0	1
T28	0	1
T29	0	1
T30	0	1
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1924	0	0
SrcPulseCheck_M	754515696	1974	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1924
T17	17445	6
T18	414	0
T21	17445	6
T22	17445	6
T23	17445	6
T24	0	1
T25	0	1
T26	0	1
T27	0	9
T28	0	1
T29	0	6
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1974
T17	488486	6
T18	116176	0
T21	488486	6
T22	488486	6
T23	488486	6
T24	0	1
T25	0	1
T26	0	1
T27	0	9
T28	0	1
T29	0	6
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1924	0	0
SrcPulseCheck_M	2727417	1924	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1924
T17	488486	6
T18	116176	0
T21	488486	6
T22	488486	6
T23	488486	6
T24	0	1
T25	0	1
T26	0	1
T27	0	9
T28	0	1
T29	0	6
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1924
T17	17445	6
T18	414	0
T21	17445	6
T22	17445	6
T23	17445	6
T24	0	1
T25	0	1
T26	0	1
T27	0	9
T28	0	1
T29	0	6
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T39,T41,T83
1	0	Covered	T39,T41,T83
1	1	Covered	T39,T41,T83

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T39,T41,T83
1	0	Covered	T39,T41,T83
1	1	Covered	T39,T41,T83

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1254	0	0
SrcPulseCheck_M	754515696	1289	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1254
T21	17445	0
T22	17445	0
T23	17445	0
T24	817	0
T39	627	5
T40	414	0
T41	627	5
T42	503	0
T83	0	5
T84	0	2
T85	0	2
T87	0	5
T88	0	5
T89	0	5
T90	0	5
T91	0	5
T93	414	0
T94	414	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1289
T21	488486	0
T22	488486	0
T23	488486	0
T24	203230	0
T39	175783	5
T40	116176	0
T41	175783	5
T42	140863	0
T83	0	5
T84	0	2
T85	0	2
T87	0	5
T88	0	5
T89	0	5
T90	0	5
T91	0	5
T93	116176	0
T94	116176	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T39,T41,T83
1	0	Covered	T39,T41,T83
1	1	Covered	T39,T41,T83

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T39,T41,T83
1	0	Covered	T39,T41,T83
1	1	Covered	T39,T41,T83

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1259	0	0
SrcPulseCheck_M	2727417	1259	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1259
T21	488486	0
T22	488486	0
T23	488486	0
T24	203230	0
T39	175783	5
T40	116176	0
T41	175783	5
T42	140863	0
T83	0	5
T84	0	2
T85	0	2
T87	0	5
T88	0	5
T89	0	5
T90	0	5
T91	0	5
T93	116176	0
T94	116176	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1259
T21	17445	0
T22	17445	0
T23	17445	0
T24	817	0
T39	627	5
T40	414	0
T41	627	5
T42	503	0
T83	0	5
T84	0	2
T85	0	2
T87	0	5
T88	0	5
T89	0	5
T90	0	5
T91	0	5
T93	414	0
T94	414	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T39,T41,T83
1	0	Covered	T39,T41,T83
1	1	Covered	T39,T41,T83

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T39,T41,T83
1	0	Covered	T39,T41,T83
1	1	Covered	T39,T41,T83

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1192	0	0
SrcPulseCheck_M	754515696	1222	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1192
T21	17445	0
T22	17445	0
T23	17445	0
T24	817	0
T39	627	3
T40	414	0
T41	627	3
T42	503	0
T83	0	3
T84	0	1
T85	0	1
T87	0	3
T88	0	3
T89	0	3
T90	0	3
T91	0	3
T93	414	0
T94	414	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1222
T21	488486	0
T22	488486	0
T23	488486	0
T24	203230	0
T39	175783	3
T40	116176	0
T41	175783	3
T42	140863	0
T83	0	3
T84	0	1
T85	0	1
T87	0	3
T88	0	3
T89	0	3
T90	0	3
T91	0	3
T93	116176	0
T94	116176	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T39,T41,T83
1	0	Covered	T39,T41,T83
1	1	Covered	T39,T41,T83

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T39,T41,T83
1	0	Covered	T39,T41,T83
1	1	Covered	T39,T41,T83

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1192	0	0
SrcPulseCheck_M	2727417	1192	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1192
T21	488486	0
T22	488486	0
T23	488486	0
T24	203230	0
T39	175783	3
T40	116176	0
T41	175783	3
T42	140863	0
T83	0	3
T84	0	1
T85	0	1
T87	0	3
T88	0	3
T89	0	3
T90	0	3
T91	0	3
T93	116176	0
T94	116176	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1192
T21	17445	0
T22	17445	0
T23	17445	0
T24	817	0
T39	627	3
T40	414	0
T41	627	3
T42	503	0
T83	0	3
T84	0	1
T85	0	1
T87	0	3
T88	0	3
T89	0	3
T90	0	3
T91	0	3
T93	414	0
T94	414	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T86
1	0	Covered	T84,T85,T86
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T86
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T86

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1052	0	0
SrcPulseCheck_M	754515696	1102	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1052
T1	0	19
T35	17445	0
T54	0	2
T55	0	2
T84	7721	11
T85	7721	11
T86	0	1
T92	0	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T107	0	1
T108	0	1
T109	0	1
T110	503	0
T111	817	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1102
T1	0	19
T35	488486	0
T54	0	2
T55	0	2
T84	215076	11
T85	215076	11
T86	0	1
T92	0	1
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T107	0	1
T108	0	1
T109	0	1
T110	140863	0
T111	203230	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T86
1	0	Covered	T84,T85,T86
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T86
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T86

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1052	0	0
SrcPulseCheck_M	2727417	1052	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1052
T1	0	19
T35	488486	0
T54	0	2
T55	0	2
T84	215076	11
T85	215076	11
T86	0	1
T92	0	1
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T107	0	1
T108	0	1
T109	0	1
T110	140863	0
T111	203230	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1052
T1	0	19
T35	17445	0
T54	0	2
T55	0	2
T84	7721	11
T85	7721	11
T86	0	1
T92	0	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T107	0	1
T108	0	1
T109	0	1
T110	503	0
T111	817	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	982	0	0
SrcPulseCheck_M	754515696	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	982
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	17445	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	7721	11
T85	7721	11
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1012
T1	0	20
T7	0	1
T13	0	2
T14	0	2
T35	488486	0
T52	0	2
T54	0	2
T55	0	2
T56	0	2
T84	215076	11
T85	215076	11
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T110	140863	0
T111	203230	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	982	0	0
SrcPulseCheck_M	2727417	982	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	982
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	488486	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	215076	11
T85	215076	11
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T110	140863	0
T111	203230	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	982
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	17445	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	7721	11
T85	7721	11
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1127	0	0
SrcPulseCheck_M	754515696	1177	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1127
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	17445	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	7721	11
T85	7721	11
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1177
T1	0	20
T7	0	2
T13	0	2
T14	0	2
T35	488486	0
T52	0	2
T54	0	2
T55	0	2
T56	0	2
T84	215076	11
T85	215076	11
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T110	140863	0
T111	203230	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1127	0	0
SrcPulseCheck_M	2727417	1127	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1127
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	488486	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	215076	11
T85	215076	11
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T110	140863	0
T111	203230	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1127
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	17445	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	7721	11
T85	7721	11
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1012	0	0
SrcPulseCheck_M	754515696	1042	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1012
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	17445	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	7721	11
T85	7721	11
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1042
T1	0	20
T7	0	1
T13	0	2
T14	0	2
T35	488486	0
T52	0	2
T54	0	2
T55	0	2
T56	0	2
T84	215076	11
T85	215076	11
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T110	140863	0
T111	203230	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1012	0	0
SrcPulseCheck_M	2727417	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1012
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	488486	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	215076	11
T85	215076	11
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T110	140863	0
T111	203230	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1012
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	17445	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	7721	11
T85	7721	11
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T86
1	0	Covered	T84,T85,T86
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T86
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T86

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1023	0	0
SrcPulseCheck_M	754515696	1053	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1023
T1	0	20
T35	17445	0
T54	0	2
T55	0	2
T84	7721	9
T85	7721	9
T86	0	1
T92	0	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T107	0	1
T108	0	1
T109	0	1
T110	503	0
T111	817	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1053
T1	0	20
T35	488486	0
T54	0	2
T55	0	2
T84	215076	9
T85	215076	9
T86	0	1
T92	0	1
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T107	0	1
T108	0	1
T109	0	1
T110	140863	0
T111	203230	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T86
1	0	Covered	T84,T85,T86
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T86
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T86

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1023	0	0
SrcPulseCheck_M	2727417	1023	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1023
T1	0	20
T35	488486	0
T54	0	2
T55	0	2
T84	215076	9
T85	215076	9
T86	0	1
T92	0	1
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T107	0	1
T108	0	1
T109	0	1
T110	140863	0
T111	203230	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1023
T1	0	20
T35	17445	0
T54	0	2
T55	0	2
T84	7721	9
T85	7721	9
T86	0	1
T92	0	1
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T107	0	1
T108	0	1
T109	0	1
T110	503	0
T111	817	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1123	0	0
SrcPulseCheck_M	754515696	1173	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1123
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	17445	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	7721	9
T85	7721	9
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1173
T1	0	20
T7	0	2
T13	0	2
T14	0	2
T35	488486	0
T52	0	2
T54	0	2
T55	0	2
T56	0	2
T84	215076	9
T85	215076	9
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T110	140863	0
T111	203230	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1123	0	0
SrcPulseCheck_M	2727417	1123	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1123
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	488486	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	215076	9
T85	215076	9
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T110	140863	0
T111	203230	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1123
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	17445	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	7721	9
T85	7721	9
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1118	0	0
SrcPulseCheck_M	754515696	1168	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1118
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	17445	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	7721	9
T85	7721	9
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1168
T1	0	20
T7	0	2
T13	0	2
T14	0	2
T35	488486	0
T52	0	2
T54	0	2
T55	0	2
T56	0	2
T84	215076	9
T85	215076	9
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T110	140863	0
T111	203230	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1118	0	0
SrcPulseCheck_M	2727417	1118	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1118
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	488486	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	215076	9
T85	215076	9
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T110	140863	0
T111	203230	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1118
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	17445	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	7721	9
T85	7721	9
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1048	0	0
SrcPulseCheck_M	754515696	1078	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1048
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	17445	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	7721	9
T85	7721	9
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1078
T1	0	20
T7	0	1
T13	0	2
T14	0	2
T35	488486	0
T52	0	2
T54	0	2
T55	0	2
T56	0	2
T84	215076	9
T85	215076	9
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T110	140863	0
T111	203230	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T84,T85,T54
1	0	Covered	T84,T85,T54
1	1	Covered	T84,T85,T54

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1048	0	0
SrcPulseCheck_M	2727417	1048	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1048
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	488486	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	215076	9
T85	215076	9
T95	138342	0
T96	118546	0
T97	138342	0
T98	488486	0
T99	146706	0
T110	140863	0
T111	203230	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1048
T1	0	20
T8	0	20
T13	0	2
T14	0	2
T35	17445	0
T52	0	2
T54	0	2
T55	0	2
T57	0	2
T84	7721	9
T85	7721	9
T95	494	0
T96	423	0
T97	494	0
T98	17445	0
T99	523	0
T110	503	0
T111	817	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1777	0	0
SrcPulseCheck_M	754515696	1827	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1777
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1827
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1777	0	0
SrcPulseCheck_M	2727417	1777	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1777
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1777
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1597	0	0
SrcPulseCheck_M	754515696	1627	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1597
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1627
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1597	0	0
SrcPulseCheck_M	2727417	1597	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1597
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1597
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1747	0	0
SrcPulseCheck_M	754515696	1777	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1747
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1777
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1747	0	0
SrcPulseCheck_M	2727417	1747	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1747
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1747
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1692	0	0
SrcPulseCheck_M	754515696	1722	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1692
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1722
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1692	0	0
SrcPulseCheck_M	2727417	1692	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1692
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	11

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1692
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	11

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1968	0	0
SrcPulseCheck_M	754515696	1998	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1968
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1998
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1968	0	0
SrcPulseCheck_M	2727417	1968	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1968
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1968
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1763	0	0
SrcPulseCheck_M	754515696	1793	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1763
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1793
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1763	0	0
SrcPulseCheck_M	2727417	1763	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1763
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1763
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1738	0	0
SrcPulseCheck_M	754515696	1768	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1738
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1768
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1738	0	0
SrcPulseCheck_M	2727417	1738	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1738
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1738
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1813	0	0
SrcPulseCheck_M	754515696	1863	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1813
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1863
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1813	0	0
SrcPulseCheck_M	2727417	1813	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1813
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1813
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1773	0	0
SrcPulseCheck_M	754515696	1803	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1773
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1803
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1773	0	0
SrcPulseCheck_M	2727417	1773	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1773
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1773
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1663	0	0
SrcPulseCheck_M	754515696	1693	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1663
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1693
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1663	0	0
SrcPulseCheck_M	2727417	1663	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1663
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1663
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1603	0	0
SrcPulseCheck_M	754515696	1633	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1603
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1633
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1603	0	0
SrcPulseCheck_M	2727417	1603	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1603
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1603
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1683	0	0
SrcPulseCheck_M	754515696	1733	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1683
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1733
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T84,T85,T54

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T84,T85,T54
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1683	0	0
SrcPulseCheck_M	2727417	1683	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1683
T17	488486	5
T18	116176	0
T21	488486	5
T22	488486	5
T23	488486	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0
T84	0	9

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1683
T17	17445	5
T18	414	0
T21	17445	5
T22	17445	5
T23	17445	5
T27	0	9
T29	0	5
T31	0	9
T33	0	9
T34	0	9
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0
T84	0	9

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1410	0	0
SrcPulseCheck_M	754515696	1440	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1410
T17	17445	7
T18	414	0
T21	17445	7
T22	17445	7
T23	17445	7
T27	0	8
T29	0	7
T31	0	8
T33	0	8
T34	0	8
T35	0	7
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1440
T17	488486	7
T18	116176	0
T21	488486	7
T22	488486	7
T23	488486	7
T27	0	8
T29	0	7
T31	0	8
T33	0	8
T34	0	8
T35	0	7
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T17,T21,T22
1	1	Covered	T24,T25,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T21,T22
1	0	Covered	T24,T25,T26
1	1	Covered	T17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	990	0	0
SrcPulseCheck_M	754515696	1022	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	990
T17	17445	1
T18	414	0
T21	17445	1
T22	17445	1
T23	17445	1
T24	0	3
T25	0	3
T26	0	3
T28	0	3
T29	0	1
T30	0	3
T38	8403	0
T39	627	0
T40	414	0
T41	627	0
T42	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1022
T17	488486	1
T18	116176	0
T21	488486	1
T22	488486	1
T23	488486	1
T24	0	3
T25	0	3
T26	0	3
T28	0	3
T29	0	1
T30	0	3
T38	235306	0
T39	175783	0
T40	116176	0
T41	175783	0
T42	140863	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc