dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.08 100.00 92.31 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.22 100.00 96.88 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_ulp_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 100.00 87.50 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.79 96.99 84.93 93.22 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 92.06 95.92 81.63 90.70 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 100.00 87.50 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.79 96.99 84.93 93.22 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 92.06 95.92 81.63 90.70 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.33 100.00 93.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.17 100.00 96.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 100.00 100.00 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.68 96.99 84.51 93.22 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 92.06 95.92 81.63 90.70 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.u_reg.u_ec_rst_ctl_cdc
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
tb.dut.u_reg.u_ulp_ctl_cdc
tb.dut.u_reg.u_ulp_status_cdc
tb.dut.u_reg.u_wkup_status_cdc
tb.dut.u_reg.u_key_invert_ctl_cdc
tb.dut.u_reg.u_pin_allowed_ctl_cdc
tb.dut.u_reg.u_pin_out_ctl_cdc
tb.dut.u_reg.u_pin_out_value_cdc
tb.dut.u_reg.u_key_intr_ctl_cdc
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
tb.dut.u_reg.u_auto_block_out_ctl_cdc
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
tb.dut.u_reg.u_com_sel_ctl_0_cdc
tb.dut.u_reg.u_com_sel_ctl_1_cdc
tb.dut.u_reg.u_com_sel_ctl_2_cdc
tb.dut.u_reg.u_com_sel_ctl_3_cdc
tb.dut.u_reg.u_com_det_ctl_0_cdc
tb.dut.u_reg.u_com_det_ctl_1_cdc
tb.dut.u_reg.u_com_det_ctl_2_cdc
tb.dut.u_reg.u_com_det_ctl_3_cdc
tb.dut.u_reg.u_com_out_ctl_0_cdc
tb.dut.u_reg.u_com_out_ctl_1_cdc
tb.dut.u_reg.u_com_out_ctl_2_cdc
tb.dut.u_reg.u_com_out_ctl_3_cdc
tb.dut.u_reg.u_combo_intr_status_cdc
Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1786691 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1932 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1786691 0 0
T17 488486 4015 0 0
T18 116176 0 0 0
T21 488486 4015 0 0
T22 488486 4015 0 0
T23 488486 4015 0 0
T27 0 8163 0 0
T29 0 4015 0 0
T31 0 8163 0 0
T33 0 8163 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T100 0 1113 0 0
T101 0 1113 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1932 0 0
T17 488486 5 0 0
T18 116176 0 0 0
T21 488486 5 0 0
T22 488486 5 0 0
T23 488486 5 0 0
T27 0 9 0 0
T29 0 5 0 0
T31 0 9 0 0
T33 0 9 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T100 0 1 0 0
T101 0 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT16,T19,T20

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT16,T19,T20
11CoveredT16,T19,T20

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT16,T19,T20

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT16,T19,T20
11CoveredT16,T19,T20

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T16,T19,T20
0 0 1 Covered T16,T19,T20
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T16,T19,T20
0 0 1 Covered T16,T19,T20
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1091464 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1147 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1091464 0 0
T16 130789 2233 0 0
T17 488486 0 0 0
T18 116176 0 0 0
T19 0 2233 0 0
T20 0 2233 0 0
T21 488486 0 0 0
T22 488486 0 0 0
T23 488486 0 0 0
T32 0 2233 0 0
T36 0 2233 0 0
T37 0 2233 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T43 0 2233 0 0
T44 0 2233 0 0
T84 0 1117 0 0
T85 0 1117 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1147 0 0
T16 130789 2 0 0
T17 488486 0 0 0
T18 116176 0 0 0
T19 0 2 0 0
T20 0 2 0 0
T21 488486 0 0 0
T22 488486 0 0 0
T23 488486 0 0 0
T32 0 2 0 0
T36 0 2 0 0
T37 0 2 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T43 0 2 0 0
T44 0 2 0 0
T84 0 1 0 0
T85 0 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT16,T19,T20

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT16,T19,T20
11CoveredT16,T19,T20

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT16,T19,T20

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT16,T19,T20
11CoveredT16,T19,T20

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T16,T19,T20
0 0 1 Covered T16,T19,T20
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T16,T19,T20
0 0 1 Covered T16,T19,T20
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 971565 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1012 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 971565 0 0
T16 130789 2210 0 0
T17 488486 0 0 0
T18 116176 0 0 0
T19 0 2210 0 0
T20 0 2210 0 0
T21 488486 0 0 0
T22 488486 0 0 0
T23 488486 0 0 0
T32 0 2210 0 0
T36 0 2210 0 0
T37 0 2210 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T43 0 2210 0 0
T44 0 2210 0 0
T84 0 1110 0 0
T85 0 1110 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1012 0 0
T16 130789 2 0 0
T17 488486 0 0 0
T18 116176 0 0 0
T19 0 2 0 0
T20 0 2 0 0
T21 488486 0 0 0
T22 488486 0 0 0
T23 488486 0 0 0
T32 0 2 0 0
T36 0 2 0 0
T37 0 2 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T43 0 2 0 0
T44 0 2 0 0
T84 0 1 0 0
T85 0 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT16,T19,T20

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT16,T19,T20
11CoveredT16,T19,T20

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT16,T19,T20

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT16,T19,T20
11CoveredT16,T19,T20

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T16,T19,T20
0 0 1 Covered T16,T19,T20
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T16,T19,T20
0 0 1 Covered T16,T19,T20
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1116552 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1147 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1116552 0 0
T16 130789 2195 0 0
T17 488486 0 0 0
T18 116176 0 0 0
T19 0 2195 0 0
T20 0 2195 0 0
T21 488486 0 0 0
T22 488486 0 0 0
T23 488486 0 0 0
T32 0 2195 0 0
T36 0 2195 0 0
T37 0 2195 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T43 0 2195 0 0
T44 0 2195 0 0
T84 0 1106 0 0
T85 0 1106 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1147 0 0
T16 130789 2 0 0
T17 488486 0 0 0
T18 116176 0 0 0
T19 0 2 0 0
T20 0 2 0 0
T21 488486 0 0 0
T22 488486 0 0 0
T23 488486 0 0 0
T32 0 2 0 0
T36 0 2 0 0
T37 0 2 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T43 0 2 0 0
T44 0 2 0 0
T84 0 1 0 0
T85 0 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
TotalCoveredPercent
Conditions131292.31
Logical131292.31
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT16,T19,T20

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT16,T19,T20
11CoveredT16,T19,T20

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT16,T19,T20
1-CoveredT16,T19,T20

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT16,T19,T20

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT16,T19,T20
11CoveredT16,T19,T20

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T16,T19,T20
0 0 1 Covered T16,T19,T20
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T16,T19,T20
0 0 1 Covered T16,T19,T20
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1193449 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1238 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1193449 0 0
T16 130789 2223 0 0
T17 488486 0 0 0
T18 116176 0 0 0
T19 0 2223 0 0
T20 0 2223 0 0
T21 488486 0 0 0
T22 488486 0 0 0
T23 488486 0 0 0
T32 0 2223 0 0
T36 0 2223 0 0
T37 0 2223 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T43 0 2223 0 0
T44 0 2223 0 0
T84 0 3587 0 0
T85 0 3587 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1238 0 0
T16 130789 2 0 0
T17 488486 0 0 0
T18 116176 0 0 0
T19 0 2 0 0
T20 0 2 0 0
T21 488486 0 0 0
T22 488486 0 0 0
T23 488486 0 0 0
T32 0 2 0 0
T36 0 2 0 0
T37 0 2 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T43 0 2 0 0
T44 0 2 0 0
T84 0 4 0 0
T85 0 4 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
TotalCoveredPercent
Conditions161487.50
Logical161487.50
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT16,T19,T20

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT16,T19,T20
11CoveredT16,T19,T20

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT1,T7,T8
1-CoveredT16,T19,T20

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01CoveredT16,T19,T20
10CoveredT16,T19,T20

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT16,T19,T20
11CoveredT16,T19,T20

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Not Covered
11CoveredT16,T19,T20

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T16,T19,T20
0 0 1 Covered T16,T19,T20
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T16,T19,T20
0 0 1 Covered T16,T19,T20
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 836775 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 800 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 836775 0 0
T16 130789 1100 0 0
T17 488486 0 0 0
T18 116176 0 0 0
T19 0 1100 0 0
T20 0 1100 0 0
T21 488486 0 0 0
T22 488486 0 0 0
T23 488486 0 0 0
T32 0 1100 0 0
T36 0 1100 0 0
T37 0 1100 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T43 0 1100 0 0
T44 0 1100 0 0
T45 0 1100 0 0
T46 0 1100 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 800 0 0
T16 130789 1 0 0
T17 488486 0 0 0
T18 116176 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 488486 0 0 0
T22 488486 0 0 0
T23 488486 0 0 0
T32 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
TotalCoveredPercent
Conditions161487.50
Logical161487.50
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT16,T17,T21

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT16,T17,T21
11CoveredT16,T17,T21

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT84,T85,T86
1-CoveredT16,T17,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01CoveredT16,T17,T21
10CoveredT16,T17,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT16,T17,T21
11CoveredT16,T17,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Not Covered
11CoveredT16,T17,T21

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T16,T17,T21
0 0 1 Covered T16,T17,T21
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T16,T17,T21
0 0 1 Covered T16,T17,T21
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1505038 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1510 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1505038 0 0
T16 130789 1099 0 0
T17 488486 6330 0 0
T18 116176 0 0 0
T19 0 1099 0 0
T20 0 1099 0 0
T21 488486 6330 0 0
T22 488486 6330 0 0
T23 488486 6330 0 0
T27 0 7706 0 0
T29 0 6330 0 0
T31 0 7706 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1510 0 0
T16 130789 1 0 0
T17 488486 7 0 0
T18 116176 0 0 0
T19 0 1 0 0
T20 0 1 0 0
T21 488486 7 0 0
T22 488486 7 0 0
T23 488486 7 0 0
T27 0 8 0 0
T29 0 7 0 0
T31 0 8 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 3035455 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 3105 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 3035455 0 0
T17 488486 19796 0 0
T18 116176 0 0 0
T21 488486 19796 0 0
T22 488486 19796 0 0
T23 488486 19796 0 0
T29 0 19796 0 0
T35 0 19796 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T47 0 19782 0 0
T95 0 19782 0 0
T102 0 19782 0 0
T103 0 19782 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 3105 0 0
T17 488486 20 0 0
T18 116176 0 0 0
T21 488486 20 0 0
T22 488486 20 0 0
T23 488486 20 0 0
T29 0 20 0 0
T35 0 20 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T47 0 20 0 0
T95 0 20 0 0
T102 0 20 0 0
T103 0 20 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 5023070 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 5170 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 5023070 0 0
T17 488486 39828 0 0
T18 116176 0 0 0
T21 488486 39828 0 0
T22 488486 39828 0 0
T23 488486 39828 0 0
T29 0 39828 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 19506 0 0
T47 0 1113 0 0
T53 0 19506 0 0
T104 0 19506 0 0
T105 0 19492 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 5170 0 0
T17 488486 41 0 0
T18 116176 0 0 0
T21 488486 41 0 0
T22 488486 41 0 0
T23 488486 41 0 0
T29 0 41 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 20 0 0
T47 0 1 0 0
T53 0 20 0 0
T104 0 20 0 0
T105 0 20 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 5867210 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 5967 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 5867210 0 0
T17 488486 45394 0 0
T18 116176 0 0 0
T21 488486 45394 0 0
T22 488486 45394 0 0
T23 488486 45394 0 0
T27 0 8853 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 19804 0 0
T47 0 1115 0 0
T53 0 19804 0 0
T104 0 19804 0 0
T105 0 19754 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 5967 0 0
T17 488486 46 0 0
T18 116176 0 0 0
T21 488486 46 0 0
T22 488486 46 0 0
T23 488486 46 0 0
T27 0 9 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 20 0 0
T47 0 1 0 0
T53 0 20 0 0
T104 0 20 0 0
T105 0 20 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 4794510 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 4925 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 4794510 0 0
T17 488486 39295 0 0
T18 116176 0 0 0
T21 488486 39295 0 0
T22 488486 39295 0 0
T23 488486 39295 0 0
T29 0 39295 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 19644 0 0
T53 0 19644 0 0
T104 0 19644 0 0
T105 0 19618 0 0
T106 0 19618 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 4925 0 0
T17 488486 40 0 0
T18 116176 0 0 0
T21 488486 40 0 0
T22 488486 40 0 0
T23 488486 40 0 0
T29 0 40 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 20 0 0
T53 0 20 0 0
T104 0 20 0 0
T105 0 20 0 0
T106 0 20 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1219877 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1246 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1219877 0 0
T17 488486 1107 0 0
T18 116176 0 0 0
T21 488486 1107 0 0
T22 488486 1107 0 0
T23 488486 1107 0 0
T24 0 1115 0 0
T25 0 1115 0 0
T26 0 1115 0 0
T28 0 1115 0 0
T29 0 1107 0 0
T30 0 1115 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1246 0 0
T17 488486 1 0 0
T18 116176 0 0 0
T21 488486 1 0 0
T22 488486 1 0 0
T23 488486 1 0 0
T24 0 1 0 0
T25 0 1 0 0
T26 0 1 0 0
T28 0 1 0 0
T29 0 1 0 0
T30 0 1 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1783846 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1924 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1783846 0 0
T17 488486 5078 0 0
T18 116176 0 0 0
T21 488486 5078 0 0
T22 488486 5078 0 0
T23 488486 5078 0 0
T24 0 1113 0 0
T25 0 1113 0 0
T26 0 1113 0 0
T27 0 8109 0 0
T28 0 1113 0 0
T29 0 5078 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1924 0 0
T17 488486 6 0 0
T18 116176 0 0 0
T21 488486 6 0 0
T22 488486 6 0 0
T23 488486 6 0 0
T24 0 1 0 0
T25 0 1 0 0
T26 0 1 0 0
T27 0 9 0 0
T28 0 1 0 0
T29 0 6 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT39,T41,T83

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT39,T41,T83
11CoveredT39,T41,T83

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT39,T41,T83

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT39,T41,T83
11CoveredT39,T41,T83

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T39,T41,T83
0 0 1 Covered T39,T41,T83
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T39,T41,T83
0 0 1 Covered T39,T41,T83
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1193645 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1259 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1193645 0 0
T21 488486 0 0 0
T22 488486 0 0 0
T23 488486 0 0 0
T24 203230 0 0 0
T39 175783 4731 0 0
T40 116176 0 0 0
T41 175783 4731 0 0
T42 140863 0 0 0
T83 0 4731 0 0
T84 0 2225 0 0
T85 0 2225 0 0
T87 0 4731 0 0
T88 0 4731 0 0
T89 0 4731 0 0
T90 0 4731 0 0
T91 0 4731 0 0
T93 116176 0 0 0
T94 116176 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1259 0 0
T21 488486 0 0 0
T22 488486 0 0 0
T23 488486 0 0 0
T24 203230 0 0 0
T39 175783 5 0 0
T40 116176 0 0 0
T41 175783 5 0 0
T42 140863 0 0 0
T83 0 5 0 0
T84 0 2 0 0
T85 0 2 0 0
T87 0 5 0 0
T88 0 5 0 0
T89 0 5 0 0
T90 0 5 0 0
T91 0 5 0 0
T93 116176 0 0 0
T94 116176 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT39,T41,T83

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT39,T41,T83
11CoveredT39,T41,T83

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT39,T41,T83

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT39,T41,T83
11CoveredT39,T41,T83

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T39,T41,T83
0 0 1 Covered T39,T41,T83
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T39,T41,T83
0 0 1 Covered T39,T41,T83
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1143333 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1192 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1143333 0 0
T21 488486 0 0 0
T22 488486 0 0 0
T23 488486 0 0 0
T24 203230 0 0 0
T39 175783 3042 0 0
T40 116176 0 0 0
T41 175783 3042 0 0
T42 140863 0 0 0
T83 0 3042 0 0
T84 0 1119 0 0
T85 0 1119 0 0
T87 0 3042 0 0
T88 0 3042 0 0
T89 0 3042 0 0
T90 0 3042 0 0
T91 0 3042 0 0
T93 116176 0 0 0
T94 116176 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1192 0 0
T21 488486 0 0 0
T22 488486 0 0 0
T23 488486 0 0 0
T24 203230 0 0 0
T39 175783 3 0 0
T40 116176 0 0 0
T41 175783 3 0 0
T42 140863 0 0 0
T83 0 3 0 0
T84 0 1 0 0
T85 0 1 0 0
T87 0 3 0 0
T88 0 3 0 0
T89 0 3 0 0
T90 0 3 0 0
T91 0 3 0 0
T93 116176 0 0 0
T94 116176 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T86

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT84,T85,T86
11CoveredT84,T85,T86

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T86

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT84,T85,T86
11CoveredT84,T85,T86

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T86
0 0 1 Covered T84,T85,T86
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T86
0 0 1 Covered T84,T85,T86
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 998106 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1052 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 998106 0 0
T1 0 16281 0 0
T35 488486 0 0 0
T54 0 1899 0 0
T55 0 1899 0 0
T84 215076 10508 0 0
T85 215076 10508 0 0
T86 0 1115 0 0
T92 0 1115 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T107 0 1115 0 0
T108 0 1115 0 0
T109 0 1115 0 0
T110 140863 0 0 0
T111 203230 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1052 0 0
T1 0 19 0 0
T35 488486 0 0 0
T54 0 2 0 0
T55 0 2 0 0
T84 215076 11 0 0
T85 215076 11 0 0
T86 0 1 0 0
T92 0 1 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T107 0 1 0 0
T108 0 1 0 0
T109 0 1 0 0
T110 140863 0 0 0
T111 203230 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T54

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT84,T85,T54
11CoveredT84,T85,T54

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T54

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT84,T85,T54
11CoveredT84,T85,T54

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T54
0 0 1 Covered T84,T85,T54
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T54
0 0 1 Covered T84,T85,T54
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 918274 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 982 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 918274 0 0
T1 0 17147 0 0
T7 0 825 0 0
T13 0 1829 0 0
T14 0 1829 0 0
T35 488486 0 0 0
T52 0 1829 0 0
T54 0 1829 0 0
T55 0 1829 0 0
T56 0 295 0 0
T84 215076 10492 0 0
T85 215076 10492 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T110 140863 0 0 0
T111 203230 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 982 0 0
T1 0 20 0 0
T8 0 20 0 0
T13 0 2 0 0
T14 0 2 0 0
T35 488486 0 0 0
T52 0 2 0 0
T54 0 2 0 0
T55 0 2 0 0
T57 0 2 0 0
T84 215076 11 0 0
T85 215076 11 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T110 140863 0 0 0
T111 203230 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T54

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT84,T85,T54
11CoveredT84,T85,T54

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T54

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT84,T85,T54
11CoveredT84,T85,T54

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T54
0 0 1 Covered T84,T85,T54
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T54
0 0 1 Covered T84,T85,T54
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1074469 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1127 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1074469 0 0
T1 0 17599 0 0
T7 0 699 0 0
T13 0 1910 0 0
T14 0 1910 0 0
T35 488486 0 0 0
T52 0 1910 0 0
T54 0 1910 0 0
T55 0 1910 0 0
T56 0 208 0 0
T84 215076 10517 0 0
T85 215076 10517 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T110 140863 0 0 0
T111 203230 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1127 0 0
T1 0 20 0 0
T8 0 20 0 0
T13 0 2 0 0
T14 0 2 0 0
T35 488486 0 0 0
T52 0 2 0 0
T54 0 2 0 0
T55 0 2 0 0
T57 0 2 0 0
T84 215076 11 0 0
T85 215076 11 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T110 140863 0 0 0
T111 203230 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T54

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT84,T85,T54
11CoveredT84,T85,T54

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T54

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT84,T85,T54
11CoveredT84,T85,T54

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T54
0 0 1 Covered T84,T85,T54
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T54
0 0 1 Covered T84,T85,T54
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 956817 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1012 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 956817 0 0
T1 0 17326 0 0
T7 0 747 0 0
T13 0 1936 0 0
T14 0 1936 0 0
T35 488486 0 0 0
T52 0 1936 0 0
T54 0 1936 0 0
T55 0 1936 0 0
T56 0 466 0 0
T84 215076 10521 0 0
T85 215076 10521 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T110 140863 0 0 0
T111 203230 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1012 0 0
T1 0 20 0 0
T8 0 20 0 0
T13 0 2 0 0
T14 0 2 0 0
T35 488486 0 0 0
T52 0 2 0 0
T54 0 2 0 0
T55 0 2 0 0
T57 0 2 0 0
T84 215076 11 0 0
T85 215076 11 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T110 140863 0 0 0
T111 203230 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T86

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT84,T85,T86
11CoveredT84,T85,T86

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T86

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT84,T85,T86
11CoveredT84,T85,T86

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T86
0 0 1 Covered T84,T85,T86
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T86
0 0 1 Covered T84,T85,T86
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 967832 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1023 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 967832 0 0
T1 0 17222 0 0
T35 488486 0 0 0
T54 0 1989 0 0
T55 0 1989 0 0
T84 215076 8196 0 0
T85 215076 8196 0 0
T86 0 1113 0 0
T92 0 1113 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T107 0 1113 0 0
T108 0 1113 0 0
T109 0 1113 0 0
T110 140863 0 0 0
T111 203230 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1023 0 0
T1 0 20 0 0
T35 488486 0 0 0
T54 0 2 0 0
T55 0 2 0 0
T84 215076 9 0 0
T85 215076 9 0 0
T86 0 1 0 0
T92 0 1 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T107 0 1 0 0
T108 0 1 0 0
T109 0 1 0 0
T110 140863 0 0 0
T111 203230 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T54

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT84,T85,T54
11CoveredT84,T85,T54

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T54

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT84,T85,T54
11CoveredT84,T85,T54

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T54
0 0 1 Covered T84,T85,T54
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T54
0 0 1 Covered T84,T85,T54
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1055937 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1123 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1055937 0 0
T1 0 16597 0 0
T7 0 834 0 0
T13 0 1962 0 0
T14 0 1962 0 0
T35 488486 0 0 0
T52 0 1962 0 0
T54 0 1962 0 0
T55 0 1962 0 0
T56 0 401 0 0
T84 215076 8191 0 0
T85 215076 8191 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T110 140863 0 0 0
T111 203230 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1123 0 0
T1 0 20 0 0
T8 0 20 0 0
T13 0 2 0 0
T14 0 2 0 0
T35 488486 0 0 0
T52 0 2 0 0
T54 0 2 0 0
T55 0 2 0 0
T57 0 2 0 0
T84 215076 9 0 0
T85 215076 9 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T110 140863 0 0 0
T111 203230 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T54

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT84,T85,T54
11CoveredT84,T85,T54

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T54

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT84,T85,T54
11CoveredT84,T85,T54

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T54
0 0 1 Covered T84,T85,T54
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T54
0 0 1 Covered T84,T85,T54
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1068121 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1118 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1068121 0 0
T1 0 17602 0 0
T7 0 783 0 0
T13 0 1983 0 0
T14 0 1983 0 0
T35 488486 0 0 0
T52 0 1983 0 0
T54 0 1983 0 0
T55 0 1983 0 0
T56 0 431 0 0
T84 215076 8218 0 0
T85 215076 8218 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T110 140863 0 0 0
T111 203230 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1118 0 0
T1 0 20 0 0
T8 0 20 0 0
T13 0 2 0 0
T14 0 2 0 0
T35 488486 0 0 0
T52 0 2 0 0
T54 0 2 0 0
T55 0 2 0 0
T57 0 2 0 0
T84 215076 9 0 0
T85 215076 9 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T110 140863 0 0 0
T111 203230 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T54

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT84,T85,T54
11CoveredT84,T85,T54

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT84,T85,T54

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT84,T85,T54
11CoveredT84,T85,T54

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T54
0 0 1 Covered T84,T85,T54
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T84,T85,T54
0 0 1 Covered T84,T85,T54
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 990005 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1048 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 990005 0 0
T1 0 17303 0 0
T7 0 642 0 0
T13 0 2059 0 0
T14 0 2059 0 0
T35 488486 0 0 0
T52 0 2059 0 0
T54 0 2059 0 0
T55 0 2059 0 0
T56 0 365 0 0
T84 215076 8225 0 0
T85 215076 8225 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T110 140863 0 0 0
T111 203230 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1048 0 0
T1 0 20 0 0
T8 0 20 0 0
T13 0 2 0 0
T14 0 2 0 0
T35 488486 0 0 0
T52 0 2 0 0
T54 0 2 0 0
T55 0 2 0 0
T57 0 2 0 0
T84 215076 9 0 0
T85 215076 9 0 0
T95 138342 0 0 0
T96 118546 0 0 0
T97 138342 0 0 0
T98 488486 0 0 0
T99 146706 0 0 0
T110 140863 0 0 0
T111 203230 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1697673 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1777 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1697673 0 0
T17 488486 4456 0 0
T18 116176 0 0 0
T21 488486 4456 0 0
T22 488486 4456 0 0
T23 488486 4456 0 0
T27 0 8932 0 0
T29 0 4456 0 0
T31 0 8932 0 0
T33 0 8932 0 0
T34 0 8932 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 10374 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1777 0 0
T17 488486 5 0 0
T18 116176 0 0 0
T21 488486 5 0 0
T22 488486 5 0 0
T23 488486 5 0 0
T27 0 9 0 0
T29 0 5 0 0
T31 0 9 0 0
T33 0 9 0 0
T34 0 9 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 11 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1515794 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1597 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1515794 0 0
T17 488486 4415 0 0
T18 116176 0 0 0
T21 488486 4415 0 0
T22 488486 4415 0 0
T23 488486 4415 0 0
T27 0 8870 0 0
T29 0 4415 0 0
T31 0 8870 0 0
T33 0 8870 0 0
T34 0 8870 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 10362 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1597 0 0
T17 488486 5 0 0
T18 116176 0 0 0
T21 488486 5 0 0
T22 488486 5 0 0
T23 488486 5 0 0
T27 0 9 0 0
T29 0 5 0 0
T31 0 9 0 0
T33 0 9 0 0
T34 0 9 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 11 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1642757 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1747 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1642757 0 0
T17 488486 4380 0 0
T18 116176 0 0 0
T21 488486 4380 0 0
T22 488486 4380 0 0
T23 488486 4380 0 0
T27 0 8806 0 0
T29 0 4380 0 0
T31 0 8806 0 0
T33 0 8806 0 0
T34 0 8806 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 10371 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1747 0 0
T17 488486 5 0 0
T18 116176 0 0 0
T21 488486 5 0 0
T22 488486 5 0 0
T23 488486 5 0 0
T27 0 9 0 0
T29 0 5 0 0
T31 0 9 0 0
T33 0 9 0 0
T34 0 9 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 11 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1577726 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1692 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1577726 0 0
T17 488486 4340 0 0
T18 116176 0 0 0
T21 488486 4340 0 0
T22 488486 4340 0 0
T23 488486 4340 0 0
T27 0 8728 0 0
T29 0 4340 0 0
T31 0 8728 0 0
T33 0 8728 0 0
T34 0 8728 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 10398 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1692 0 0
T17 488486 5 0 0
T18 116176 0 0 0
T21 488486 5 0 0
T22 488486 5 0 0
T23 488486 5 0 0
T27 0 9 0 0
T29 0 5 0 0
T31 0 9 0 0
T33 0 9 0 0
T34 0 9 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 11 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1858413 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1968 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1858413 0 0
T17 488486 4303 0 0
T18 116176 0 0 0
T21 488486 4303 0 0
T22 488486 4303 0 0
T23 488486 4303 0 0
T27 0 8660 0 0
T29 0 4303 0 0
T31 0 8660 0 0
T33 0 8660 0 0
T34 0 8660 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 8069 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1968 0 0
T17 488486 5 0 0
T18 116176 0 0 0
T21 488486 5 0 0
T22 488486 5 0 0
T23 488486 5 0 0
T27 0 9 0 0
T29 0 5 0 0
T31 0 9 0 0
T33 0 9 0 0
T34 0 9 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 9 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1644517 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1763 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1644517 0 0
T17 488486 4262 0 0
T18 116176 0 0 0
T21 488486 4262 0 0
T22 488486 4262 0 0
T23 488486 4262 0 0
T27 0 8592 0 0
T29 0 4262 0 0
T31 0 8592 0 0
T33 0 8592 0 0
T34 0 8592 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 8066 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1763 0 0
T17 488486 5 0 0
T18 116176 0 0 0
T21 488486 5 0 0
T22 488486 5 0 0
T23 488486 5 0 0
T27 0 9 0 0
T29 0 5 0 0
T31 0 9 0 0
T33 0 9 0 0
T34 0 9 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 9 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1622780 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1738 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1622780 0 0
T17 488486 4216 0 0
T18 116176 0 0 0
T21 488486 4216 0 0
T22 488486 4216 0 0
T23 488486 4216 0 0
T27 0 8528 0 0
T29 0 4216 0 0
T31 0 8528 0 0
T33 0 8528 0 0
T34 0 8528 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 8075 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1738 0 0
T17 488486 5 0 0
T18 116176 0 0 0
T21 488486 5 0 0
T22 488486 5 0 0
T23 488486 5 0 0
T27 0 9 0 0
T29 0 5 0 0
T31 0 9 0 0
T33 0 9 0 0
T34 0 9 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 9 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1697927 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1813 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1697927 0 0
T17 488486 4188 0 0
T18 116176 0 0 0
T21 488486 4188 0 0
T22 488486 4188 0 0
T23 488486 4188 0 0
T27 0 8470 0 0
T29 0 4188 0 0
T31 0 8470 0 0
T33 0 8470 0 0
T34 0 8470 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 8091 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1813 0 0
T17 488486 5 0 0
T18 116176 0 0 0
T21 488486 5 0 0
T22 488486 5 0 0
T23 488486 5 0 0
T27 0 9 0 0
T29 0 5 0 0
T31 0 9 0 0
T33 0 9 0 0
T34 0 9 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 9 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1653905 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1773 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1653905 0 0
T17 488486 4150 0 0
T18 116176 0 0 0
T21 488486 4150 0 0
T22 488486 4150 0 0
T23 488486 4150 0 0
T27 0 8413 0 0
T29 0 4150 0 0
T31 0 8413 0 0
T33 0 8413 0 0
T34 0 8413 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 7985 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1773 0 0
T17 488486 5 0 0
T18 116176 0 0 0
T21 488486 5 0 0
T22 488486 5 0 0
T23 488486 5 0 0
T27 0 9 0 0
T29 0 5 0 0
T31 0 9 0 0
T33 0 9 0 0
T34 0 9 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 9 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1532754 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1663 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1532754 0 0
T17 488486 4110 0 0
T18 116176 0 0 0
T21 488486 4110 0 0
T22 488486 4110 0 0
T23 488486 4110 0 0
T27 0 8347 0 0
T29 0 4110 0 0
T31 0 8347 0 0
T33 0 8347 0 0
T34 0 8347 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 8012 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1663 0 0
T17 488486 5 0 0
T18 116176 0 0 0
T21 488486 5 0 0
T22 488486 5 0 0
T23 488486 5 0 0
T27 0 9 0 0
T29 0 5 0 0
T31 0 9 0 0
T33 0 9 0 0
T34 0 9 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 9 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1483275 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1603 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1483275 0 0
T17 488486 4089 0 0
T18 116176 0 0 0
T21 488486 4089 0 0
T22 488486 4089 0 0
T23 488486 4089 0 0
T27 0 8295 0 0
T29 0 4089 0 0
T31 0 8295 0 0
T33 0 8295 0 0
T34 0 8295 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 8005 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1603 0 0
T17 488486 5 0 0
T18 116176 0 0 0
T21 488486 5 0 0
T22 488486 5 0 0
T23 488486 5 0 0
T27 0 9 0 0
T29 0 5 0 0
T31 0 9 0 0
T33 0 9 0 0
T34 0 9 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 9 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1543220 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1683 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1543220 0 0
T17 488486 4059 0 0
T18 116176 0 0 0
T21 488486 4059 0 0
T22 488486 4059 0 0
T23 488486 4059 0 0
T27 0 8236 0 0
T29 0 4059 0 0
T31 0 8236 0 0
T33 0 8236 0 0
T34 0 8236 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 8020 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1683 0 0
T17 488486 5 0 0
T18 116176 0 0 0
T21 488486 5 0 0
T22 488486 5 0 0
T23 488486 5 0 0
T27 0 9 0 0
T29 0 5 0 0
T31 0 9 0 0
T33 0 9 0 0
T34 0 9 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0
T84 0 9 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01CoveredT17,T21,T22
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Not Covered
11CoveredT17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1344425 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 1410 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1344425 0 0
T17 488486 6262 0 0
T18 116176 0 0 0
T21 488486 6262 0 0
T22 488486 6262 0 0
T23 488486 6262 0 0
T27 0 7644 0 0
T29 0 6262 0 0
T31 0 7644 0 0
T33 0 7644 0 0
T34 0 7644 0 0
T35 0 6262 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1410 0 0
T17 488486 7 0 0
T18 116176 0 0 0
T21 488486 7 0 0
T22 488486 7 0 0
T23 488486 7 0 0
T27 0 8 0 0
T29 0 7 0 0
T31 0 8 0 0
T33 0 8 0 0
T34 0 8 0 0
T35 0 7 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%