Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T17,T18 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T17,T21,T22 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T17,T18 |
1 | 0 | Covered | T17,T21,T22 |
1 | 1 | Covered | T17,T21,T22 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T17,T18 |
0 | 1 | Covered | T17,T21,T22 |
1 | 0 | Covered | T17,T21,T22 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T17,T21,T22 |
1 | 1 | Covered | T17,T21,T22 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T17,T18 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T17,T21,T22 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T16,T17,T18 |
0 |
1 |
- |
Covered |
T17,T21,T22 |
0 |
0 |
1 |
Covered |
T17,T21,T22 |
0 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T16,T17,T18 |
0 |
1 |
- |
Covered |
T17,T21,T22 |
0 |
0 |
1 |
Covered |
T17,T21,T22 |
0 |
0 |
0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
754515696 |
1042508 |
0 |
0 |
T17 |
488486 |
1096 |
0 |
0 |
T18 |
116176 |
0 |
0 |
0 |
T21 |
488486 |
1096 |
0 |
0 |
T22 |
488486 |
1096 |
0 |
0 |
T23 |
488486 |
1096 |
0 |
0 |
T24 |
0 |
2989 |
0 |
0 |
T25 |
0 |
2989 |
0 |
0 |
T26 |
0 |
2989 |
0 |
0 |
T28 |
0 |
2989 |
0 |
0 |
T29 |
0 |
1096 |
0 |
0 |
T30 |
0 |
2989 |
0 |
0 |
T38 |
235306 |
0 |
0 |
0 |
T39 |
175783 |
0 |
0 |
0 |
T40 |
116176 |
0 |
0 |
0 |
T41 |
175783 |
0 |
0 |
0 |
T42 |
140863 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2727417 |
2106687 |
0 |
0 |
T16 |
1037 |
637 |
0 |
0 |
T17 |
17445 |
15025 |
0 |
0 |
T18 |
414 |
14 |
0 |
0 |
T21 |
17445 |
15025 |
0 |
0 |
T22 |
17445 |
15025 |
0 |
0 |
T23 |
17445 |
15025 |
0 |
0 |
T38 |
8403 |
3 |
0 |
0 |
T39 |
627 |
227 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
627 |
227 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
754515696 |
990 |
0 |
0 |
T17 |
488486 |
1 |
0 |
0 |
T18 |
116176 |
0 |
0 |
0 |
T21 |
488486 |
1 |
0 |
0 |
T22 |
488486 |
1 |
0 |
0 |
T23 |
488486 |
1 |
0 |
0 |
T24 |
0 |
3 |
0 |
0 |
T25 |
0 |
3 |
0 |
0 |
T26 |
0 |
3 |
0 |
0 |
T28 |
0 |
3 |
0 |
0 |
T29 |
0 |
1 |
0 |
0 |
T30 |
0 |
3 |
0 |
0 |
T38 |
235306 |
0 |
0 |
0 |
T39 |
175783 |
0 |
0 |
0 |
T40 |
116176 |
0 |
0 |
0 |
T41 |
175783 |
0 |
0 |
0 |
T42 |
140863 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
754515696 |
753291408 |
0 |
0 |
T16 |
130789 |
130705 |
0 |
0 |
T17 |
488486 |
487880 |
0 |
0 |
T18 |
116176 |
116092 |
0 |
0 |
T21 |
488486 |
487880 |
0 |
0 |
T22 |
488486 |
487880 |
0 |
0 |
T23 |
488486 |
487880 |
0 |
0 |
T38 |
235306 |
235144 |
0 |
0 |
T39 |
175783 |
175699 |
0 |
0 |
T40 |
116176 |
116092 |
0 |
0 |
T41 |
175783 |
175699 |
0 |
0 |