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Module Instance : tb.dut.u_reg.u_key_intr_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.76 100.00 88.73 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.43 100.00 93.73 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

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Module Instances:
tb.dut.u_reg.u_key_intr_status_cdc
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT16,T17,T18
01Unreachable
10CoveredT17,T21,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT16,T17,T18
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT16,T17,T18
01CoveredT17,T21,T22
10CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT17,T21,T22
11CoveredT17,T21,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT16,T17,T18
10Not Covered
11CoveredT17,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T16,T17,T18
0 1 - Covered T17,T21,T22
0 0 1 Covered T17,T21,T22
0 0 0 Covered T16,T17,T18


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 754515696 1042508 0 0
DstReqKnown_A 2727417 2106687 0 0
SrcAckBusyChk_A 754515696 990 0 0
SrcBusyKnown_A 754515696 753291408 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 1042508 0 0
T17 488486 1096 0 0
T18 116176 0 0 0
T21 488486 1096 0 0
T22 488486 1096 0 0
T23 488486 1096 0 0
T24 0 2989 0 0
T25 0 2989 0 0
T26 0 2989 0 0
T28 0 2989 0 0
T29 0 1096 0 0
T30 0 2989 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2727417 2106687 0 0
T16 1037 637 0 0
T17 17445 15025 0 0
T18 414 14 0 0
T21 17445 15025 0 0
T22 17445 15025 0 0
T23 17445 15025 0 0
T38 8403 3 0 0
T39 627 227 0 0
T40 414 14 0 0
T41 627 227 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 990 0 0
T17 488486 1 0 0
T18 116176 0 0 0
T21 488486 1 0 0
T22 488486 1 0 0
T23 488486 1 0 0
T24 0 3 0 0
T25 0 3 0 0
T26 0 3 0 0
T28 0 3 0 0
T29 0 1 0 0
T30 0 3 0 0
T38 235306 0 0 0
T39 175783 0 0 0
T40 116176 0 0 0
T41 175783 0 0 0
T42 140863 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 754515696 753291408 0 0
T16 130789 130705 0 0
T17 488486 487880 0 0
T18 116176 116092 0 0
T21 488486 487880 0 0
T22 488486 487880 0 0
T23 488486 487880 0 0
T38 235306 235144 0 0
T39 175783 175699 0 0
T40 116176 116092 0 0
T41 175783 175699 0 0

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