Module Definition
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Module : sysrst_ctrl_keyintr
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_keyintr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sysrst_ctrl_keyintr 100.00 100.00 100.00



Module Instance : tb.dut.u_sysrst_ctrl_keyintr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.89 98.62 89.23 95.24 98.21 98.16


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.34 100.00 96.72 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_keyfsm[0].u_sysrst_ctrl_detect_h2l 98.10 100.00 90.48 100.00 100.00 100.00
gen_keyfsm[0].u_sysrst_ctrl_detect_l2h 90.61 95.65 85.71 83.33 95.00 93.33
gen_keyfsm[1].u_sysrst_ctrl_detect_h2l 98.10 100.00 90.48 100.00 100.00 100.00
gen_keyfsm[1].u_sysrst_ctrl_detect_l2h 98.10 100.00 90.48 100.00 100.00 100.00
gen_keyfsm[2].u_sysrst_ctrl_detect_h2l 98.10 100.00 90.48 100.00 100.00 100.00
gen_keyfsm[2].u_sysrst_ctrl_detect_l2h 98.10 100.00 90.48 100.00 100.00 100.00
gen_keyfsm[3].u_sysrst_ctrl_detect_h2l 90.69 95.65 85.71 83.33 95.00 93.75
gen_keyfsm[3].u_sysrst_ctrl_detect_l2h 98.10 100.00 90.48 100.00 100.00 100.00
gen_keyfsm[4].u_sysrst_ctrl_detect_h2l 96.66 97.83 90.48 100.00 95.00 100.00
gen_keyfsm[4].u_sysrst_ctrl_detect_l2h 98.10 100.00 90.48 100.00 100.00 100.00
gen_keyfsm[5].u_sysrst_ctrl_detect_h2l 98.10 100.00 90.48 100.00 100.00 100.00
gen_keyfsm[5].u_sysrst_ctrl_detect_l2h 98.10 100.00 90.48 100.00 100.00 100.00
gen_keyfsm[6].u_sysrst_ctrl_detect_h2l 90.69 95.65 85.71 83.33 95.00 93.75
gen_keyfsm[6].u_sysrst_ctrl_detect_l2h 90.61 95.65 85.71 83.33 95.00 93.33


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sysrst_ctrl_keyintr
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_keyintr.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_keyintr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
31 1 1
40 1 1
49 1 1
101 1 1
109 1 1
118 1 1


Cond Coverage for Module : sysrst_ctrl_keyintr
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       118
 EXPRESSION (((|l2h_met_pulse)) || ((|h2l_met_pulse)))
             ---------1--------    ---------2--------
-1--2-StatusTests
00CoveredT36,T12,T25
01CoveredT12,T15,T16
10CoveredT12,T13,T15
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%