Unified Coverage Report :: Module :: sysrst_ctrl

Module : sysrst_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.34	100.00	96.72	100.00		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	99.34	100.00	96.72	100.00		100.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.34	100.00	96.72	100.00		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.55	99.39	96.05	100.00	97.44	98.78	99.63

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
sysrst_ctrl_csr_assert	100.00						100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_prim_flop_2sync_input	100.00	100.00				100.00
u_prim_intr_hw	100.00	100.00	100.00			100.00	100.00
u_prim_sync_reqack	87.50	100.00	50.00			100.00	100.00
u_reg	98.93	99.40	96.43	100.00		98.84	100.00
u_sysrst_ctrl_autoblock	99.44	100.00	97.22		100.00	100.00	100.00
u_sysrst_ctrl_combo	99.12	100.00	97.61		100.00	98.00	100.00
u_sysrst_ctrl_keyintr	95.89	98.62	89.23		95.24	98.21	98.16
u_sysrst_ctrl_pin	100.00	100.00	100.00			100.00
u_sysrst_ctrl_ulp	98.98	100.00	94.92		100.00	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
ALWAYS	339	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
67	1	1
106	1	1
107	1	1
108	1	1
109	1	1
110	1	1
111	1	1
113	1	1
114	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
330	1	1
333	1	1
335	1	1
339	1	1
340	1	1
343	1	1

---

Cond Coverage for Module : sysrst_ctrl

	Total	Covered	Percent
Conditions	61	59	96.72
Logical	61	59	96.72
Non-Logical	0	0
Event	0	0

 LINE       67
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T36,T104,T131
1	0	Covered	T36,T12,T25
1	1	Covered	T36,T104,T131

 LINE       106
 EXPRESSION (reg2hw.key_invert_ctl.pwrb_in.q ^ cio_pwrb_in_i)
             ---------------1---------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T36,T12,T25
0	1	Covered	T12,T25,T26
1	0	Covered	T79,T69,T80
1	1	Covered	T79,T69,T80

 LINE       107
 EXPRESSION (reg2hw.key_invert_ctl.key0_in.q ^ cio_key0_in_i)
             ---------------1---------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T36,T12,T25
0	1	Covered	T12,T25,T27
1	0	Covered	T79,T69,T80
1	1	Covered	T79,T69,T80

 LINE       108
 EXPRESSION (reg2hw.key_invert_ctl.key1_in.q ^ cio_key1_in_i)
             ---------------1---------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T36,T12,T25
0	1	Covered	T12,T25,T27
1	0	Covered	T79,T69,T80
1	1	Covered	T79,T69,T80

 LINE       109
 EXPRESSION (reg2hw.key_invert_ctl.key2_in.q ^ cio_key2_in_i)
             ---------------1---------------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T36,T12,T25
0	1	Covered	T12,T25,T27
1	0	Covered	T79,T69,T80
1	1	Covered	T79,T69,T80

 LINE       110
 EXPRESSION (reg2hw.key_invert_ctl.ac_present.q ^ cio_ac_present_i)
             -----------------1----------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T36,T12,T25
0	1	Covered	T12,T25,T26
1	0	Covered	T79,T69,T80
1	1	Covered	T79,T69,T80

 LINE       111
 EXPRESSION (reg2hw.key_invert_ctl.lid_open.q ^ cio_lid_open_i)
             ----------------1---------------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T36,T12,T25
0	1	Covered	T12,T25,T26
1	0	Covered	T79,T69,T80
1	1	Covered	T79,T69,T80

 LINE       304
 EXPRESSION (reg2hw.key_invert_ctl.pwrb_out.q ^ pwrb_out_int)
             ----------------1---------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T36,T12,T25
0	1	Covered	T12,T25,T26
1	0	Covered	T79,T69,T80
1	1	Covered	T79,T69,T80

 LINE       305
 EXPRESSION (reg2hw.key_invert_ctl.key0_out.q ^ key0_out_int)
             ----------------1---------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T36,T12,T25
0	1	Covered	T12,T25,T27
1	0	Covered	T79,T69,T80
1	1	Covered	T79,T69,T80

 LINE       306
 EXPRESSION (reg2hw.key_invert_ctl.key1_out.q ^ key1_out_int)
             ----------------1---------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T36,T12,T25
0	1	Covered	T12,T25,T27
1	0	Covered	T79,T69,T80
1	1	Covered	T79,T69,T80

 LINE       307
 EXPRESSION (reg2hw.key_invert_ctl.key2_out.q ^ key2_out_int)
             ----------------1---------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T36,T12,T25
0	1	Covered	T12,T25,T27
1	0	Covered	T79,T69,T80
1	1	Covered	T79,T69,T80

 LINE       308
 EXPRESSION (reg2hw.key_invert_ctl.bat_disable.q ^ aon_bat_disable_out_int)
             -----------------1-----------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T12,T25
0	1	Covered	T12,T25,T27
1	0	Covered	T79,T69,T80
1	1	Not Covered

 LINE       309
 EXPRESSION (reg2hw.key_invert_ctl.z3_wakeup.q ^ aon_z3_wakeup_out_int)
             ----------------1----------------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T36,T12,T25
0	1	Covered	T12,T25,T27
1	0	Covered	T79,T69,T80
1	1	Not Covered

 LINE       330
 EXPRESSION (aon_ulp_wakeup_pulse_int || aon_sysrst_ctrl_combo_intr || aon_sysrst_ctrl_key_intr)
             ------------1-----------    -------------2------------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T36,T12,T25
0	0	1	Covered	T12,T13,T15
0	1	0	Covered	T14,T16,T18
1	0	0	Covered	T12,T16,T21

 LINE       343
 EXPRESSION ((aon_intr_req && ((!aon_intr_ack))) || aon_intr_event_pulse)
             -----------------1-----------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T12,T25
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14

 LINE       343
 SUB-EXPRESSION (aon_intr_req && ((!aon_intr_ack)))
                 ------1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T36,T12,T25
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

---

Toggle Coverage for Module : sysrst_ctrl

	Total	Covered	Percent
Totals	47	47	100.00
Total Bits	374	374	100.00
Total Bits 0->1	187	187	100.00
Total Bits 1->0	187	187	100.00

Ports	47	47	100.00
Port Bits	374	374	100.00
Port Bits 0->1	187	187	100.00
Port Bits 1->0	187	187	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
clk_aon_i	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
rst_ni	Yes	Yes	T3,T23,T4	Yes	T1,T2,T5	INPUT
rst_aon_ni	Yes	Yes	T3,T23,T4	Yes	T1,T2,T5	INPUT
tl_i.d_ready	Yes	Yes	T2,T5,T3	Yes	T1,T2,T5	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T5,T23	Yes	T1,T5,T23	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
tl_o.d_error	Yes	Yes	T5,T23,T6	Yes	T5,T23,T6	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,T5	Yes	T1,T2,T5	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T2,T5,T22	Yes	T2,T5,T22	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T5,*T22	Yes	T1,T2,T5	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
wkup_req_o	Yes	Yes	T12,T14,T15	Yes	T12,T13,T14	OUTPUT
rst_req_o	Yes	Yes	T14,T18,T19	Yes	T14,T18,T19	OUTPUT
intr_event_detected_o	Yes	Yes	T22,T300,T301	Yes	T22,T300,T301	OUTPUT
cio_ac_present_i	Yes	Yes	T12,T25,T26	Yes	T12,T25,T26	INPUT
cio_ec_rst_l_i	Yes	Yes	T12,T25,T27	Yes	T12,T25,T27	INPUT
cio_key0_in_i	Yes	Yes	T12,T25,T27	Yes	T12,T25,T27	INPUT
cio_key1_in_i	Yes	Yes	T12,T25,T27	Yes	T12,T25,T27	INPUT
cio_key2_in_i	Yes	Yes	T12,T25,T27	Yes	T12,T25,T27	INPUT
cio_pwrb_in_i	Yes	Yes	T12,T25,T26	Yes	T12,T25,T26	INPUT
cio_lid_open_i	Yes	Yes	T12,T25,T26	Yes	T12,T25,T26	INPUT
cio_flash_wp_l_i	Yes	Yes	T12,T25,T27	Yes	T12,T25,T27	INPUT
cio_bat_disable_o	Yes	Yes	T3,T4,T6	Yes	T2,T3,T4	OUTPUT
cio_flash_wp_l_o	Yes	Yes	T6,T8,T302	Yes	T6,T8,T34	OUTPUT
cio_ec_rst_l_o	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
cio_key0_out_o	Yes	Yes	T3,T4,T6	Yes	T1,T3,T4	OUTPUT
cio_key1_out_o	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
cio_key2_out_o	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
cio_pwrb_out_o	Yes	Yes	T3,T4,T6	Yes	T3,T4,T6	OUTPUT
cio_z3_wakeup_o	Yes	Yes	T3,T4,T6	Yes	T2,T3,T4	OUTPUT
cio_bat_disable_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_flash_wp_l_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_ec_rst_l_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key0_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key1_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key2_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pwrb_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_z3_wakeup_en_o	Unreachable	Unreachable		Unreachable		OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : sysrst_ctrl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	339	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	339	if ((~rst_aon_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Module : sysrst_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	23	23	100.00	23	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	23	23	100.00	23	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnown_A	1285302250	1283579953	0	0
BatOEnIsOne_A	1285302250	1283579953	0	0
BatOKnown_A	1285302250	1283579953	0	0
ECRSTOEnIsOne_A	1285302250	1283579953	0	0
ECRSTOKnown_A	1285302250	1283579953	0	0
FlashWpOEnIsOne_A	1285302250	1283579953	0	0
FlashWpOKnown_A	1285302250	1283579953	0	0
FpvSecCmRegWeOnehotCheck_A	1285302250	80	0	0
IntrEventOKnown_A	1285302250	1283579953	0	0
Key0OEnIsOne_A	1285302250	1283579953	0	0
Key0OKnown_A	1285302250	1283579953	0	0
Key1OEnIsOne_A	1285302250	1283579953	0	0
Key1OKnown_A	1285302250	1283579953	0	0
Key2OEnIsOne_A	1285302250	1283579953	0	0
Key2OKnown_A	1285302250	1283579953	0	0
OTRstOKnown_A	1285302250	1283579953	0	0
OTWkOKnown_A	1285302250	1283579953	0	0
PwrbOEnIsOne_A	1285302250	1283579953	0	0
PwrbOKnown_A	1285302250	1283579953	0	0
TlOAReadyKnown_A	1285302250	1283579953	0	0
TlODValidKnown_A	1285302250	1283579953	0	0
Z3WakeupOEnIsOne_A	1285302250	1283579953	0	0
Z3WwakupOKnown_A	1285302250	1283579953	0	0

AlertKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

BatOEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

BatOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

ECRSTOEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

ECRSTOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

FlashWpOEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

FlashWpOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	80	0	0
T289	101030	20	0	0
T290	0	20	0	0
T291	0	20	0	0
T303	0	10	0	0
T304	0	10	0	0
T305	258265	0	0	0
T306	106976	0	0	0
T307	225865	0	0	0
T308	892266	0	0	0
T309	124431	0	0	0
T310	785058	0	0	0
T311	278571	0	0	0
T312	197969	0	0	0
T313	111298	0	0	0

IntrEventOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

Key0OEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

Key0OKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

Key1OEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

Key1OKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

Key2OEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

Key2OKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

OTRstOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

OTWkOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

PwrbOEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

PwrbOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

Z3WakeupOEnIsOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0

Z3WwakupOKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1285302250	1283579953	0	0
T12	157994	157212	0	0
T25	248515	248450	0	0
T26	52146	52051	0	0
T27	261356	261257	0	0
T28	119924	119855	0	0
T29	110159	110106	0	0
T30	29436	29341	0	0
T31	250551	250479	0	0
T32	299770	299682	0	0
T36	193431	193367	0	0