Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T25,T26
1	Covered	T36,T12,T25

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T25,T26
1	0	Covered	T36,T12,T25
1	1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T32,T16,T70

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T32,T16,T70

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T32,T16,T70

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T16,T70
1	0	Covered	T12,T25,T26
1	1	Covered	T32,T16,T70

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T16,T70
0	1	Covered	T109,T111,T114
1	0	Covered	T86

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32,T16,T70
0	1	Covered	T32,T16,T70
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T32,T16,T70
1	-	Covered	T32,T16,T70

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T16,T70
0	1	Covered	T32,T16,T70
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T32,T16,T70
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T16,T70
IdleSt	0	-	-	-	-	-	-	Covered	T36,T12,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T85
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T16,T70
DebounceSt	-	0	1	0	-	-	-	Covered	T97,T98,T139
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T16,T70
DetectSt	-	-	-	-	1	-	-	Covered	T109,T111,T114
DetectSt	-	-	-	-	0	1	-	Covered	T32,T16,T70
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T16,T70
StableSt	-	-	-	-	-	-	0	Covered	T32,T16,T70
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	259	0	0
CntIncr_A	8819542	145717	0	0
CntNoWrap_A	8819542	8158583	0	0
DetectStDropOut_A	8819542	4	0	0
DetectedOut_A	8819542	746	0	0
DetectedPulseOut_A	8819542	118	0	0
DisabledIdleSt_A	8819542	8007345	0	0
DisabledNoDetection_A	8819542	8009578	0	0
EnterDebounceSt_A	8819542	137	0	0
EnterDetectSt_A	8819542	123	0	0
EnterStableSt_A	8819542	118	0	0
PulseIsPulse_A	8819542	118	0	0
StayInStableSt	8819542	627	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8819542	7087	0	0
gen_low_level_sva.LowLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	117	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	259	0	0
T13	664	0	0	0
T14	16320	0	0	0
T16	0	2	0	0
T21	0	4	0	0
T32	630	2	0	0
T33	739	0	0	0
T45	0	6	0	0
T50	0	2	0	0
T57	450	0	0	0
T68	522	0	0	0
T70	0	2	0	0
T71	0	2	0	0
T79	495	0	0	0
T99	0	2	0	0
T100	0	6	0	0
T101	0	4	0	0
T102	525	0	0	0
T103	851	0	0	0
T104	403	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	145717	0	0
T13	664	0	0	0
T14	16320	0	0	0
T16	0	34	0	0
T21	0	152	0	0
T32	630	20	0	0
T33	739	0	0	0
T45	0	164	0	0
T50	0	89	0	0
T57	450	0	0	0
T68	522	0	0	0
T70	0	66	0	0
T71	0	84	0	0
T79	495	0	0	0
T99	0	22	0	0
T100	0	257	0	0
T101	0	17883	0	0
T102	525	0	0	0
T103	851	0	0	0
T104	403	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158583	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	227	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	4	0	0
T109	30508	1	0	0
T111	9385	1	0	0
T114	0	1	0	0
T116	0	1	0	0
T120	406	0	0	0
T121	582	0	0	0
T122	14346	0	0	0
T123	8875	0	0	0
T124	409	0	0	0
T125	952	0	0	0
T126	491	0	0	0
T127	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	746	0	0
T13	664	0	0	0
T14	16320	0	0	0
T16	0	3	0	0
T21	0	6	0	0
T32	630	12	0	0
T33	739	0	0	0
T45	0	6	0	0
T50	0	2	0	0
T57	450	0	0	0
T68	522	0	0	0
T70	0	7	0	0
T71	0	3	0	0
T79	495	0	0	0
T99	0	2	0	0
T100	0	25	0	0
T101	0	19	0	0
T102	525	0	0	0
T103	851	0	0	0
T104	403	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	118	0	0
T13	664	0	0	0
T14	16320	0	0	0
T16	0	1	0	0
T21	0	2	0	0
T32	630	1	0	0
T33	739	0	0	0
T45	0	3	0	0
T50	0	1	0	0
T57	450	0	0	0
T68	522	0	0	0
T70	0	1	0	0
T71	0	1	0	0
T79	495	0	0	0
T99	0	1	0	0
T100	0	3	0	0
T101	0	2	0	0
T102	525	0	0	0
T103	851	0	0	0
T104	403	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8007345	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	151	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8009578	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	152	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	137	0	0
T13	664	0	0	0
T14	16320	0	0	0
T16	0	1	0	0
T21	0	2	0	0
T32	630	1	0	0
T33	739	0	0	0
T45	0	3	0	0
T50	0	1	0	0
T57	450	0	0	0
T68	522	0	0	0
T70	0	1	0	0
T71	0	1	0	0
T79	495	0	0	0
T99	0	1	0	0
T100	0	3	0	0
T101	0	2	0	0
T102	525	0	0	0
T103	851	0	0	0
T104	403	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	123	0	0
T13	664	0	0	0
T14	16320	0	0	0
T16	0	1	0	0
T21	0	2	0	0
T32	630	1	0	0
T33	739	0	0	0
T45	0	3	0	0
T50	0	1	0	0
T57	450	0	0	0
T68	522	0	0	0
T70	0	1	0	0
T71	0	1	0	0
T79	495	0	0	0
T99	0	1	0	0
T100	0	3	0	0
T101	0	2	0	0
T102	525	0	0	0
T103	851	0	0	0
T104	403	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	118	0	0
T13	664	0	0	0
T14	16320	0	0	0
T16	0	1	0	0
T21	0	2	0	0
T32	630	1	0	0
T33	739	0	0	0
T45	0	3	0	0
T50	0	1	0	0
T57	450	0	0	0
T68	522	0	0	0
T70	0	1	0	0
T71	0	1	0	0
T79	495	0	0	0
T99	0	1	0	0
T100	0	3	0	0
T101	0	2	0	0
T102	525	0	0	0
T103	851	0	0	0
T104	403	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	118	0	0
T13	664	0	0	0
T14	16320	0	0	0
T16	0	1	0	0
T21	0	2	0	0
T32	630	1	0	0
T33	739	0	0	0
T45	0	3	0	0
T50	0	1	0	0
T57	450	0	0	0
T68	522	0	0	0
T70	0	1	0	0
T71	0	1	0	0
T79	495	0	0	0
T99	0	1	0	0
T100	0	3	0	0
T101	0	2	0	0
T102	525	0	0	0
T103	851	0	0	0
T104	403	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	627	0	0
T13	664	0	0	0
T14	16320	0	0	0
T16	0	2	0	0
T21	0	4	0	0
T32	630	11	0	0
T33	739	0	0	0
T45	0	3	0	0
T50	0	1	0	0
T57	450	0	0	0
T68	522	0	0	0
T70	0	6	0	0
T71	0	2	0	0
T79	495	0	0	0
T99	0	1	0	0
T100	0	22	0	0
T101	0	17	0	0
T102	525	0	0	0
T103	851	0	0	0
T104	403	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7087	0	0
T12	185966	34	0	0
T25	502	6	0	0
T26	701	2	0	0
T27	522	6	0	0
T28	999	0	0	0
T29	449	9	0	0
T30	452	4	0	0
T31	521	4	0	0
T32	630	3	0	0
T33	739	0	0	0
T79	0	7	0	0
T102	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	117	0	0
T13	664	0	0	0
T14	16320	0	0	0
T16	0	1	0	0
T21	0	2	0	0
T32	630	1	0	0
T33	739	0	0	0
T45	0	3	0	0
T50	0	1	0	0
T57	450	0	0	0
T68	522	0	0	0
T70	0	1	0	0
T71	0	1	0	0
T79	495	0	0	0
T99	0	1	0	0
T100	0	3	0	0
T101	0	2	0	0
T102	525	0	0	0
T103	851	0	0	0
T104	403	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T25,T26
1	Covered	T36,T12,T25

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T25,T26
1	0	Covered	T36,T12,T25
1	1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T16,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T12,T16,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T16,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T16,T21
1	0	Covered	T12,T25,T26
1	1	Covered	T12,T16,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T21
0	1	Covered	T45,T95,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T21
0	1	Unreachable
1	0	Covered	T12,T16,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T16,T21
0	1	Covered	T12,T16,T21
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T16,T21
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T16,T21
IdleSt	0	-	-	-	-	-	-	Covered	T36,T12,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T16,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T76,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T16,T21
DetectSt	-	-	-	-	1	-	-	Covered	T45,T95,T96
DetectSt	-	-	-	-	0	1	-	Covered	T12,T16,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T16,T21
StableSt	-	-	-	-	-	-	0	Covered	T12,T16,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	230	0	0
CntIncr_A	8819542	98223	0	0
CntNoWrap_A	8819542	8158612	0	0
DetectStDropOut_A	8819542	22	0	0
DetectedOut_A	8819542	541389	0	0
DetectedPulseOut_A	8819542	60	0	0
DisabledIdleSt_A	8819542	6241363	0	0
DisabledNoDetection_A	8819542	6243644	0	0
EnterDebounceSt_A	8819542	148	0	0
EnterDetectSt_A	8819542	82	0	0
EnterStableSt_A	8819542	60	0	0
PulseIsPulse_A	8819542	60	0	0
StayInStableSt	8819542	541329	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8819542	7087	0	0
gen_low_level_sva.LowLevelEvent_A	8819542	8161124	0	0
gen_sticky_sva.StableStDropOut_A	8819542	573225	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	230	0	0
T12	185966	2	0	0
T16	0	2	0	0
T21	0	2	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	4	0	0
T65	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	7	0	0
T77	0	2	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	98223	0	0
T12	185966	47	0	0
T16	0	91	0	0
T21	0	56	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	219	0	0
T65	0	58	0	0
T74	0	48539	0	0
T75	0	46	0	0
T76	0	152	0	0
T77	0	54	0	0
T78	0	162	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158612	0	0
T12	185966	181122	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	22	0	0
T41	19055	0	0	0
T45	12251	1	0	0
T52	106721	0	0	0
T66	7406	0	0	0
T67	11520	0	0	0
T95	0	1	0	0
T96	0	4	0	0
T113	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	3	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	0	3	0	0
T146	425	0	0	0
T147	502	0	0	0
T148	527	0	0	0
T149	2200	0	0	0
T150	496	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	541389	0	0
T12	185966	12	0	0
T16	0	237	0	0
T21	0	76	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T65	0	3	0	0
T74	0	391819	0	0
T75	0	17	0	0
T76	0	37	0	0
T77	0	127	0	0
T91	0	353	0	0
T132	0	419	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	60	0	0
T12	185966	1	0	0
T16	0	1	0	0
T21	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T65	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T91	0	3	0	0
T132	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	6241363	0	0
T12	185966	180972	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	6243644	0	0
T12	185966	180986	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	148	0	0
T12	185966	1	0	0
T16	0	1	0	0
T21	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	3	0	0
T65	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	6	0	0
T77	0	1	0	0
T78	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	82	0	0
T12	185966	1	0	0
T16	0	1	0	0
T21	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	1	0	0
T65	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T95	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	60	0	0
T12	185966	1	0	0
T16	0	1	0	0
T21	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T65	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T91	0	3	0	0
T132	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	60	0	0
T12	185966	1	0	0
T16	0	1	0	0
T21	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T65	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T91	0	3	0	0
T132	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	541329	0	0
T12	185966	11	0	0
T16	0	236	0	0
T21	0	75	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T65	0	2	0	0
T74	0	391818	0	0
T75	0	16	0	0
T76	0	36	0	0
T77	0	126	0	0
T91	0	350	0	0
T132	0	418	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7087	0	0
T12	185966	34	0	0
T25	502	6	0	0
T26	701	2	0	0
T27	522	6	0	0
T28	999	0	0	0
T29	449	9	0	0
T30	452	4	0	0
T31	521	4	0	0
T32	630	3	0	0
T33	739	0	0	0
T79	0	7	0	0
T102	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	573225	0	0
T12	185966	70	0	0
T16	0	65	0	0
T21	0	123	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T65	0	106	0	0
T74	0	111	0	0
T75	0	30	0	0
T76	0	30	0	0
T77	0	47	0	0
T91	0	372	0	0
T132	0	124	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T25,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T12,T25
1	0	Covered	T12,T25,T26
1	1	Covered	T12,T25,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T16,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T12,T16,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T16,T21,T74

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T16,T21
1	0	Covered	T12,T25,T26
1	1	Covered	T12,T16,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T74,T45
0	1	Covered	T16,T93,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T74,T45
0	1	Unreachable
1	0	Covered	T21,T74,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T16,T21
0	1	Covered	T12,T16,T21
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T21,T74
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T16,T21
IdleSt	0	-	-	-	-	-	-	Covered	T12,T25,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T21,T74
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T16,T65
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T16,T21
DetectSt	-	-	-	-	1	-	-	Covered	T16,T93,T94
DetectSt	-	-	-	-	0	1	-	Covered	T21,T74,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T74,T45
StableSt	-	-	-	-	-	-	0	Covered	T21,T74,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	214	0	0
CntIncr_A	8819542	7310	0	0
CntNoWrap_A	8819542	8158628	0	0
DetectStDropOut_A	8819542	14	0	0
DetectedOut_A	8819542	12107	0	0
DetectedPulseOut_A	8819542	65	0	0
DisabledIdleSt_A	8819542	6241363	0	0
DisabledNoDetection_A	8819542	6243644	0	0
EnterDebounceSt_A	8819542	135	0	0
EnterDetectSt_A	8819542	79	0	0
EnterStableSt_A	8819542	65	0	0
PulseIsPulse_A	8819542	65	0	0
StayInStableSt	8819542	12042	0	0
gen_high_level_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_sticky_sva.StableStDropOut_A	8819542	1226464	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	214	0	0
T12	185966	1	0	0
T16	0	4	0	0
T21	0	2	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	2	0	0
T65	0	1	0	0
T74	0	4	0	0
T75	0	2	0	0
T76	0	4	0	0
T77	0	2	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7310	0	0
T12	185966	33	0	0
T16	0	204	0	0
T21	0	96	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	73	0	0
T65	0	92	0	0
T74	0	213	0	0
T75	0	35	0	0
T76	0	123	0	0
T77	0	67	0	0
T78	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158628	0	0
T12	185966	181123	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	14	0	0
T16	10070	1	0	0
T17	2061	0	0	0
T18	8858	0	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T93	0	4	0	0
T94	0	2	0	0
T99	724	0	0	0
T109	0	1	0	0
T112	0	2	0	0
T131	403	0	0	0
T151	0	2	0	0
T152	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	12107	0	0
T21	2316	102	0	0
T38	11375	0	0	0
T45	0	323	0	0
T59	31937	0	0	0
T74	0	146	0	0
T75	0	23	0	0
T76	0	451	0	0
T77	0	95	0	0
T78	0	51	0	0
T91	0	200	0	0
T95	0	42	0	0
T129	424	0	0	0
T132	0	223	0	0
T133	566	0	0	0
T134	635	0	0	0
T135	422	0	0	0
T136	642	0	0	0
T137	422	0	0	0
T138	406	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	65	0	0
T21	2316	1	0	0
T38	11375	0	0	0
T45	0	1	0	0
T59	31937	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T91	0	1	0	0
T95	0	1	0	0
T129	424	0	0	0
T132	0	1	0	0
T133	566	0	0	0
T134	635	0	0	0
T135	422	0	0	0
T136	642	0	0	0
T137	422	0	0	0
T138	406	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	6241363	0	0
T12	185966	180972	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	6243644	0	0
T12	185966	180986	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	135	0	0
T12	185966	1	0	0
T16	0	3	0	0
T21	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	1	0	0
T65	0	1	0	0
T74	0	3	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	79	0	0
T16	10070	1	0	0
T17	2061	0	0	0
T18	8858	0	0	0
T21	0	1	0	0
T45	0	1	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T95	0	1	0	0
T99	724	0	0	0
T131	403	0	0	0
T132	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	65	0	0
T21	2316	1	0	0
T38	11375	0	0	0
T45	0	1	0	0
T59	31937	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T91	0	1	0	0
T95	0	1	0	0
T129	424	0	0	0
T132	0	1	0	0
T133	566	0	0	0
T134	635	0	0	0
T135	422	0	0	0
T136	642	0	0	0
T137	422	0	0	0
T138	406	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	65	0	0
T21	2316	1	0	0
T38	11375	0	0	0
T45	0	1	0	0
T59	31937	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0
T91	0	1	0	0
T95	0	1	0	0
T129	424	0	0	0
T132	0	1	0	0
T133	566	0	0	0
T134	635	0	0	0
T135	422	0	0	0
T136	642	0	0	0
T137	422	0	0	0
T138	406	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	12042	0	0
T21	2316	101	0	0
T38	11375	0	0	0
T45	0	322	0	0
T59	31937	0	0	0
T74	0	145	0	0
T75	0	22	0	0
T76	0	449	0	0
T77	0	94	0	0
T78	0	50	0	0
T91	0	199	0	0
T95	0	41	0	0
T129	424	0	0	0
T132	0	222	0	0
T133	566	0	0	0
T134	635	0	0	0
T135	422	0	0	0
T136	642	0	0	0
T137	422	0	0	0
T138	406	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1226464	0	0
T21	2316	47	0	0
T38	11375	0	0	0
T45	0	75	0	0
T59	31937	0	0	0
T74	0	264073	0	0
T75	0	46	0	0
T76	0	204	0	0
T77	0	82	0	0
T78	0	239	0	0
T91	0	61	0	0
T95	0	69	0	0
T129	424	0	0	0
T132	0	342	0	0
T133	566	0	0	0
T134	635	0	0	0
T135	422	0	0	0
T136	642	0	0	0
T137	422	0	0	0
T138	406	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T25,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T16,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T12,T16,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T16,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T16,T21
1	0	Covered	T12,T25,T26
1	1	Covered	T12,T16,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T21
0	1	Covered	T76,T77,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T21
0	1	Unreachable
1	0	Covered	T12,T16,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T16,T21
0	1	Covered	T12,T16,T21
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T16,T21
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T16,T21
IdleSt	0	-	-	-	-	-	-	Covered	T12,T25,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T16,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T77,T91
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T16,T21
DetectSt	-	-	-	-	1	-	-	Covered	T76,T77,T91
DetectSt	-	-	-	-	0	1	-	Covered	T12,T16,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T16,T21
StableSt	-	-	-	-	-	-	0	Covered	T12,T16,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	221	0	0
CntIncr_A	8819542	1050997	0	0
CntNoWrap_A	8819542	8158621	0	0
DetectStDropOut_A	8819542	14	0	0
DetectedOut_A	8819542	230634	0	0
DetectedPulseOut_A	8819542	63	0	0
DisabledIdleSt_A	8819542	6241363	0	0
DisabledNoDetection_A	8819542	6243644	0	0
EnterDebounceSt_A	8819542	144	0	0
EnterDetectSt_A	8819542	77	0	0
EnterStableSt_A	8819542	63	0	0
PulseIsPulse_A	8819542	63	0	0
StayInStableSt	8819542	230571	0	0
gen_high_event_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_high_level_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_sticky_sva.StableStDropOut_A	8819542	590203	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	221	0	0
T12	185966	2	0	0
T16	0	2	0	0
T21	0	3	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	2	0	0
T65	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	4	0	0
T77	0	3	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1050997	0	0
T12	185966	81	0	0
T16	0	55	0	0
T21	0	122	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	75	0	0
T65	0	22	0	0
T74	0	93	0	0
T75	0	68	0	0
T76	0	74	0	0
T77	0	132	0	0
T78	0	73	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158621	0	0
T12	185966	181122	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	14	0	0
T42	15216	0	0	0
T60	10958	0	0	0
T61	15294	0	0	0
T76	14200	1	0	0
T77	0	1	0	0
T91	0	1	0	0
T93	0	3	0	0
T98	0	2	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	502	0	0	0
T158	13087	0	0	0
T159	502	0	0	0
T160	495	0	0	0
T161	402	0	0	0
T162	675	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	230634	0	0
T12	185966	11	0	0
T16	0	156	0	0
T21	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	222	0	0
T65	0	13	0	0
T74	0	671	0	0
T75	0	7	0	0
T76	0	349	0	0
T78	0	210	0	0
T95	0	59	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	63	0	0
T12	185966	1	0	0
T16	0	1	0	0
T21	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	1	0	0
T65	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T95	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	6241363	0	0
T12	185966	180972	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	6243644	0	0
T12	185966	180986	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	144	0	0
T12	185966	1	0	0
T16	0	1	0	0
T21	0	2	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	1	0	0
T65	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	77	0	0
T12	185966	1	0	0
T16	0	1	0	0
T21	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	1	0	0
T65	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	63	0	0
T12	185966	1	0	0
T16	0	1	0	0
T21	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	1	0	0
T65	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T95	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	63	0	0
T12	185966	1	0	0
T16	0	1	0	0
T21	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	1	0	0
T65	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T95	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	230571	0	0
T12	185966	10	0	0
T16	0	155	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	221	0	0
T65	0	12	0	0
T74	0	670	0	0
T75	0	6	0	0
T76	0	348	0	0
T78	0	209	0	0
T95	0	58	0	0
T132	0	487	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	590203	0	0
T12	185966	54	0	0
T16	0	186	0	0
T21	0	75	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	184	0	0
T65	0	141	0	0
T74	0	439714	0	0
T75	0	33	0	0
T76	0	258	0	0
T78	0	58	0	0
T95	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T36,T12,T25

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T12,T25
1	0	Covered	T12,T25,T26
1	1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T16,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T12,T16,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T16,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T16,T20
1	0	Covered	T36,T12,T25
1	1	Covered	T12,T16,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T20
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T20
0	1	Covered	T12,T51,T88
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T16,T20
1	-	Covered	T12,T51,T88

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T16,T20
0	1	Covered	T12,T16,T20
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T16,T20
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T16,T20
IdleSt	0	-	-	-	-	-	-	Covered	T36,T12,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T16,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T163,T164
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T16,T20
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T16,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T51,T88
StableSt	-	-	-	-	-	-	0	Covered	T12,T16,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	76	0	0
CntIncr_A	8819542	1744	0	0
CntNoWrap_A	8819542	8158766	0	0
DetectStDropOut_A	8819542	0	0	0
DetectedOut_A	8819542	2988	0	0
DetectedPulseOut_A	8819542	36	0	0
DisabledIdleSt_A	8819542	8074186	0	0
DisabledNoDetection_A	8819542	8076405	0	0
EnterDebounceSt_A	8819542	40	0	0
EnterDetectSt_A	8819542	36	0	0
EnterStableSt_A	8819542	36	0	0
PulseIsPulse_A	8819542	36	0	0
StayInStableSt	8819542	2929	0	0
gen_high_level_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	76	0	0
T12	185966	4	0	0
T16	0	2	0	0
T20	0	2	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T47	0	2	0	0
T51	0	2	0	0
T76	0	2	0	0
T88	0	2	0	0
T92	0	2	0	0
T98	0	2	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1744	0	0
T12	185966	76	0	0
T16	0	57	0	0
T20	0	19	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T47	0	24	0	0
T51	0	39	0	0
T76	0	73	0	0
T88	0	34	0	0
T92	0	45	0	0
T98	0	15	0	0
T165	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158766	0	0
T12	185966	181120	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	2988	0	0
T12	185966	78	0	0
T16	0	88	0	0
T20	0	47	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T47	0	2	0	0
T51	0	20	0	0
T76	0	37	0	0
T88	0	102	0	0
T92	0	89	0	0
T98	0	115	0	0
T165	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	36	0	0
T12	185966	2	0	0
T16	0	1	0	0
T20	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T47	0	1	0	0
T51	0	1	0	0
T76	0	1	0	0
T88	0	1	0	0
T92	0	1	0	0
T98	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8074186	0	0
T12	185966	180750	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8076405	0	0
T12	185966	180763	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	40	0	0
T12	185966	2	0	0
T16	0	1	0	0
T20	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T47	0	1	0	0
T51	0	1	0	0
T76	0	1	0	0
T88	0	1	0	0
T92	0	1	0	0
T98	0	1	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	36	0	0
T12	185966	2	0	0
T16	0	1	0	0
T20	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T47	0	1	0	0
T51	0	1	0	0
T76	0	1	0	0
T88	0	1	0	0
T92	0	1	0	0
T98	0	1	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	36	0	0
T12	185966	2	0	0
T16	0	1	0	0
T20	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T47	0	1	0	0
T51	0	1	0	0
T76	0	1	0	0
T88	0	1	0	0
T92	0	1	0	0
T98	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	36	0	0
T12	185966	2	0	0
T16	0	1	0	0
T20	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T47	0	1	0	0
T51	0	1	0	0
T76	0	1	0	0
T88	0	1	0	0
T92	0	1	0	0
T98	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	2929	0	0
T12	185966	75	0	0
T16	0	86	0	0
T20	0	45	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T47	0	1	0	0
T51	0	19	0	0
T76	0	35	0	0
T88	0	101	0	0
T92	0	88	0	0
T98	0	113	0	0
T165	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	13	0	0
T12	185966	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T47	0	1	0	0
T51	0	1	0	0
T88	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T153	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T36,T12,T25

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T25,T26
1	0	Covered	T36,T12,T25
1	1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T15,T16,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T15,T16,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T15,T16,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T20
1	0	Covered	T12,T25,T27
1	1	Covered	T15,T16,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T20
0	1	Covered	T45,T169
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T20
0	1	Covered	T20,T49,T51
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T16,T20
1	-	Covered	T20,T49,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T16,T20
0	1	Covered	T15,T16,T20
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T20
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T16,T20
IdleSt	0	-	-	-	-	-	-	Covered	T36,T12,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T16,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T167,T168,T170
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T16,T20
DetectSt	-	-	-	-	1	-	-	Covered	T45,T169
DetectSt	-	-	-	-	0	1	-	Covered	T15,T16,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T49,T51
StableSt	-	-	-	-	-	-	0	Covered	T15,T16,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	146	0	0
CntIncr_A	8819542	66815	0	0
CntNoWrap_A	8819542	8158696	0	0
DetectStDropOut_A	8819542	2	0	0
DetectedOut_A	8819542	67953	0	0
DetectedPulseOut_A	8819542	67	0	0
DisabledIdleSt_A	8819542	7966071	0	0
DisabledNoDetection_A	8819542	7968291	0	0
EnterDebounceSt_A	8819542	77	0	0
EnterDetectSt_A	8819542	69	0	0
EnterStableSt_A	8819542	67	0	0
PulseIsPulse_A	8819542	67	0	0
StayInStableSt	8819542	67857	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8819542	2688	0	0
gen_low_level_sva.LowLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	146	0	0
T15	2755	4	0	0
T16	10070	4	0	0
T17	2061	0	0	0
T20	0	2	0	0
T45	0	2	0	0
T47	0	4	0	0
T48	0	4	0	0
T49	0	2	0	0
T51	0	4	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	2	0	0
T171	0	2	0	0
T172	510	0	0	0
T173	494	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	66815	0	0
T15	2755	127	0	0
T16	10070	183	0	0
T17	2061	0	0	0
T20	0	19	0	0
T45	0	78	0	0
T47	0	48	0	0
T48	0	182	0	0
T49	0	94	0	0
T51	0	78	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	88	0	0
T171	0	45	0	0
T172	510	0	0	0
T173	494	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158696	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	2	0	0
T41	19055	0	0	0
T45	12251	1	0	0
T52	106721	0	0	0
T66	7406	0	0	0
T67	11520	0	0	0
T146	425	0	0	0
T147	502	0	0	0
T148	527	0	0	0
T149	2200	0	0	0
T150	496	0	0	0
T169	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	67953	0	0
T15	2755	281	0	0
T16	10070	173	0	0
T17	2061	0	0	0
T20	0	40	0	0
T47	0	85	0	0
T48	0	304	0	0
T49	0	27	0	0
T51	0	156	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	130	0	0
T91	0	12471	0	0
T171	0	44	0	0
T172	510	0	0	0
T173	494	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	67	0	0
T15	2755	2	0	0
T16	10070	2	0	0
T17	2061	0	0	0
T20	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	2	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	1	0	0
T91	0	1	0	0
T171	0	1	0	0
T172	510	0	0	0
T173	494	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7966071	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7968291	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	77	0	0
T15	2755	2	0	0
T16	10070	2	0	0
T17	2061	0	0	0
T20	0	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	2	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	1	0	0
T171	0	1	0	0
T172	510	0	0	0
T173	494	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	69	0	0
T15	2755	2	0	0
T16	10070	2	0	0
T17	2061	0	0	0
T20	0	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	2	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	1	0	0
T171	0	1	0	0
T172	510	0	0	0
T173	494	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	67	0	0
T15	2755	2	0	0
T16	10070	2	0	0
T17	2061	0	0	0
T20	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	2	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	1	0	0
T91	0	1	0	0
T171	0	1	0	0
T172	510	0	0	0
T173	494	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	67	0	0
T15	2755	2	0	0
T16	10070	2	0	0
T17	2061	0	0	0
T20	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	0	2	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	1	0	0
T91	0	1	0	0
T171	0	1	0	0
T172	510	0	0	0
T173	494	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	67857	0	0
T15	2755	277	0	0
T16	10070	169	0	0
T17	2061	0	0	0
T20	0	39	0	0
T47	0	82	0	0
T48	0	301	0	0
T49	0	26	0	0
T51	0	153	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	128	0	0
T91	0	12470	0	0
T171	0	42	0	0
T172	510	0	0	0
T173	494	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	2688	0	0
T12	185966	28	0	0
T13	0	1	0	0
T25	502	5	0	0
T26	701	0	0	0
T27	522	3	0	0
T28	999	0	0	0
T29	449	7	0	0
T30	452	3	0	0
T31	521	7	0	0
T32	630	0	0	0
T33	739	0	0	0
T68	0	4	0	0
T79	0	3	0	0
T102	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	38	0	0
T20	649	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	2512	1	0	0
T51	704	1	0	0
T53	882	0	0	0
T54	821	0	0	0
T56	5216	0	0	0
T91	0	1	0	0
T93	0	3	0	0
T98	0	1	0	0
T117	426	0	0	0
T118	527	0	0	0
T153	0	1	0	0
T174	0	1	0	0
T175	426	0	0	0
T176	506	0	0	0