Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T25,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T12,T25
1	0	Covered	T12,T25,T27
1	1	Covered	T12,T25,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T16,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T12,T16,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T16,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T16,T54
1	0	Covered	T12,T25,T27
1	1	Covered	T12,T16,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T54
0	1	Covered	T45,T82,T237
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T16,T54
0	1	Covered	T12,T16,T54
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T16,T54
1	-	Covered	T12,T16,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T16,T54
0	1	Covered	T12,T16,T54
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T16,T54
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T16,T54
IdleSt	0	-	-	-	-	-	-	Covered	T12,T25,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T16,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T167,T238
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T16,T54
DetectSt	-	-	-	-	1	-	-	Covered	T45,T82,T237
DetectSt	-	-	-	-	0	1	-	Covered	T12,T16,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T16,T54
StableSt	-	-	-	-	-	-	0	Covered	T12,T16,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	116	0	0
CntIncr_A	8819542	60002	0	0
CntNoWrap_A	8819542	8158726	0	0
DetectStDropOut_A	8819542	3	0	0
DetectedOut_A	8819542	16792	0	0
DetectedPulseOut_A	8819542	51	0	0
DisabledIdleSt_A	8819542	7980965	0	0
DisabledNoDetection_A	8819542	7983198	0	0
EnterDebounceSt_A	8819542	62	0	0
EnterDetectSt_A	8819542	54	0	0
EnterStableSt_A	8819542	51	0	0
PulseIsPulse_A	8819542	51	0	0
StayInStableSt	8819542	16716	0	0
gen_high_level_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	116	0	0
T12	185966	3	0	0
T16	0	6	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	2	0	0
T54	0	2	0	0
T77	0	2	0	0
T91	0	2	0	0
T153	0	4	0	0
T167	0	1	0	0
T174	0	2	0	0
T229	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	60002	0	0
T12	185966	76	0	0
T16	0	240	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	78	0	0
T54	0	39	0	0
T77	0	51	0	0
T91	0	40547	0	0
T153	0	78	0	0
T167	0	18	0	0
T174	0	76	0	0
T229	0	156	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158726	0	0
T12	185966	181121	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	3	0	0
T41	19055	0	0	0
T45	12251	1	0	0
T52	106721	0	0	0
T66	7406	0	0	0
T67	11520	0	0	0
T82	0	1	0	0
T146	425	0	0	0
T147	502	0	0	0
T148	527	0	0	0
T149	2200	0	0	0
T150	496	0	0	0
T237	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	16792	0	0
T12	185966	18	0	0
T16	0	324	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T54	0	168	0	0
T77	0	208	0	0
T91	0	12471	0	0
T153	0	286	0	0
T174	0	150	0	0
T186	0	370	0	0
T205	0	302	0	0
T229	0	243	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	51	0	0
T12	185966	1	0	0
T16	0	3	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T54	0	1	0	0
T77	0	1	0	0
T91	0	1	0	0
T153	0	2	0	0
T174	0	1	0	0
T186	0	2	0	0
T205	0	3	0	0
T229	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7980965	0	0
T12	185966	180750	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7983198	0	0
T12	185966	180763	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	62	0	0
T12	185966	2	0	0
T16	0	3	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	1	0	0
T54	0	1	0	0
T77	0	1	0	0
T91	0	1	0	0
T153	0	2	0	0
T167	0	1	0	0
T174	0	1	0	0
T229	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	54	0	0
T12	185966	1	0	0
T16	0	3	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T45	0	1	0	0
T54	0	1	0	0
T77	0	1	0	0
T91	0	1	0	0
T153	0	2	0	0
T174	0	1	0	0
T205	0	3	0	0
T229	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	51	0	0
T12	185966	1	0	0
T16	0	3	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T54	0	1	0	0
T77	0	1	0	0
T91	0	1	0	0
T153	0	2	0	0
T174	0	1	0	0
T186	0	2	0	0
T205	0	3	0	0
T229	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	51	0	0
T12	185966	1	0	0
T16	0	3	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T54	0	1	0	0
T77	0	1	0	0
T91	0	1	0	0
T153	0	2	0	0
T174	0	1	0	0
T186	0	2	0	0
T205	0	3	0	0
T229	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	16716	0	0
T12	185966	17	0	0
T16	0	319	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T54	0	167	0	0
T77	0	206	0	0
T91	0	12470	0	0
T153	0	283	0	0
T174	0	148	0	0
T186	0	367	0	0
T205	0	298	0	0
T229	0	240	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	26	0	0
T12	185966	1	0	0
T16	0	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T54	0	1	0	0
T91	0	1	0	0
T153	0	1	0	0
T186	0	1	0	0
T205	0	2	0	0
T218	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T25,T27
1	Covered	T36,T12,T25

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T25,T27
1	0	Covered	T36,T12,T25
1	1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T49,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T12,T49,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T49,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T16
1	0	Covered	T12,T25,T27
1	1	Covered	T12,T49,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T49,T50
0	1	Covered	T153
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T49,T50
0	1	Covered	T12,T93,T191
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T49,T50
1	-	Covered	T12,T93,T191

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T49,T50
0	1	Covered	T12,T49,T50
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T49,T50
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T49,T50
IdleSt	0	-	-	-	-	-	-	Covered	T36,T12,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T49,T50
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T49,T50
DetectSt	-	-	-	-	1	-	-	Covered	T153
DetectSt	-	-	-	-	0	1	-	Covered	T12,T49,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T93,T191
StableSt	-	-	-	-	-	-	0	Covered	T12,T49,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	92	0	0
CntIncr_A	8819542	75838	0	0
CntNoWrap_A	8819542	8158750	0	0
DetectStDropOut_A	8819542	1	0	0
DetectedOut_A	8819542	45363	0	0
DetectedPulseOut_A	8819542	44	0	0
DisabledIdleSt_A	8819542	7691337	0	0
DisabledNoDetection_A	8819542	7693562	0	0
EnterDebounceSt_A	8819542	47	0	0
EnterDetectSt_A	8819542	45	0	0
EnterStableSt_A	8819542	44	0	0
PulseIsPulse_A	8819542	44	0	0
StayInStableSt	8819542	45297	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8819542	6333	0	0
gen_low_level_sva.LowLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	92	0	0
T12	185966	4	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T49	0	2	0	0
T50	0	2	0	0
T76	0	2	0	0
T93	0	4	0	0
T153	0	2	0	0
T167	0	2	0	0
T188	0	4	0	0
T191	0	2	0	0
T229	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	75838	0	0
T12	185966	76	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T49	0	94	0	0
T50	0	59	0	0
T76	0	73	0	0
T93	0	90	0	0
T153	0	39	0	0
T167	0	27	0	0
T188	0	44	0	0
T191	0	57209	0	0
T229	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158750	0	0
T12	185966	181120	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1	0	0
T96	441893	0	0	0
T153	6537	1	0	0
T239	402	0	0	0
T240	599	0	0	0
T241	6203	0	0	0
T242	924	0	0	0
T243	479	0	0	0
T244	1619	0	0	0
T245	503	0	0	0
T246	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	45363	0	0
T12	185966	79	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T49	0	42	0	0
T50	0	43	0	0
T76	0	37	0	0
T93	0	279	0	0
T167	0	5	0	0
T188	0	84	0	0
T191	0	7579	0	0
T229	0	298	0	0
T240	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	44	0	0
T12	185966	2	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T76	0	1	0	0
T93	0	2	0	0
T167	0	1	0	0
T188	0	2	0	0
T191	0	1	0	0
T229	0	1	0	0
T240	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7691337	0	0
T12	185966	180750	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7693562	0	0
T12	185966	180763	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	47	0	0
T12	185966	2	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T76	0	1	0	0
T93	0	2	0	0
T153	0	1	0	0
T167	0	1	0	0
T188	0	2	0	0
T191	0	1	0	0
T229	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	45	0	0
T12	185966	2	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T76	0	1	0	0
T93	0	2	0	0
T153	0	1	0	0
T167	0	1	0	0
T188	0	2	0	0
T191	0	1	0	0
T229	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	44	0	0
T12	185966	2	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T76	0	1	0	0
T93	0	2	0	0
T167	0	1	0	0
T188	0	2	0	0
T191	0	1	0	0
T229	0	1	0	0
T240	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	44	0	0
T12	185966	2	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T76	0	1	0	0
T93	0	2	0	0
T167	0	1	0	0
T188	0	2	0	0
T191	0	1	0	0
T229	0	1	0	0
T240	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	45297	0	0
T12	185966	76	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T49	0	40	0	0
T50	0	41	0	0
T76	0	35	0	0
T93	0	276	0	0
T167	0	4	0	0
T188	0	81	0	0
T191	0	7578	0	0
T229	0	297	0	0
T240	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	6333	0	0
T12	185966	27	0	0
T14	0	12	0	0
T25	502	8	0	0
T26	701	0	0	0
T27	522	5	0	0
T28	999	0	0	0
T29	449	5	0	0
T30	452	4	0	0
T31	521	5	0	0
T32	630	0	0	0
T33	739	0	0	0
T68	0	5	0	0
T79	0	9	0	0
T102	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	22	0	0
T12	185966	1	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T93	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T186	0	1	0	0
T188	0	1	0	0
T191	0	1	0	0
T205	0	2	0	0
T218	0	1	0	0
T229	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T25,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T12,T25
1	0	Covered	T12,T25,T27
1	1	Covered	T12,T25,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T15,T16,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T15,T16,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T15,T16,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T17
1	0	Covered	T12,T25,T27
1	1	Covered	T15,T16,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T178,T204,T206
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T16,T17,T20
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T16,T17
1	-	Covered	T16,T17,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T16,T17
0	1	Covered	T15,T16,T17
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T16,T17
IdleSt	0	-	-	-	-	-	-	Covered	T12,T25,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T16,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T48,T114
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T16,T17
DetectSt	-	-	-	-	1	-	-	Covered	T178,T204,T206
DetectSt	-	-	-	-	0	1	-	Covered	T15,T16,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T17,T20
StableSt	-	-	-	-	-	-	0	Covered	T15,T16,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	160	0	0
CntIncr_A	8819542	163856	0	0
CntNoWrap_A	8819542	8158682	0	0
DetectStDropOut_A	8819542	4	0	0
DetectedOut_A	8819542	72372	0	0
DetectedPulseOut_A	8819542	72	0	0
DisabledIdleSt_A	8819542	7608996	0	0
DisabledNoDetection_A	8819542	7611213	0	0
EnterDebounceSt_A	8819542	84	0	0
EnterDetectSt_A	8819542	76	0	0
EnterStableSt_A	8819542	72	0	0
PulseIsPulse_A	8819542	72	0	0
StayInStableSt	8819542	72270	0	0
gen_high_level_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	42	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	160	0	0
T15	2755	4	0	0
T16	10070	4	0	0
T17	2061	4	0	0
T20	0	3	0	0
T45	0	2	0	0
T46	0	2	0	0
T51	0	4	0	0
T54	0	2	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T76	0	2	0	0
T77	0	2	0	0
T172	510	0	0	0
T173	494	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	163856	0	0
T15	2755	127	0	0
T16	10070	149	0	0
T17	2061	88	0	0
T20	0	38	0	0
T45	0	78	0	0
T46	0	29	0	0
T51	0	78	0	0
T54	0	39	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T76	0	73	0	0
T77	0	51	0	0
T172	510	0	0	0
T173	494	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158682	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	4	0	0
T163	0	1	0	0
T178	12353	1	0	0
T181	516	0	0	0
T182	1415	0	0	0
T183	433	0	0	0
T184	422	0	0	0
T185	423	0	0	0
T204	0	1	0	0
T206	0	1	0	0
T247	5068	0	0	0
T248	695	0	0	0
T249	645	0	0	0
T250	15195	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	72372	0	0
T15	2755	355	0	0
T16	10070	148	0	0
T17	2061	146	0	0
T20	0	95	0	0
T45	0	131	0	0
T46	0	69	0	0
T51	0	54	0	0
T54	0	199	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T76	0	102	0	0
T77	0	118	0	0
T172	510	0	0	0
T173	494	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	72	0	0
T15	2755	2	0	0
T16	10070	2	0	0
T17	2061	2	0	0
T20	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T172	510	0	0	0
T173	494	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7608996	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7611213	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	84	0	0
T15	2755	2	0	0
T16	10070	2	0	0
T17	2061	2	0	0
T20	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T172	510	0	0	0
T173	494	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	76	0	0
T15	2755	2	0	0
T16	10070	2	0	0
T17	2061	2	0	0
T20	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T172	510	0	0	0
T173	494	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	72	0	0
T15	2755	2	0	0
T16	10070	2	0	0
T17	2061	2	0	0
T20	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T172	510	0	0	0
T173	494	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	72	0	0
T15	2755	2	0	0
T16	10070	2	0	0
T17	2061	2	0	0
T20	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T172	510	0	0	0
T173	494	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	72270	0	0
T15	2755	351	0	0
T16	10070	146	0	0
T17	2061	143	0	0
T20	0	94	0	0
T45	0	129	0	0
T46	0	67	0	0
T51	0	52	0	0
T54	0	198	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T76	0	100	0	0
T77	0	117	0	0
T172	510	0	0	0
T173	494	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	42	0	0
T16	10070	2	0	0
T17	2061	1	0	0
T18	8858	0	0	0
T20	0	1	0	0
T48	0	1	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	1	0	0
T92	0	1	0	0
T98	0	2	0	0
T99	724	0	0	0
T131	403	0	0	0
T166	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T25,T27
1	Covered	T36,T12,T25

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T25,T27
1	0	Covered	T36,T12,T25
1	1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T16,T17,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T16,T17,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T16,T17,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T12,T25,T27
1	1	Covered	T16,T17,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T48
0	1	Covered	T186,T237
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T48
0	1	Covered	T17,T48,T93
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T17,T48
1	-	Covered	T17,T48,T93

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T17,T48
0	1	Covered	T16,T17,T48
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T48
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T17,T48
IdleSt	0	-	-	-	-	-	-	Covered	T36,T12,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T17,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T113
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T17,T48
DetectSt	-	-	-	-	1	-	-	Covered	T186,T237
DetectSt	-	-	-	-	0	1	-	Covered	T16,T17,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T48,T93
StableSt	-	-	-	-	-	-	0	Covered	T16,T17,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	91	0	0
CntIncr_A	8819542	7419	0	0
CntNoWrap_A	8819542	8158751	0	0
DetectStDropOut_A	8819542	2	0	0
DetectedOut_A	8819542	3507	0	0
DetectedPulseOut_A	8819542	42	0	0
DisabledIdleSt_A	8819542	8109435	0	0
DisabledNoDetection_A	8819542	8111655	0	0
EnterDebounceSt_A	8819542	48	0	0
EnterDetectSt_A	8819542	44	0	0
EnterStableSt_A	8819542	42	0	0
PulseIsPulse_A	8819542	42	0	0
StayInStableSt	8819542	3443	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8819542	6312	0	0
gen_low_level_sva.LowLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	91	0	0
T16	10070	2	0	0
T17	2061	2	0	0
T18	8858	0	0	0
T48	0	4	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T93	0	2	0	0
T99	724	0	0	0
T131	403	0	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	2	0	0
T178	0	2	0	0
T190	0	4	0	0
T229	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7419	0	0
T16	10070	136	0	0
T17	2061	44	0	0
T18	8858	0	0	0
T48	0	182	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T93	0	12	0	0
T99	724	0	0	0
T131	403	0	0	0
T165	0	81	0	0
T166	0	10	0	0
T167	0	18	0	0
T178	0	67	0	0
T190	0	106	0	0
T229	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158751	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	2	0	0
T186	13532	1	0	0
T237	905	1	0	0
T251	14253	0	0	0
T252	527	0	0	0
T253	16290	0	0	0
T254	726	0	0	0
T255	779	0	0	0
T256	420	0	0	0
T257	755	0	0	0
T258	418	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	3507	0	0
T16	10070	132	0	0
T17	2061	43	0	0
T18	8858	0	0	0
T48	0	168	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T93	0	40	0	0
T99	724	0	0	0
T131	403	0	0	0
T165	0	176	0	0
T166	0	105	0	0
T167	0	39	0	0
T178	0	38	0	0
T190	0	77	0	0
T229	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	42	0	0
T16	10070	1	0	0
T17	2061	1	0	0
T18	8858	0	0	0
T48	0	2	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T93	0	1	0	0
T99	724	0	0	0
T131	403	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T178	0	1	0	0
T190	0	2	0	0
T229	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8109435	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8111655	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	48	0	0
T16	10070	2	0	0
T17	2061	1	0	0
T18	8858	0	0	0
T48	0	2	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T93	0	1	0	0
T99	724	0	0	0
T131	403	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T178	0	1	0	0
T190	0	2	0	0
T229	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	44	0	0
T16	10070	1	0	0
T17	2061	1	0	0
T18	8858	0	0	0
T48	0	2	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T93	0	1	0	0
T99	724	0	0	0
T131	403	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T178	0	1	0	0
T190	0	2	0	0
T229	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	42	0	0
T16	10070	1	0	0
T17	2061	1	0	0
T18	8858	0	0	0
T48	0	2	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T93	0	1	0	0
T99	724	0	0	0
T131	403	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T178	0	1	0	0
T190	0	2	0	0
T229	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	42	0	0
T16	10070	1	0	0
T17	2061	1	0	0
T18	8858	0	0	0
T48	0	2	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T93	0	1	0	0
T99	724	0	0	0
T131	403	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T178	0	1	0	0
T190	0	2	0	0
T229	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	3443	0	0
T16	10070	130	0	0
T17	2061	42	0	0
T18	8858	0	0	0
T48	0	165	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T93	0	39	0	0
T99	724	0	0	0
T131	403	0	0	0
T165	0	174	0	0
T166	0	103	0	0
T167	0	37	0	0
T178	0	36	0	0
T190	0	74	0	0
T229	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	6312	0	0
T12	185966	28	0	0
T14	0	15	0	0
T25	502	5	0	0
T26	701	0	0	0
T27	522	3	0	0
T28	999	0	0	0
T29	449	4	0	0
T30	452	4	0	0
T31	521	6	0	0
T32	630	0	0	0
T33	739	0	0	0
T68	0	7	0	0
T79	0	8	0	0
T102	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	20	0	0
T17	2061	1	0	0
T18	8858	0	0	0
T19	12606	0	0	0
T48	0	1	0	0
T55	5266	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T93	0	1	0	0
T99	724	0	0	0
T109	0	1	0	0
T131	403	0	0	0
T141	0	1	0	0
T168	0	1	0	0
T190	0	1	0	0
T217	0	1	0	0
T228	688	0	0	0
T229	0	1	0	0
T230	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T25,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T12,T25
1	0	Covered	T12,T25,T26
1	1	Covered	T12,T25,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T15,T54,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T15,T54,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T15,T54,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T54,T51
1	0	Covered	T12,T25,T26
1	1	Covered	T15,T54,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T54,T51
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T54,T51
0	1	Covered	T15,T45,T91
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T54,T51
1	-	Covered	T15,T45,T91

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T54,T51
0	1	Covered	T15,T54,T51
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T54,T51
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T54,T51
IdleSt	0	-	-	-	-	-	-	Covered	T12,T25,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T54,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T77,T259,T226
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T54,T51
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T15,T54,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T45,T91
StableSt	-	-	-	-	-	-	0	Covered	T15,T54,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	129	0	0
CntIncr_A	8819542	54956	0	0
CntNoWrap_A	8819542	8158713	0	0
DetectStDropOut_A	8819542	0	0	0
DetectedOut_A	8819542	17479	0	0
DetectedPulseOut_A	8819542	62	0	0
DisabledIdleSt_A	8819542	8021423	0	0
DisabledNoDetection_A	8819542	8023653	0	0
EnterDebounceSt_A	8819542	67	0	0
EnterDetectSt_A	8819542	62	0	0
EnterStableSt_A	8819542	62	0	0
PulseIsPulse_A	8819542	62	0	0
StayInStableSt	8819542	17388	0	0
gen_high_level_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	129	0	0
T15	2755	4	0	0
T16	10070	0	0	0
T17	2061	0	0	0
T45	0	4	0	0
T51	0	2	0	0
T54	0	2	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	5	0	0
T91	0	2	0	0
T92	0	4	0	0
T167	0	6	0	0
T172	510	0	0	0
T173	494	0	0	0
T188	0	4	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	54956	0	0
T15	2755	127	0	0
T16	10070	0	0	0
T17	2061	0	0	0
T45	0	162	0	0
T51	0	39	0	0
T54	0	39	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	165	0	0
T91	0	40547	0	0
T92	0	90	0	0
T167	0	72	0	0
T172	510	0	0	0
T173	494	0	0	0
T188	0	68	0	0
T194	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158713	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	17479	0	0
T15	2755	156	0	0
T16	10070	0	0	0
T17	2061	0	0	0
T45	0	46	0	0
T51	0	182	0	0
T54	0	164	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	121	0	0
T91	0	12471	0	0
T92	0	210	0	0
T167	0	171	0	0
T172	510	0	0	0
T173	494	0	0	0
T188	0	36	0	0
T194	0	164	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	62	0	0
T15	2755	2	0	0
T16	10070	0	0	0
T17	2061	0	0	0
T45	0	2	0	0
T51	0	1	0	0
T54	0	1	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	2	0	0
T91	0	1	0	0
T92	0	2	0	0
T167	0	3	0	0
T172	510	0	0	0
T173	494	0	0	0
T188	0	2	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8021423	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8023653	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	67	0	0
T15	2755	2	0	0
T16	10070	0	0	0
T17	2061	0	0	0
T45	0	2	0	0
T51	0	1	0	0
T54	0	1	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	3	0	0
T91	0	1	0	0
T92	0	2	0	0
T167	0	3	0	0
T172	510	0	0	0
T173	494	0	0	0
T188	0	2	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	62	0	0
T15	2755	2	0	0
T16	10070	0	0	0
T17	2061	0	0	0
T45	0	2	0	0
T51	0	1	0	0
T54	0	1	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	2	0	0
T91	0	1	0	0
T92	0	2	0	0
T167	0	3	0	0
T172	510	0	0	0
T173	494	0	0	0
T188	0	2	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	62	0	0
T15	2755	2	0	0
T16	10070	0	0	0
T17	2061	0	0	0
T45	0	2	0	0
T51	0	1	0	0
T54	0	1	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	2	0	0
T91	0	1	0	0
T92	0	2	0	0
T167	0	3	0	0
T172	510	0	0	0
T173	494	0	0	0
T188	0	2	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	62	0	0
T15	2755	2	0	0
T16	10070	0	0	0
T17	2061	0	0	0
T45	0	2	0	0
T51	0	1	0	0
T54	0	1	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	2	0	0
T91	0	1	0	0
T92	0	2	0	0
T167	0	3	0	0
T172	510	0	0	0
T173	494	0	0	0
T188	0	2	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	17388	0	0
T15	2755	154	0	0
T16	10070	0	0	0
T17	2061	0	0	0
T45	0	43	0	0
T51	0	180	0	0
T54	0	162	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T77	0	117	0	0
T91	0	12470	0	0
T92	0	207	0	0
T167	0	166	0	0
T172	510	0	0	0
T173	494	0	0	0
T188	0	34	0	0
T194	0	162	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	33	0	0
T15	2755	2	0	0
T16	10070	0	0	0
T17	2061	0	0	0
T45	0	1	0	0
T55	5266	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T91	0	1	0	0
T92	0	1	0	0
T153	0	1	0	0
T167	0	1	0	0
T172	510	0	0	0
T173	494	0	0	0
T188	0	2	0	0
T205	0	1	0	0
T240	0	1	0	0
T260	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T25,T26
1	Covered	T36,T12,T25

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T25,T26
1	0	Covered	T36,T12,T25
1	1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T45,T46,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T45,T46,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T45,T46,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T16
1	0	Covered	T12,T25,T26
1	1	Covered	T45,T46,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T47
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T47
0	1	Covered	T77,T190,T188
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T46,T47
1	-	Covered	T77,T190,T188

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T45,T46,T47
0	1	Covered	T45,T46,T47
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T45,T46,T47
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T45,T46,T47
IdleSt	0	-	-	-	-	-	-	Covered	T36,T12,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T45,T46,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T261
DebounceSt	-	0	0	-	-	-	-	Covered	T45,T46,T47
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T45,T46,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T77,T190,T188
StableSt	-	-	-	-	-	-	0	Covered	T45,T46,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	77	0	0
CntIncr_A	8819542	99732	0	0
CntNoWrap_A	8819542	8158765	0	0
DetectStDropOut_A	8819542	0	0	0
DetectedOut_A	8819542	240488	0	0
DetectedPulseOut_A	8819542	37	0	0
DisabledIdleSt_A	8819542	7689954	0	0
DisabledNoDetection_A	8819542	7692180	0	0
EnterDebounceSt_A	8819542	40	0	0
EnterDetectSt_A	8819542	37	0	0
EnterStableSt_A	8819542	37	0	0
PulseIsPulse_A	8819542	37	0	0
StayInStableSt	8819542	240427	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8819542	7087	0	0
gen_low_level_sva.LowLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	77	0	0
T41	19055	0	0	0
T45	12251	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T52	106721	0	0	0
T66	7406	0	0	0
T67	11520	0	0	0
T77	0	2	0	0
T91	0	2	0	0
T93	0	2	0	0
T146	425	0	0	0
T147	502	0	0	0
T148	527	0	0	0
T149	2200	0	0	0
T150	496	0	0	0
T167	0	2	0	0
T188	0	4	0	0
T190	0	2	0	0
T191	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	99732	0	0
T41	19055	0	0	0
T45	12251	78	0	0
T46	0	29	0	0
T47	0	24	0	0
T52	106721	0	0	0
T66	7406	0	0	0
T67	11520	0	0	0
T77	0	57	0	0
T91	0	40547	0	0
T93	0	78	0	0
T146	425	0	0	0
T147	502	0	0	0
T148	527	0	0	0
T149	2200	0	0	0
T150	496	0	0	0
T167	0	27	0	0
T188	0	68	0	0
T190	0	53	0	0
T191	0	57209	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158765	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	240488	0	0
T41	19055	0	0	0
T45	12251	51	0	0
T46	0	45	0	0
T47	0	42	0	0
T52	106721	0	0	0
T66	7406	0	0	0
T67	11520	0	0	0
T77	0	39	0	0
T91	0	41	0	0
T93	0	46	0	0
T146	425	0	0	0
T147	502	0	0	0
T148	527	0	0	0
T149	2200	0	0	0
T150	496	0	0	0
T167	0	75	0	0
T188	0	84	0	0
T190	0	143	0	0
T191	0	237004	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	37	0	0
T41	19055	0	0	0
T45	12251	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	106721	0	0	0
T66	7406	0	0	0
T67	11520	0	0	0
T77	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T146	425	0	0	0
T147	502	0	0	0
T148	527	0	0	0
T149	2200	0	0	0
T150	496	0	0	0
T167	0	1	0	0
T188	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7689954	0	0
T12	185966	180750	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7692180	0	0
T12	185966	180763	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	40	0	0
T41	19055	0	0	0
T45	12251	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	106721	0	0	0
T66	7406	0	0	0
T67	11520	0	0	0
T77	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T146	425	0	0	0
T147	502	0	0	0
T148	527	0	0	0
T149	2200	0	0	0
T150	496	0	0	0
T167	0	1	0	0
T188	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	37	0	0
T41	19055	0	0	0
T45	12251	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	106721	0	0	0
T66	7406	0	0	0
T67	11520	0	0	0
T77	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T146	425	0	0	0
T147	502	0	0	0
T148	527	0	0	0
T149	2200	0	0	0
T150	496	0	0	0
T167	0	1	0	0
T188	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	37	0	0
T41	19055	0	0	0
T45	12251	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	106721	0	0	0
T66	7406	0	0	0
T67	11520	0	0	0
T77	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T146	425	0	0	0
T147	502	0	0	0
T148	527	0	0	0
T149	2200	0	0	0
T150	496	0	0	0
T167	0	1	0	0
T188	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	37	0	0
T41	19055	0	0	0
T45	12251	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	106721	0	0	0
T66	7406	0	0	0
T67	11520	0	0	0
T77	0	1	0	0
T91	0	1	0	0
T93	0	1	0	0
T146	425	0	0	0
T147	502	0	0	0
T148	527	0	0	0
T149	2200	0	0	0
T150	496	0	0	0
T167	0	1	0	0
T188	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	240427	0	0
T41	19055	0	0	0
T45	12251	49	0	0
T46	0	43	0	0
T47	0	40	0	0
T52	106721	0	0	0
T66	7406	0	0	0
T67	11520	0	0	0
T77	0	38	0	0
T91	0	39	0	0
T93	0	44	0	0
T146	425	0	0	0
T147	502	0	0	0
T148	527	0	0	0
T149	2200	0	0	0
T150	496	0	0	0
T167	0	74	0	0
T188	0	81	0	0
T190	0	142	0	0
T191	0	237002	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7087	0	0
T12	185966	34	0	0
T25	502	6	0	0
T26	701	2	0	0
T27	522	6	0	0
T28	999	0	0	0
T29	449	9	0	0
T30	452	4	0	0
T31	521	4	0	0
T32	630	3	0	0
T33	739	0	0	0
T79	0	7	0	0
T102	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	13	0	0
T77	7813	1	0	0
T114	0	1	0	0
T141	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T188	0	1	0	0
T190	9202	1	0	0
T217	0	1	0	0
T218	0	1	0	0
T219	422	0	0	0
T220	504	0	0	0
T221	11349	0	0	0
T222	404	0	0	0
T223	538	0	0	0
T224	636	0	0	0
T225	502	0	0	0
T262	0	1	0	0
T263	502	0	0	0