Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1352205319	10479	0	0
auto_block_debounce_ctl_rd_A	1352205319	1326	0	0
auto_block_out_ctl_rd_A	1352205319	1601	0	0
com_det_ctl_0_rd_A	1352205319	3319	0	0
com_det_ctl_1_rd_A	1352205319	3265	0	0
com_det_ctl_2_rd_A	1352205319	3430	0	0
com_det_ctl_3_rd_A	1352205319	3407	0	0
com_out_ctl_0_rd_A	1352205319	3710	0	0
com_out_ctl_1_rd_A	1352205319	3544	0	0
com_out_ctl_2_rd_A	1352205319	3569	0	0
com_out_ctl_3_rd_A	1352205319	3619	0	0
com_pre_det_ctl_0_rd_A	1352205319	1012	0	0
com_pre_det_ctl_1_rd_A	1352205319	950	0	0
com_pre_det_ctl_2_rd_A	1352205319	1007	0	0
com_pre_det_ctl_3_rd_A	1352205319	990	0	0
com_pre_sel_ctl_0_rd_A	1352205319	3578	0	0
com_pre_sel_ctl_1_rd_A	1352205319	3827	0	0
com_pre_sel_ctl_2_rd_A	1352205319	3801	0	0
com_pre_sel_ctl_3_rd_A	1352205319	3923	0	0
com_sel_ctl_0_rd_A	1352205319	3642	0	0
com_sel_ctl_1_rd_A	1352205319	3719	0	0
com_sel_ctl_2_rd_A	1352205319	3720	0	0
com_sel_ctl_3_rd_A	1352205319	3603	0	0
ec_rst_ctl_rd_A	1352205319	2104	0	0
intr_enable_rd_A	1352205319	1850	0	0
key_intr_ctl_rd_A	1352205319	1867	0	0
key_intr_debounce_ctl_rd_A	1352205319	1047	0	0
key_invert_ctl_rd_A	1352205319	3708	0	0
pin_allowed_ctl_rd_A	1352205319	4403	0	0
pin_out_ctl_rd_A	1352205319	3474	0	0
pin_out_value_rd_A	1352205319	3809	0	0
regwen_rd_A	1352205319	1503	0	0
ulp_ac_debounce_ctl_rd_A	1352205319	1222	0	0
ulp_ctl_rd_A	1352205319	1176	0	0
ulp_lid_debounce_ctl_rd_A	1352205319	1193	0	0
ulp_pwrb_debounce_ctl_rd_A	1352205319	1182	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	10479	0	0
T3	967042	0	0	0
T4	507152	0	0	0
T5	194417	273	0	0
T6	109305	2	0	0
T7	143114	0	0	0
T8	194988	4	0	0
T22	97139	0	0	0
T23	21412	2	0	0
T24	193176	0	0	0
T37	102937	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T292	0	7	0	0
T293	0	638	0	0
T314	0	2	0	0
T315	0	12	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	1326	0	0
T4	507152	0	0	0
T6	109305	70	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T23	21412	1	0	0
T24	193176	0	0	0
T34	0	290	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T293	0	4	0	0
T294	0	13	0	0
T299	0	11	0	0
T302	0	35	0	0
T316	0	11	0	0
T317	0	67	0	0
T318	0	3	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	1601	0	0
T4	507152	0	0	0
T6	109305	82	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T23	21412	4	0	0
T24	193176	0	0	0
T34	0	270	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T293	0	12	0	0
T294	0	6	0	0
T295	0	1	0	0
T299	0	12	0	0
T302	0	98	0	0
T316	0	15	0	0
T317	0	98	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3319	0	0
T6	109305	25	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T24	193176	0	0	0
T34	0	292	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T63	203574	0	0	0
T293	0	11	0	0
T294	0	19	0	0
T295	0	6	0	0
T299	0	2	0	0
T300	50897	0	0	0
T302	0	37	0	0
T316	0	30	0	0
T317	0	35	0	0
T318	0	3	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3265	0	0
T6	109305	36	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T24	193176	0	0	0
T34	0	305	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T63	203574	0	0	0
T293	0	13	0	0
T294	0	7	0	0
T295	0	5	0	0
T299	0	15	0	0
T300	50897	0	0	0
T302	0	36	0	0
T316	0	7	0	0
T317	0	51	0	0
T318	0	7	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3430	0	0
T6	109305	43	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T24	193176	0	0	0
T34	0	323	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T63	203574	0	0	0
T293	0	7	0	0
T294	0	3	0	0
T299	0	19	0	0
T300	50897	0	0	0
T302	0	19	0	0
T316	0	10	0	0
T317	0	67	0	0
T318	0	8	0	0
T319	0	8	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3407	0	0
T6	109305	38	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T24	193176	0	0	0
T34	0	266	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T63	203574	0	0	0
T293	0	9	0	0
T294	0	30	0	0
T295	0	6	0	0
T299	0	10	0	0
T300	50897	0	0	0
T302	0	27	0	0
T316	0	41	0	0
T317	0	68	0	0
T320	0	201	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3710	0	0
T4	507152	0	0	0
T6	109305	27	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T23	21412	3	0	0
T24	193176	0	0	0
T34	0	348	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T293	0	5	0	0
T294	0	17	0	0
T295	0	9	0	0
T299	0	2	0	0
T302	0	107	0	0
T316	0	11	0	0
T317	0	97	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3544	0	0
T2	100133	5	0	0
T3	967042	0	0	0
T4	507152	0	0	0
T5	194417	0	0	0
T6	109305	69	0	0
T7	143114	0	0	0
T22	97139	0	0	0
T23	21412	5	0	0
T24	193176	0	0	0
T34	0	318	0	0
T37	102937	0	0	0
T293	0	11	0	0
T294	0	20	0	0
T299	0	3	0	0
T302	0	78	0	0
T316	0	18	0	0
T317	0	103	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3569	0	0
T6	109305	79	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T24	193176	0	0	0
T34	0	304	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T63	203574	0	0	0
T293	0	9	0	0
T294	0	23	0	0
T295	0	5	0	0
T299	0	17	0	0
T300	50897	0	0	0
T302	0	105	0	0
T316	0	30	0	0
T317	0	102	0	0
T318	0	6	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3619	0	0
T4	507152	0	0	0
T6	109305	56	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T23	21412	2	0	0
T24	193176	0	0	0
T34	0	295	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T293	0	7	0	0
T294	0	13	0	0
T295	0	10	0	0
T299	0	1	0	0
T302	0	91	0	0
T316	0	31	0	0
T317	0	76	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	1012	0	0
T6	109305	45	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T24	193176	0	0	0
T34	0	301	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T63	203574	0	0	0
T293	0	16	0	0
T294	0	24	0	0
T295	0	13	0	0
T299	0	12	0	0
T300	50897	0	0	0
T302	0	25	0	0
T316	0	25	0	0
T317	0	37	0	0
T318	0	4	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	950	0	0
T4	507152	0	0	0
T6	109305	27	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T23	21412	9	0	0
T24	193176	0	0	0
T34	0	292	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T293	0	8	0	0
T294	0	22	0	0
T299	0	1	0	0
T302	0	27	0	0
T316	0	19	0	0
T317	0	30	0	0
T318	0	8	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	1007	0	0
T4	507152	0	0	0
T6	109305	29	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T23	21412	2	0	0
T24	193176	0	0	0
T34	0	299	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T293	0	4	0	0
T294	0	15	0	0
T299	0	15	0	0
T302	0	39	0	0
T316	0	7	0	0
T317	0	51	0	0
T319	0	6	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	990	0	0
T2	100133	3	0	0
T3	967042	0	0	0
T4	507152	0	0	0
T5	194417	0	0	0
T6	109305	40	0	0
T7	143114	0	0	0
T22	97139	0	0	0
T23	21412	0	0	0
T24	193176	0	0	0
T34	0	301	0	0
T37	102937	0	0	0
T293	0	7	0	0
T294	0	17	0	0
T299	0	11	0	0
T302	0	22	0	0
T316	0	29	0	0
T317	0	21	0	0
T319	0	2	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3578	0	0
T2	100133	14	0	0
T3	967042	0	0	0
T4	507152	0	0	0
T5	194417	0	0	0
T6	109305	122	0	0
T7	143114	0	0	0
T22	97139	0	0	0
T23	21412	0	0	0
T24	193176	0	0	0
T34	0	257	0	0
T37	102937	0	0	0
T293	0	2	0	0
T294	0	11	0	0
T299	0	23	0	0
T302	0	90	0	0
T316	0	23	0	0
T317	0	104	0	0
T318	0	5	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3827	0	0
T4	507152	0	0	0
T6	109305	107	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T23	21412	2	0	0
T24	193176	0	0	0
T34	0	308	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T294	0	3	0	0
T295	0	7	0	0
T299	0	16	0	0
T302	0	138	0	0
T316	0	12	0	0
T317	0	131	0	0
T318	0	4	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3801	0	0
T6	109305	81	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T24	193176	0	0	0
T34	0	320	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T63	203574	0	0	0
T293	0	7	0	0
T299	0	20	0	0
T300	50897	0	0	0
T302	0	155	0	0
T316	0	24	0	0
T317	0	187	0	0
T318	0	1	0	0
T319	0	16	0	0
T321	0	7	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3923	0	0
T4	507152	0	0	0
T6	109305	108	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T23	21412	3	0	0
T24	193176	0	0	0
T34	0	305	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T293	0	7	0	0
T294	0	3	0	0
T295	0	8	0	0
T299	0	1	0	0
T302	0	105	0	0
T316	0	34	0	0
T317	0	157	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3642	0	0
T6	109305	74	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T24	193176	0	0	0
T34	0	309	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T63	203574	0	0	0
T293	0	20	0	0
T294	0	16	0	0
T299	0	21	0	0
T300	50897	0	0	0
T302	0	71	0	0
T316	0	7	0	0
T317	0	144	0	0
T318	0	1	0	0
T320	0	163	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3719	0	0
T6	109305	122	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T24	193176	0	0	0
T34	0	307	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T63	203574	0	0	0
T293	0	15	0	0
T294	0	1	0	0
T295	0	2	0	0
T299	0	6	0	0
T300	50897	0	0	0
T302	0	184	0	0
T316	0	26	0	0
T317	0	101	0	0
T318	0	7	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3720	0	0
T6	109305	118	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T24	193176	0	0	0
T34	0	277	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T63	203574	0	0	0
T293	0	7	0	0
T294	0	4	0	0
T299	0	6	0	0
T300	50897	0	0	0
T302	0	56	0	0
T316	0	36	0	0
T317	0	167	0	0
T319	0	19	0	0
T321	0	9	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3603	0	0
T6	109305	100	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T24	193176	0	0	0
T34	0	328	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T63	203574	0	0	0
T293	0	8	0	0
T294	0	4	0	0
T295	0	10	0	0
T299	0	28	0	0
T300	50897	0	0	0
T302	0	95	0	0
T316	0	28	0	0
T317	0	93	0	0
T319	0	37	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	2104	0	0
T4	507152	0	0	0
T6	109305	31	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T23	21412	8	0	0
T24	193176	0	0	0
T34	0	337	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T293	0	1	0	0
T294	0	8	0	0
T295	0	4	0	0
T299	0	10	0	0
T302	0	29	0	0
T316	0	25	0	0
T317	0	40	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	1850	0	0
T2	100133	6	0	0
T3	967042	0	0	0
T4	507152	0	0	0
T5	194417	0	0	0
T6	109305	26	0	0
T7	143114	0	0	0
T22	97139	0	0	0
T23	21412	0	0	0
T24	193176	0	0	0
T34	0	328	0	0
T37	102937	0	0	0
T293	0	7	0	0
T294	0	7	0	0
T322	0	9	0	0
T323	0	11	0	0
T324	0	8	0	0
T325	0	5	0	0
T326	0	3	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	1867	0	0
T2	100133	32	0	0
T3	967042	0	0	0
T4	507152	0	0	0
T5	194417	0	0	0
T6	109305	218	0	0
T7	143114	0	0	0
T22	97139	0	0	0
T23	21412	0	0	0
T24	193176	0	0	0
T34	0	332	0	0
T37	102937	0	0	0
T293	0	4	0	0
T299	0	6	0	0
T302	0	174	0	0
T316	0	15	0	0
T317	0	181	0	0
T319	0	2	0	0
T321	0	9	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	1047	0	0
T4	507152	0	0	0
T6	109305	23	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T23	21412	6	0	0
T24	193176	0	0	0
T34	0	277	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T293	0	11	0	0
T294	0	18	0	0
T299	0	4	0	0
T302	0	25	0	0
T316	0	11	0	0
T317	0	44	0	0
T319	0	4	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3708	0	0
T4	507152	0	0	0
T6	109305	251	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T23	21412	3	0	0
T24	193176	0	0	0
T34	0	304	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T293	0	30	0	0
T294	0	34	0	0
T295	0	11	0	0
T302	0	235	0	0
T316	0	11	0	0
T317	0	315	0	0
T319	0	4	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	4403	0	0
T2	100133	32	0	0
T3	967042	0	0	0
T4	507152	0	0	0
T5	194417	0	0	0
T6	109305	480	0	0
T7	143114	0	0	0
T22	97139	0	0	0
T23	21412	0	0	0
T24	193176	0	0	0
T34	0	311	0	0
T37	102937	0	0	0
T293	0	3	0	0
T294	0	15	0	0
T295	0	7	0	0
T299	0	8	0	0
T302	0	251	0	0
T316	0	18	0	0
T317	0	350	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3474	0	0
T4	507152	0	0	0
T6	109305	254	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T23	21412	5	0	0
T24	193176	0	0	0
T34	0	314	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T293	0	20	0	0
T294	0	12	0	0
T295	0	2	0	0
T299	0	17	0	0
T302	0	128	0	0
T316	0	25	0	0
T317	0	107	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	3809	0	0
T4	507152	0	0	0
T6	109305	117	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T23	21412	8	0	0
T24	193176	0	0	0
T34	0	291	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T293	0	6	0	0
T294	0	16	0	0
T295	0	7	0	0
T302	0	155	0	0
T316	0	51	0	0
T317	0	236	0	0
T319	0	7	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	1503	0	0
T2	100133	4	0	0
T3	967042	0	0	0
T4	507152	0	0	0
T5	194417	0	0	0
T6	109305	30	0	0
T7	143114	0	0	0
T22	97139	0	0	0
T23	21412	3	0	0
T24	193176	0	0	0
T34	0	296	0	0
T37	102937	0	0	0
T293	0	22	0	0
T294	0	17	0	0
T295	0	11	0	0
T302	0	35	0	0
T316	0	17	0	0
T317	0	47	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	1222	0	0
T6	109305	39	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T24	193176	0	0	0
T34	0	278	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T63	203574	0	0	0
T293	0	26	0	0
T299	0	13	0	0
T300	50897	0	0	0
T302	0	42	0	0
T316	0	39	0	0
T317	0	52	0	0
T318	0	3	0	0
T319	0	2	0	0
T321	0	9	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	1176	0	0
T4	507152	0	0	0
T6	109305	35	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T23	21412	4	0	0
T24	193176	0	0	0
T34	0	268	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T294	0	6	0	0
T299	0	7	0	0
T302	0	31	0	0
T316	0	34	0	0
T317	0	40	0	0
T318	0	1	0	0
T319	0	1	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	1193	0	0
T2	100133	6	0	0
T3	967042	0	0	0
T4	507152	0	0	0
T5	194417	0	0	0
T6	109305	34	0	0
T7	143114	0	0	0
T22	97139	0	0	0
T23	21412	2	0	0
T24	193176	0	0	0
T34	0	331	0	0
T37	102937	0	0	0
T293	0	7	0	0
T294	0	17	0	0
T295	0	10	0	0
T302	0	32	0	0
T316	0	8	0	0
T317	0	48	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	1182	0	0
T6	109305	27	0	0
T7	143114	0	0	0
T8	194988	0	0	0
T9	49519	0	0	0
T10	240939	0	0	0
T24	193176	0	0	0
T34	0	309	0	0
T37	102937	0	0	0
T62	206194	0	0	0
T63	203574	0	0	0
T294	0	3	0	0
T295	0	2	0	0
T299	0	15	0	0
T300	50897	0	0	0
T302	0	55	0	0
T316	0	35	0	0
T317	0	27	0	0
T318	0	1	0	0
T319	0	4	0	0