Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.16 92.00 86.05 82.61 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.16 92.00 86.05 82.61 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.17 100.00 93.02 95.65 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.17 100.00 93.02 95.65 100.00 u_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_sync_reqack

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 50.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.34 100.00 96.72 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00

Line Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Module : prim_sync_reqack
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Module : prim_sync_reqack
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T3,T4
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T5
ODD - 1 Covered T1,T3,T4
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T5


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T5


Assert Coverage for Module : prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 2147483647 6315 0 0
SyncReqAckHoldReq 45092514 4094 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 6315 0 0
T1 2003408 24 0 0
T2 400532 4 0 0
T3 3868168 34 0 0
T4 2028608 47 0 0
T5 777668 0 0 0
T6 437220 38 0 0
T7 572456 24 0 0
T8 0 77 0 0
T9 0 4 0 0
T10 0 4 0 0
T11 0 4 0 0
T12 157994 5 0 0
T13 0 1 0 0
T14 0 1 0 0
T15 0 6 0 0
T16 0 7 0 0
T17 0 2 0 0
T18 0 1 0 0
T19 0 2 0 0
T20 0 4 0 0
T21 0 1 0 0
T22 388556 0 0 0
T23 85648 0 0 0
T24 772704 0 0 0
T25 248515 0 0 0
T26 52146 0 0 0
T27 261356 0 0 0
T28 119924 0 0 0
T29 110159 0 0 0
T30 29436 0 0 0
T31 250551 0 0 0
T32 299770 0 0 0
T33 51784 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 45092514 4094 0 0
T1 4132 2 0 0
T2 1632 2 0 0
T3 7972 4 0 0
T4 8448 4 0 0
T5 1636 0 0 0
T6 17844 1 0 0
T7 4088 2 0 0
T9 0 2 0 0
T10 0 2 0 0
T11 0 2 0 0
T12 185966 5 0 0
T13 0 1 0 0
T14 0 1 0 0
T15 0 6 0 0
T16 0 7 0 0
T17 0 2 0 0
T18 0 1 0 0
T19 0 2 0 0
T20 0 4 0 0
T21 0 1 0 0
T22 1616 0 0 0
T23 1712 0 0 0
T24 1608 0 0 0
T25 502 0 0 0
T26 701 0 0 0
T27 522 0 0 0
T28 999 0 0 0
T29 449 0 0 0
T30 452 0 0 0
T31 521 0 0 0
T32 630 0 0 0
T33 739 0 0 0
T34 0 4 0 0
T35 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T3,T4
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T5
ODD - 1 Covered T1,T3,T4
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T5


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T5


Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 1352205319 631 0 0
SyncReqAckHoldReq 9068243 199 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 1352205319 631 0 0
T1 500852 11 0 0
T2 100133 1 0 0
T3 967042 17 0 0
T4 507152 4 0 0
T5 194417 0 0 0
T6 109305 9 0 0
T7 143114 8 0 0
T8 0 17 0 0
T9 0 1 0 0
T10 0 1 0 0
T11 0 1 0 0
T22 97139 0 0 0
T23 21412 0 0 0
T24 193176 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 9068243 199 0 0
T1 1033 1 0 0
T2 408 1 0 0
T3 1993 2 0 0
T4 2112 2 0 0
T5 409 0 0 0
T6 4461 0 0 0
T7 1022 1 0 0
T9 0 1 0 0
T10 0 1 0 0
T11 0 1 0 0
T22 404 0 0 0
T23 428 0 0 0
T24 402 0 0 0
T34 0 2 0 0
T35 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T3,T4
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T5
ODD - 1 Covered T1,T3,T4
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T5


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T5


Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 1352205319 1825 0 0
SyncReqAckHoldReq 9068243 1020 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 1352205319 1825 0 0
T1 500852 7 0 0
T2 100133 1 0 0
T3 967042 4 0 0
T4 507152 8 0 0
T5 194417 0 0 0
T6 109305 10 0 0
T7 143114 10 0 0
T8 0 20 0 0
T9 0 1 0 0
T10 0 1 0 0
T11 0 1 0 0
T22 97139 0 0 0
T23 21412 0 0 0
T24 193176 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 9068243 1020 0 0
T1 1033 1 0 0
T2 408 1 0 0
T3 1993 2 0 0
T4 2112 2 0 0
T5 409 0 0 0
T6 4461 1 0 0
T7 1022 1 0 0
T9 0 1 0 0
T10 0 1 0 0
T11 0 1 0 0
T22 404 0 0 0
T23 428 0 0 0
T24 402 0 0 0
T34 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T1,T3,T4
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T5
ODD - 1 Covered T1,T3,T4
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T5


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T5


Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 1352205319 1644 0 0
SyncReqAckHoldReq 9068243 1245 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 1352205319 1644 0 0
T1 500852 5 0 0
T2 100133 1 0 0
T3 967042 3 0 0
T4 507152 16 0 0
T5 194417 0 0 0
T6 109305 9 0 0
T7 143114 2 0 0
T8 0 20 0 0
T9 0 1 0 0
T10 0 1 0 0
T11 0 1 0 0
T22 97139 0 0 0
T23 21412 0 0 0
T24 193176 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 9068243 1245 0 0
T1 1033 1 0 0
T2 408 1 0 0
T3 1993 2 0 0
T4 2112 2 0 0
T5 409 0 0 0
T6 4461 0 0 0
T7 1022 1 0 0
T9 0 1 0 0
T10 0 1 0 0
T11 0 1 0 0
T22 404 0 0 0
T23 428 0 0 0
T24 402 0 0 0
T34 0 2 0 0
T35 0 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T3
ODD - 1 Covered T3,T4,T7
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T1,T2,T3
EVEN 0 - Covered T1,T2,T5
ODD - 1 Covered T3,T4,T7
ODD - 0 Covered T1,T2,T3


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T5


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T5


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 1352205319 1216 0 0
SyncReqAckHoldReq 9068243 639 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 1352205319 1216 0 0
T1 500852 1 0 0
T2 100133 1 0 0
T3 967042 10 0 0
T4 507152 19 0 0
T5 194417 0 0 0
T6 109305 10 0 0
T7 143114 4 0 0
T8 0 20 0 0
T9 0 1 0 0
T10 0 1 0 0
T11 0 1 0 0
T22 97139 0 0 0
T23 21412 0 0 0
T24 193176 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 9068243 639 0 0
T1 1033 1 0 0
T2 408 1 0 0
T3 1993 2 0 0
T4 2112 2 0 0
T5 409 0 0 0
T6 4461 1 0 0
T7 1022 1 0 0
T9 0 1 0 0
T10 0 1 0 0
T11 0 1 0 0
T22 404 0 0 0
T23 428 0 0 0
T24 402 0 0 0
T34 0 2 0 0

Line Coverage for Instance : tb.dut.u_prim_sync_reqack
Line No.TotalCoveredPercent
TOTAL3636100.00
CONT_ASSIGN5500
CONT_ASSIGN19411100.00
CONT_ASSIGN19511100.00
ALWAYS2191212100.00
ALWAYS2631212100.00
ALWAYS30755100.00
ALWAYS31655100.00
CONT_ASSIGN33500
ALWAYS33900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 unreachable
194 1 1
195 1 1
219 1 1
222 1 1
223 1 1
225 1 1
229 1 1
230 1 1
233 1 1
234 1 1
MISSING_ELSE
241 1 1
242 1 1
245 1 1
246 1 1
MISSING_ELSE
263 1 1
266 1 1
267 1 1
269 1 1
273 1 1
274 1 1
277 1 1
278 1 1
MISSING_ELSE
285 1 1
286 1 1
289 1 1
290 1 1
MISSING_ELSE
307 1 1
308 1 1
309 1 1
311 1 1
312 1 1
316 1 1
317 1 1
318 1 1
320 1 1
321 1 1
335 unreachable
339 unreachable
340 unreachable
341 unreachable
342 unreachable
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_prim_sync_reqack
TotalCoveredPercent
Conditions6350.00
Logical6350.00
Non-Logical00
Event00

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT12,T13,T14
11CoveredT12,T13,T14

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT12,T13,T14

Branch Coverage for Instance : tb.dut.u_prim_sync_reqack
Line No.TotalCoveredPercent
Branches 12 12 100.00
CASE 225 4 4 100.00
CASE 269 4 4 100.00
IF 307 2 2 100.00
IF 316 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs) -2-: 233 if (gen_nrz_hs_protocol.src_handshake) -3-: 245 if (gen_nrz_hs_protocol.src_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T12,T13,T14
EVEN 0 - Covered T12,T13,T14
ODD - 1 Covered T12,T15,T16
ODD - 0 Covered T12,T13,T14


LineNo. Expression -1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs) -2-: 277 if (gen_nrz_hs_protocol.dst_handshake) -3-: 289 if (gen_nrz_hs_protocol.dst_handshake)

Branches:
-1--2--3-StatusTests
EVEN 1 - Covered T12,T13,T14
EVEN 0 - Covered T36,T12,T25
ODD - 1 Covered T12,T15,T16
ODD - 0 Covered T12,T13,T14


LineNo. Expression -1-: 307 if ((!rst_src_ni))

Branches:
-1-StatusTests
1 Covered T36,T12,T25
0 Covered T36,T12,T25


LineNo. Expression -1-: 316 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T36,T12,T25
0 Covered T36,T12,T25


Assert Coverage for Instance : tb.dut.u_prim_sync_reqack
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SyncReqAckAckNeedsReq 1285302250 999 0 0
SyncReqAckHoldReq 8819542 991 0 0


SyncReqAckAckNeedsReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 1285302250 999 0 0
T12 157994 5 0 0
T13 0 1 0 0
T14 0 1 0 0
T15 0 6 0 0
T16 0 7 0 0
T17 0 2 0 0
T18 0 1 0 0
T19 0 2 0 0
T20 0 4 0 0
T21 0 1 0 0
T25 248515 0 0 0
T26 52146 0 0 0
T27 261356 0 0 0
T28 119924 0 0 0
T29 110159 0 0 0
T30 29436 0 0 0
T31 250551 0 0 0
T32 299770 0 0 0
T33 51784 0 0 0

SyncReqAckHoldReq
NameAttemptsReal SuccessesFailuresIncomplete
Total 8819542 991 0 0
T12 185966 5 0 0
T13 0 1 0 0
T14 0 1 0 0
T15 0 6 0 0
T16 0 7 0 0
T17 0 2 0 0
T18 0 1 0 0
T19 0 2 0 0
T20 0 4 0 0
T21 0 1 0 0
T25 502 0 0 0
T26 701 0 0 0
T27 522 0 0 0
T28 999 0 0 0
T29 449 0 0 0
T30 452 0 0 0
T31 521 0 0 0
T32 630 0 0 0
T33 739 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%