SYSRST_CTRL Simulation Results

Wednesday December 20 2023 20:02:55 UTC

GitHub Revision: `9601d3bbdd`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 30104064247514112511662306974640835321092728874679524971043777466318536599043

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.340s	2.108ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	7.870s	2.459ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.890s	2.397ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	7.070s	2.543ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	10.820s	4.012ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.280s	2.059ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	3.434m	49.945ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	13.390s	3.167ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.380s	2.056ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.280s	2.059ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	13.390s	3.167ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	9.055m	204.065ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	6.040m	152.445ms	94	100	94.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	13.122m	287.179ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	13.988m	1.783s	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.610s	2.513ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.360s	2.171ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	32.654m	712.650ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.840s	2.610ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	11.435m	3.047s	44	50	88.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	25.620s	41.608ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	30.468m	738.201ms	47	50	94.00
V2	alert_test	sysrst_ctrl_alert_test	6.130s	2.015ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.230s	2.009ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	8.500s	2.045ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	8.500s	2.045ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	10.820s	4.012ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.280s	2.059ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	13.390s	3.167ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	31.420s	8.417ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	10.820s	4.012ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.280s	2.059ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	13.390s	3.167ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	31.420s	8.417ms	20	20	100.00
V2		TOTAL			677	692	97.83
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.711m	42.011ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.928m	42.444ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.928m	42.444ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	8.955m	2.209s	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			909	932	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.39	96.05	100.00	97.44	98.78	99.63	93.16

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 10 failures:

Test sysrst_ctrl_stress_all has 2 failures.

0.sysrst_ctrl_stress_all.4853384607710603681778586973708601863912759712356765440328694930003122242827
Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 4205414699 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 4342914699 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 6587914699 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
  UVM_INFO @ 6588009178 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
  UVM_INFO @ 6609052530 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_auto_blk_key_output_vseq

46.sysrst_ctrl_stress_all.27300698192509986523824263090590296972742094928221636548351584978189212014418
Line 564, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 6353200887 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 6455700887 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 6995700887 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
  UVM_INFO @ 6995817058 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
  UVM_INFO @ 7030735186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.

9.sysrst_ctrl_stress_all_with_rand_reset.68659277258760567889020473535565578288335486091507364658275152396487802751933
Line 621, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 38591893595 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 40214393595 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:214) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 40214393595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.sysrst_ctrl_stress_all_with_rand_reset.71076650221734867000749769690345310260220851696751303234273510405000540104063
Line 713, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 62628475514 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 62725975514 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 64380975514 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
  UVM_INFO @ 64381105976 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
  UVM_INFO @ 64391752396 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_common_vseq

Test sysrst_ctrl_ultra_low_pwr has 6 failures.

13.sysrst_ctrl_ultra_low_pwr.51911421502911424454960816684948179180727650049914454013656497063997981490184
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 5713530640 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 5821030640 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 9121030640 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
  UVM_INFO @ 9121272181 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
  UVM_INFO @ 9155272413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

22.sysrst_ctrl_ultra_low_pwr.65928667532985372309413159108303981880783491086710237564155640417868654980813
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2480773059 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 2483273059 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 4433273059 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disble Z3 wakeup check
  UVM_INFO @ 4433381703 ps: (sysrst_ctrl_base_vseq.sv:119) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Unhandled interrupt detected
  UVM_INFO @ 4445199105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 3 failures:
- Test sysrst_ctrl_stress_all has 1 failures.
  - 5.sysrst_ctrl_stress_all.9160818478087022333276349897008898044924481117932424694645646856892918840064
    Line 559, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 4255790359 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 4255790359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.
  - 7.sysrst_ctrl_stress_all_with_rand_reset.89305645018252279094397882642768006420879974770427686764412843817504012153380
    Line 630, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 34582716648 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 34582716648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.sysrst_ctrl_stress_all_with_rand_reset.44174196186360229683029355263702718436099523215901248834122171663190634467937
    Line 692, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 112387227334 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 112387227334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_combo_detect_vseq.sv:239) [sysrst_ctrl_combo_detect_vseq] Check failed rdata == intr_actions (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

3.sysrst_ctrl_stress_all_with_rand_reset.8991236329036148092989069648255362721323793303250901052322307497148241575868
Line 673, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 59495584646 ps: (sysrst_ctrl_combo_detect_vseq.sv:239) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed rdata == intr_actions (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 59495584646 ps: (sysrst_ctrl_combo_detect_vseq.sv:244) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 59495584646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:35) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

12.sysrst_ctrl_stress_all_with_rand_reset.33119238487144981934382232940317323581635873251020191164632345120401021766358
Line 617, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 26982586181 ps: (sysrst_ctrl_pin_access_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 26982586181 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 26982586181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:36) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

15.sysrst_ctrl_stress_all_with_rand_reset.19580951989852625552235123084461672372286449882114256230894854812592384433331
Line 581, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 18002497368 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 18002497368 ps: (sysrst_ctrl_pin_access_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key1_in == rdata_key1_in (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 18002497368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

25.sysrst_ctrl_combo_detect_with_pre_cond.24221826580410040907436461431277407469427508019332098190797769915142201140676
Line 606, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 50751958995 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4
  UVM_INFO @ 61003065111 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x24
  UVM_INFO @ 61003185111 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xf
  UVM_INFO @ 61297185111 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
  UVM_INFO @ 61311958995 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 19

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(3) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

32.sysrst_ctrl_combo_detect_with_pre_cond.28086321661364963332949333653439145233106411366696986043270069802448036457130
Line 589, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 33259528037 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(3) +/-4
  UVM_ERROR @ 33259528037 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-4
  UVM_INFO @ 33259528037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

33.sysrst_ctrl_combo_detect_with_pre_cond.84985250412217002749831002735717730982117737789436059949707569350290717974457
Line 652, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 189224278198 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 189224278198 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 189224278198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:116) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key0_out_value == cfg.vif.key0_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

35.sysrst_ctrl_stress_all_with_rand_reset.21821280577077633791011694065999158031207549171234264174716037148432339652773
Line 563, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4330025990 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:116) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key0_out_value == cfg.vif.key0_out (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 4330025990 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4330025990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

37.sysrst_ctrl_combo_detect_with_pre_cond.12181548463041539103530224039675422304412495356809449370059670324083340182021
Line 573, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 15222076937 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-4
  UVM_INFO @ 15227076937 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0
  UVM_INFO @ 15377076937 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 15397076937 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 15907076937 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

50.sysrst_ctrl_combo_detect_with_pre_cond.80672363184721957274292576569547650417010193706614439075050583812196978100203
Line 576, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/50.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13899427947 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(5) +/-4
  UVM_ERROR @ 13899427947 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-4
  UVM_INFO @ 13899427947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

86.sysrst_ctrl_combo_detect_with_pre_cond.9396882714932626371882381734589800319828865389055194581182610314000886618836
Line 581, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/86.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 30443116000 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-4
  UVM_ERROR @ 30443116000 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(3) +/-4
  UVM_INFO @ 30443116000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---