Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1663

1

T16

40

T18

3

T20

5

auto[1]

547

1

T18

1

T23

4

T40

10

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1691

1

T16

35

T18

3

T20

2

auto[1]

519

1

T16

5

T18

1

T20

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1647

1

T16

25

T18

4

T20

3

auto[1]

563

1

T16

15

T20

2

T43

11

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1617

1

T16

32

T18

3

T23

16

auto[1]

593

1

T16

8

T18

1

T20

5

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2044

1

T16

22

T18

4

T20

5

auto[1]

166

1

T16

18

T43

11

T218

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2065

1

T16

37

T18

4

T20

5

auto[1]

145

1

T16

3

T41

19

T43

22

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2029

1

T16

37

T18

4

T20

5

auto[1]

181

1

T16

3

T23

4

T41

28

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2083

1

T16

40

T18

4

T20

5

auto[1]

127

1

T41

6

T159

4

T107

5

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2039

1

T16

35

T18

3

T20

5

auto[1]

171

1

T16

5

T18

1

T23

4

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1761

1

T16

37

T18

4

T20

3

auto[1]

449

1

T16

3

T20

2

T40

11

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	874	1			T20	5		T40	21		T42	20
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	57	1			T16	10		T43	3		T349	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	38	1			T18	1		T159	7		T218	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	14	1			T16	5		T244	2		T349	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	40	1			T233	3		T337	5		T148	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	5	1			T337	2		T347	3		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	30	1			T107	5		T350	2		T351	8
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	5	1			T341	1		T342	1		T260	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	53	1			T105	3		T352	1		T353	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	27	1			T126	5		T341	5		T354	8
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	37	1			T23	4		T41	9		T233	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T275	1		T355	1		T356	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	19	1			T159	4		T342	3		T344	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T343	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T357	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	37	1			T43	6		T159	5		T273	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	18	1			T350	1		T358	3		T71	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	13	1			T337	1		T359	1		T353	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	7	1			T341	4		T71	3		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	2	1			T343	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	2	1			T360	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	2	1			T342	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	13	1			T41	13		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	4	1			T16	3		T361	1		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	10	1			T41	6		T362	4		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T363	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

138

1

T40

10

T41

6

T54

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

85

1

T40

7

T43

3

T67

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

40

1

T339

6

T280

4

T188

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

99

1

T41

22

T233

2

T299

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

53

1

T105

3

T159

5

T50

11

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

67

1

T16

3

T339

5

T114

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T264

5

T364

1

T365

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

104

1

T16

10

T77

10

T66

14

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

60

1

T54

5

T288

3

T212

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

26

1

T43

3

T250

4

T188

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T336

3

T337

5

T117

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

70

1

T44

6

T366

1

T244

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T367

1

T337

1

T290

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T20

2

T250

4

T336

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

18

1

T67

1

T288

2

T336

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

83

1

T43

3

T159

4

T275

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

57

1

T23

4

T42

8

T54

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

16

1

T40

4

T42

4

T337

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T77

1

T338

3

T72

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

67

1

T20

3

T44

8

T126

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T18

1

T54

1

T67

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

9

1

T113

6

T85

1

T368

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T336

1

T282

3

T369

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

68

1

T98

10

T44

7

T233

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T42

5

T50

3

T298

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T98

3

T44

3

T67

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T112

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

29

1

T16

5

T42

3

T274

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T233

3

T172

2

T349

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

19

1

T336

1

T113

5

T280

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T66

2

T282

2

T365

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded