Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T56

10

T22

10

T170

9

auto[1]

1102

1

T56

10

T22

10

T170

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

502

1

T56

5

T22

5

T170

4

from_0to1

501

1

T56

4

T22

5

T170

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1105

1

T56

11

T22

11

T170

10

auto[1]

1081

1

T56

9

T22

9

T170

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T56

10

T22

10

T170

9

auto[1]

1090

1

T56

10

T22

10

T170

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T56

1

T51

1

T209

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T22

1

T170

1

T171

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T56

1

T22

2

T164

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T170

1

T335

3

T164

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T171

1

T335

2

T164

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T170

1

T335

1

T333

2

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T56

2

T22

1

T176

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T171

1

T51

1

T164

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T56

1

T22

2

T170

1

auto[1]

from_1to0

auto[0]

auto[1]

52

1

T171

3

T333

1

T50

1

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T56

1

T170

1

T335

2

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T56

1

T171

1

T333

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T22

2

T170

1

T171

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T56

2

T22

1

T170

1

auto[1]

from_0to1

auto[1]

auto[0]

77

1

T22

1

T170

2

T333

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T171

1

T333

1

T209

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1073

1

T56

9

T22

12

T170

11

auto[1]

1113

1

T56

11

T22

8

T170

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

521

1

T56

4

T22

5

T170

7

from_0to1

514

1

T56

4

T22

5

T170

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T56

13

T22

12

T170

10

auto[1]

1102

1

T56

7

T22

8

T170

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T56

10

T22

10

T170

14

auto[1]

1078

1

T56

10

T22

10

T170

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T170

2

T171

2

T333

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T56

1

T22

2

T164

1

auto[0]

from_1to0

auto[1]

auto[0]

78

1

T22

1

T170

1

T335

2

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T170

1

T335

2

T333

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T22

3

T170

2

T171

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T56

1

T170

2

T171

2

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T56

2

T335

3

T333

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T208

2

T209

2

T383

2

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T170

1

T335

1

T333

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T56

2

T22

1

T171

2

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T56

1

T170

1

T333

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T22

1

T170

1

T171

1

auto[1]

from_0to1

auto[0]

auto[0]

79

1

T170

1

T333

1

T176

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T56

1

T170

1

T208

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T22

1

T170

1

T171

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T22

1

T171

1

T208

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T56

6

T22

5

T170

9

auto[1]

1053

1

T56

14

T22

15

T170

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

506

1

T56

5

T22

6

T170

4

from_0to1

509

1

T56

5

T22

6

T170

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T56

8

T22

10

T170

7

auto[1]

1123

1

T56

12

T22

10

T170

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1097

1

T56

11

T22

6

T170

9

auto[1]

1089

1

T56

9

T22

14

T170

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T170

1

T171

3

T51

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T22

1

T171

1

T335

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T383

1

T251

1

T234

1

auto[0]

from_1to0

auto[1]

auto[1]

81

1

T56

1

T170

1

T333

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T335

1

T176

2

T51

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T56

1

T170

2

T335

2

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T171

2

T333

1

T164

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T171

1

T333

1

T164

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T56

1

T171

1

T335

1

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T56

1

T22

2

T333

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T56

1

T22

1

T176

2

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T56

1

T22

2

T170

2

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T22

2

T171

1

T335

1

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T22

2

T171

1

T333

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T56

1

T170

1

T333

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T56

3

T22

2

T170

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107

1

T56

15

T22

13

T170

9

auto[1]

1079

1

T56

5

T22

7

T170

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

524

1

T56

3

T22

3

T170

7

from_0to1

532

1

T56

2

T22

3

T170

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1056

1

T56

9

T22

12

T170

10

auto[1]

1130

1

T56

11

T22

8

T170

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1088

1

T56

12

T22

7

T170

9

auto[1]

1098

1

T56

8

T22

13

T170

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T56

2

T335

2

T208

1

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T22

1

T170

2

T171

1

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T170

2

T171

1

T335

2

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T56

1

T22

2

T170

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T171

1

T335

2

T164

2

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T22

2

T170

1

T335

1

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T56

2

T164

3

T209

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T335

1

T176

1

T209

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T333

1

T50

1

T384

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T170

1

T171

1

T176

2

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T170

1

T335

1

T333

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T335

1

T333

2

T176

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T22

1

T170

1

T171

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T170

2

T171

1

T208

2

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T170

2

T171

2

T335

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T170

1

T335

2

T333

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T56

13

T22

11

T170

12

auto[1]

1061

1

T56

7

T22

9

T170

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

539

1

T56

5

T22

5

T170

3

from_0to1

531

1

T56

4

T22

6

T170

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1117

1

T56

13

T22

7

T170

13

auto[1]

1069

1

T56

7

T22

13

T170

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1114

1

T56

16

T22

12

T170

8

auto[1]

1072

1

T56

4

T22

8

T170

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T56

1

T333

1

T176

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T56

1

T170

2

T171

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T56

1

T22

1

T171

1

auto[0]

from_1to0

auto[1]

auto[1]

73

1

T56

1

T22

1

T335

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T56

2

T22

1

T171

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T170

1

T335

3

T333

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T22

3

T335

1

T176

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T56

1

T170

1

T335

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T22

1

T333

1

T164

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T170

1

T171

2

T335

3

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T56

1

T22

2

T333

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T333

1

T383

2

T166

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T56

1

T171

1

T333

2

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T22

1

T171

2

T176

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T335

1

T383

1

T251

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T22

1

T170

1

T333

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1047

1

T56

8

T22

10

T170

10

auto[1]

1139

1

T56

12

T22

10

T170

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

537

1

T56

4

T22

6

T170

4

from_0to1

542

1

T56

4

T22

7

T170

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T56

12

T22

10

T170

6

auto[1]

1107

1

T56

8

T22

10

T170

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1090

1

T56

7

T22

8

T170

10

auto[1]

1096

1

T56

13

T22

12

T170

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T22

1

T171

1

T335

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T56

1

T22

1

T333

1

auto[0]

from_1to0

auto[1]

auto[0]

82

1

T170

1

T335

1

T164

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T22

1

T170

1

T335

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T22

1

T333

1

T51

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T335

2

T164

2

T209

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T56

1

T22

1

T170

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T56

1

T22

2

T171

2

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T170

2

T335

1

T176

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T56

1

T22

1

T335

1

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T22

2

T171

3

T333

2

auto[1]

from_1to0

auto[1]

auto[1]

77

1

T56

2

T335

1

T333

2

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T56

1

T22

1

T176

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T56

1

T171

2

T335

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T170

2

T335

1

T333

3

auto[1]

from_0to1

auto[1]

auto[1]

79

1

T22

2

T170

1

T335

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1104

1

T56

11

T22

9

T170

9

auto[1]

1082

1

T56

9

T22

11

T170

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

520

1

T56

6

T22

4

T170

4

from_0to1

508

1

T56

6

T22

4

T170

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1093

1

T56

10

T22

11

T170

11

auto[1]

1093

1

T56

10

T22

9

T170

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T56

12

T22

9

T170

14

auto[1]

1088

1

T56

8

T22

11

T170

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T171

1

T333

1

T51

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T56

1

T22

1

T170

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T56

1

T176

2

T208

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T22

1

T170

1

T176

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T56

1

T22

1

T170

2

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T56

1

T335

1

T164

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T56

1

T171

1

T333

1

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T171

1

T335

1

T333

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T56

1

T170

1

T335

2

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T22

1

T171

2

T335

1

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T56

1

T22

1

T170

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T56

2

T335

1

T333

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T56

1

T22

1

T176

2

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T56

1

T170

1

T335

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T56

1

T22

1

T170

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T22

1

T170

1

T164

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1134

1

T56

10

T22

10

T170

13

auto[1]

1052

1

T56

10

T22

10

T170

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

532

1

T56

5

T22

6

T170

5

from_0to1

524

1

T56

4

T22

6

T170

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T56

10

T22

10

T170

12

auto[1]

1107

1

T56

10

T22

10

T170

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1101

1

T56

11

T22

13

T170

11

auto[1]

1085

1

T56

9

T22

7

T170

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T56

1

T335

2

T333

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T170

2

T171

2

T335

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T56

1

T22

1

T170

1

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T176

1

T208

1

T67

2

auto[0]

from_0to1

auto[0]

auto[0]

82

1

T56

1

T22

1

T170

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T170

1

T171

1

T176

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T22

1

T170

1

T335

1

auto[0]

from_0to1

auto[1]

auto[1]

77

1

T56

1

T170

1

T171

3

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T170

1

T333

1

T209

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T56

1

T22

2

T171

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T56

1

T22

1

T170

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T56

1

T22

2

T171

2

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T22

3

T170

1

T335

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T171

1

T335

2

T164

2

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T56

1

T208

1

T50

2

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T56

1

T22

1

T333

1