Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	142949	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

109858

1

T5

284

T6

18

T7

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	127047	1			T5	77		T6	25		T7	16
values[0x0]	62832	1			T5	109		T6	12		T7	5
values[0x1]	62928	1			T5	141		T6	8		T7	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	116150	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

136657

1

T5

309

T6

20

T7

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1525	1			T4	2		T9	4		T53	5
valid_sources[0x01]	898	1			T4	1		T9	10		T53	6
valid_sources[0x02]	837	1			T5	25		T3	1		T4	1
valid_sources[0x03]	893	1			T4	5		T9	6		T53	5
valid_sources[0x04]	886	1			T24	16		T4	7		T9	7
valid_sources[0x05]	711	1			T4	2		T9	2		T53	6
valid_sources[0x06]	738	1			T5	18		T4	6		T9	4
valid_sources[0x07]	842	1			T2	10		T4	3		T9	2
valid_sources[0x08]	886	1			T2	17		T3	3		T4	9
valid_sources[0x09]	901	1			T2	38		T4	4		T9	6
valid_sources[0x0a]	925	1			T5	16		T2	2		T9	6
valid_sources[0x0b]	729	1			T24	3		T4	2		T9	3
valid_sources[0x0c]	791	1			T3	1		T4	2		T9	6
valid_sources[0x0d]	849	1			T1	15		T4	2		T9	2
valid_sources[0x0e]	1388	1			T1	57		T4	5		T9	3
valid_sources[0x0f]	662	1			T4	1		T27	6		T9	3
valid_sources[0x10]	2186	1			T6	2		T4	1		T9	8
valid_sources[0x11]	714	1			T6	4		T3	6		T4	4
valid_sources[0x12]	825	1			T6	2		T4	6		T9	4
valid_sources[0x13]	2491	1			T6	1		T4	4		T9	4
valid_sources[0x14]	812	1			T6	1		T24	6		T4	2
valid_sources[0x15]	820	1			T24	3		T4	3		T9	3
valid_sources[0x16]	868	1			T2	3		T4	5		T9	3
valid_sources[0x17]	1014	1			T5	12		T4	4		T9	2
valid_sources[0x18]	790	1			T3	3		T4	4		T9	1
valid_sources[0x19]	909	1			T4	3		T27	11		T9	7
valid_sources[0x1a]	800	1			T5	9		T2	30		T4	3
valid_sources[0x1b]	1426	1			T1	202		T4	3		T9	2
valid_sources[0x1c]	823	1			T2	9		T4	2		T9	3
valid_sources[0x1d]	744	1			T4	2		T9	6		T53	3
valid_sources[0x1e]	761	1			T3	4		T4	6		T9	8
valid_sources[0x1f]	1506	1			T25	1		T4	4		T9	7
valid_sources[0x20]	753	1			T4	4		T9	2		T10	15
valid_sources[0x21]	759	1			T9	3		T10	15		T53	1
valid_sources[0x22]	821	1			T4	4		T9	1		T10	55
valid_sources[0x23]	1080	1			T1	270		T24	3		T26	2
valid_sources[0x24]	867	1			T6	2		T4	5		T9	2
valid_sources[0x25]	1045	1			T5	8		T1	123		T3	2
valid_sources[0x26]	887	1			T4	2		T9	1		T53	4
valid_sources[0x27]	794	1			T4	2		T9	2		T10	32
valid_sources[0x28]	729	1			T6	6		T53	1		T11	7
valid_sources[0x29]	785	1			T3	2		T4	3		T9	6
valid_sources[0x2a]	768	1			T4	3		T9	1		T10	3
valid_sources[0x2b]	923	1			T1	84		T24	4		T4	4
valid_sources[0x2c]	828	1			T5	57		T4	6		T9	5
valid_sources[0x2d]	894	1			T1	20		T3	3		T4	2
valid_sources[0x2e]	924	1			T2	3		T3	2		T4	1
valid_sources[0x2f]	736	1			T2	11		T4	2		T9	1
valid_sources[0x30]	921	1			T24	31		T3	1		T4	5
valid_sources[0x31]	1574	1			T5	8		T4	1		T9	6
valid_sources[0x32]	837	1			T24	1		T4	1		T9	5
valid_sources[0x33]	1012	1			T4	3		T9	6		T53	4
valid_sources[0x34]	720	1			T1	20		T3	1		T4	1
valid_sources[0x35]	730	1			T2	29		T4	4		T9	3
valid_sources[0x36]	1975	1			T39	10		T24	3		T4	6
valid_sources[0x37]	803	1			T2	7		T3	2		T4	2
valid_sources[0x38]	874	1			T2	8		T3	2		T4	1
valid_sources[0x39]	883	1			T6	1		T2	20		T4	4
valid_sources[0x3a]	748	1			T3	1		T4	3		T9	10
valid_sources[0x3b]	1099	1			T1	61		T24	7		T4	3
valid_sources[0x3c]	826	1			T3	2		T4	6		T9	5
valid_sources[0x3d]	893	1			T1	21		T4	1		T9	3
valid_sources[0x3e]	691	1			T24	2		T3	2		T4	6
valid_sources[0x3f]	832	1			T5	21		T24	1		T2	6
valid_sources[0x40]	1706	1			T4	2		T9	1		T53	4
valid_sources[0x41]	1280	1			T2	26		T4	5		T53	11
valid_sources[0x42]	1180	1			T3	2		T9	2		T53	7
valid_sources[0x43]	765	1			T4	4		T9	7		T53	6
valid_sources[0x44]	821	1			T1	58		T4	2		T9	3
valid_sources[0x45]	744	1			T4	2		T9	3		T53	5
valid_sources[0x46]	931	1			T1	70		T4	2		T9	7
valid_sources[0x47]	669	1			T4	1		T9	2		T53	7
valid_sources[0x48]	792	1			T4	4		T9	2		T53	8
valid_sources[0x49]	933	1			T6	1		T4	1		T9	11
valid_sources[0x4a]	738	1			T3	6		T4	6		T9	6
valid_sources[0x4b]	2891	1			T24	6		T2	18		T3	1
valid_sources[0x4c]	847	1			T3	6		T4	7		T9	8
valid_sources[0x4d]	850	1			T4	4		T9	7		T53	5
valid_sources[0x4e]	843	1			T1	31		T2	10		T4	1
valid_sources[0x4f]	763	1			T25	11		T4	2		T9	5
valid_sources[0x50]	791	1			T4	8		T9	8		T53	1
valid_sources[0x51]	1490	1			T6	4		T3	2		T4	4
valid_sources[0x52]	761	1			T6	1		T4	4		T9	2
valid_sources[0x53]	856	1			T4	2		T9	6		T53	6
valid_sources[0x54]	940	1			T24	4		T4	4		T9	3
valid_sources[0x55]	718	1			T24	1		T4	2		T53	8
valid_sources[0x56]	652	1			T2	5		T4	2		T9	2
valid_sources[0x57]	1125	1			T4	3		T9	4		T10	6
valid_sources[0x58]	800	1			T24	17		T4	3		T9	4
valid_sources[0x59]	713	1			T3	4		T4	2		T9	3
valid_sources[0x5a]	1444	1			T4	3		T9	3		T53	2
valid_sources[0x5b]	836	1			T4	1		T9	5		T10	7
valid_sources[0x5c]	833	1			T4	2		T9	3		T53	9
valid_sources[0x5d]	871	1			T24	7		T4	6		T53	3
valid_sources[0x5e]	792	1			T24	3		T3	3		T4	2
valid_sources[0x5f]	679	1			T4	3		T9	3		T10	5
valid_sources[0x60]	804	1			T4	1		T9	1		T53	3
valid_sources[0x61]	849	1			T24	15		T4	3		T9	8
valid_sources[0x62]	2298	1			T24	7		T26	1		T4	7
valid_sources[0x63]	1471	1			T5	27		T4	1		T9	6
valid_sources[0x64]	864	1			T6	2		T3	4		T4	2
valid_sources[0x65]	982	1			T2	12		T4	3		T9	6
valid_sources[0x66]	822	1			T3	1		T4	2		T27	4
valid_sources[0x67]	862	1			T3	11		T4	4		T9	3
valid_sources[0x68]	688	1			T3	2		T4	5		T9	6
valid_sources[0x69]	793	1			T24	2		T2	5		T4	5
valid_sources[0x6a]	951	1			T4	3		T9	3		T53	5
valid_sources[0x6b]	728	1			T5	1		T24	7		T4	1
valid_sources[0x6c]	785	1			T6	1		T2	1		T4	2
valid_sources[0x6d]	855	1			T4	4		T9	5		T53	4
valid_sources[0x6e]	962	1			T6	1		T4	3		T9	5
valid_sources[0x6f]	1641	1			T4	2		T9	3		T53	8
valid_sources[0x70]	994	1			T6	3		T24	10		T25	3
valid_sources[0x71]	1121	1			T24	5		T2	9		T4	4
valid_sources[0x72]	783	1			T6	1		T3	1		T4	2
valid_sources[0x73]	805	1			T4	6		T9	6		T53	10
valid_sources[0x74]	1754	1			T4	3		T9	6		T53	9
valid_sources[0x75]	1122	1			T3	1		T4	5		T9	1
valid_sources[0x76]	750	1			T5	3		T4	2		T9	8
valid_sources[0x77]	715	1			T6	1		T24	3		T4	5
valid_sources[0x78]	833	1			T3	7		T4	2		T9	8
valid_sources[0x79]	819	1			T4	1		T9	2		T53	6
valid_sources[0x7a]	1693	1			T4	6		T9	4		T53	8
valid_sources[0x7b]	1487	1			T3	1		T4	4		T9	4
valid_sources[0x7c]	905	1			T2	16		T9	6		T53	7
valid_sources[0x7d]	988	1			T3	4		T4	1		T9	2
valid_sources[0x7e]	916	1			T4	4		T9	3		T53	5
valid_sources[0x7f]	797	1			T4	4		T9	2		T10	28
valid_sources[0x80]	787	1			T24	10		T4	6		T9	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

58312

1

T5

72

T6

12

T7

4

values[0x0]

all_enables

biggest_size

30326

1

T5

109

T6

3

T7

1

values[0x1]

all_enables

biggest_size

21220

1

T5

103

T6

3

T7

3