Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1147135699	10280	0	0
auto_block_debounce_ctl_rd_A	1147135699	1375	0	0
auto_block_out_ctl_rd_A	1147135699	1925	0	0
com_det_ctl_0_rd_A	1147135699	3426	0	0
com_det_ctl_1_rd_A	1147135699	3761	0	0
com_det_ctl_2_rd_A	1147135699	3745	0	0
com_det_ctl_3_rd_A	1147135699	3813	0	0
com_out_ctl_0_rd_A	1147135699	4124	0	0
com_out_ctl_1_rd_A	1147135699	4099	0	0
com_out_ctl_2_rd_A	1147135699	4120	0	0
com_out_ctl_3_rd_A	1147135699	4263	0	0
com_pre_det_ctl_0_rd_A	1147135699	1095	0	0
com_pre_det_ctl_1_rd_A	1147135699	1122	0	0
com_pre_det_ctl_2_rd_A	1147135699	1023	0	0
com_pre_det_ctl_3_rd_A	1147135699	1053	0	0
com_pre_sel_ctl_0_rd_A	1147135699	4278	0	0
com_pre_sel_ctl_1_rd_A	1147135699	4239	0	0
com_pre_sel_ctl_2_rd_A	1147135699	4326	0	0
com_pre_sel_ctl_3_rd_A	1147135699	4262	0	0
com_sel_ctl_0_rd_A	1147135699	4312	0	0
com_sel_ctl_1_rd_A	1147135699	4150	0	0
com_sel_ctl_2_rd_A	1147135699	4275	0	0
com_sel_ctl_3_rd_A	1147135699	4372	0	0
ec_rst_ctl_rd_A	1147135699	2120	0	0
intr_enable_rd_A	1147135699	1905	0	0
key_intr_ctl_rd_A	1147135699	2531	0	0
key_intr_debounce_ctl_rd_A	1147135699	1065	0	0
key_invert_ctl_rd_A	1147135699	3761	0	0
pin_allowed_ctl_rd_A	1147135699	4547	0	0
pin_out_ctl_rd_A	1147135699	3498	0	0
pin_out_value_rd_A	1147135699	3560	0	0
regwen_rd_A	1147135699	1858	0	0
ulp_ac_debounce_ctl_rd_A	1147135699	1203	0	0
ulp_ctl_rd_A	1147135699	1342	0	0
ulp_lid_debounce_ctl_rd_A	1147135699	1255	0	0
ulp_pwrb_debounce_ctl_rd_A	1147135699	1257	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	10280	0	0
T1	538055	6	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	260	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	3	0	0
T10	0	4	0	0
T11	0	6	0	0
T12	0	2	0	0
T24	51519	684	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T33	0	3	0	0
T35	0	6	0	0
T39	30863	0	0	0
T301	0	448	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	1375	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	4	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	15	0	0
T13	0	4	0	0
T24	51519	0	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T35	0	33	0	0
T39	30863	0	0	0
T73	0	8	0	0
T74	0	39	0	0
T75	0	81	0	0
T307	0	106	0	0
T312	0	2	0	0
T313	0	14	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	1925	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	7	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	76	0	0
T13	0	24	0	0
T24	51519	0	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T35	0	124	0	0
T39	30863	0	0	0
T73	0	29	0	0
T74	0	26	0	0
T75	0	53	0	0
T307	0	243	0	0
T313	0	26	0	0
T314	0	1	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	3426	0	0
T9	115966	28	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	6	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	10	0	0
T53	139081	0	0	0
T73	0	7	0	0
T74	0	18	0	0
T75	0	33	0	0
T301	20574	0	0	0
T307	0	88	0	0
T313	0	35	0	0
T314	0	2	0	0
T315	0	12	0	0
T316	15034	0	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	3761	0	0
T9	115966	4	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	1	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	27	0	0
T53	139081	0	0	0
T73	0	19	0	0
T74	0	21	0	0
T75	0	14	0	0
T301	20574	0	0	0
T307	0	76	0	0
T313	0	2	0	0
T314	0	2	0	0
T315	0	9	0	0
T316	15034	0	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	3745	0	0
T9	115966	24	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	10	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	46	0	0
T53	139081	0	0	0
T73	0	38	0	0
T74	0	25	0	0
T75	0	42	0	0
T301	20574	0	0	0
T307	0	67	0	0
T312	0	12	0	0
T313	0	3	0	0
T314	0	2	0	0
T316	15034	0	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	3813	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	4	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	20	0	0
T13	0	2	0	0
T24	51519	0	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T35	0	43	0	0
T39	30863	0	0	0
T73	0	13	0	0
T74	0	20	0	0
T75	0	26	0	0
T307	0	76	0	0
T312	0	1	0	0
T313	0	37	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	4124	0	0
T9	115966	38	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T35	208716	107	0	0
T53	139081	0	0	0
T73	0	10	0	0
T74	0	15	0	0
T75	0	70	0	0
T301	20574	0	0	0
T307	424439	188	0	0
T312	0	17	0	0
T313	0	20	0	0
T314	0	9	0	0
T315	0	5	0	0
T316	15034	0	0	0
T317	199503	0	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	4099	0	0
T9	115966	37	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	7	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	84	0	0
T53	139081	0	0	0
T73	0	26	0	0
T74	0	30	0	0
T75	0	4	0	0
T301	20574	0	0	0
T307	0	163	0	0
T312	0	8	0	0
T313	0	25	0	0
T316	15034	0	0	0
T318	0	2	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	4120	0	0
T9	115966	47	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	13	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	92	0	0
T53	139081	0	0	0
T73	0	31	0	0
T74	0	21	0	0
T75	0	42	0	0
T301	20574	0	0	0
T307	0	195	0	0
T312	0	13	0	0
T313	0	19	0	0
T316	15034	0	0	0
T318	0	1	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	4263	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	4	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	34	0	0
T13	0	25	0	0
T24	51519	0	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T35	0	93	0	0
T39	30863	0	0	0
T73	0	12	0	0
T74	0	58	0	0
T75	0	38	0	0
T307	0	182	0	0
T312	0	34	0	0
T313	0	6	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	1095	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	9	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	27	0	0
T13	0	7	0	0
T24	51519	0	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T35	0	47	0	0
T39	30863	0	0	0
T73	0	41	0	0
T74	0	7	0	0
T75	0	35	0	0
T307	0	70	0	0
T312	0	6	0	0
T313	0	6	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	1122	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	4	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	27	0	0
T24	51519	0	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T35	0	37	0	0
T39	30863	0	0	0
T73	0	25	0	0
T74	0	16	0	0
T75	0	24	0	0
T307	0	74	0	0
T312	0	3	0	0
T314	0	3	0	0
T315	0	2	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	1023	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	8	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	4	0	0
T24	51519	0	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T35	0	22	0	0
T39	30863	0	0	0
T73	0	16	0	0
T74	0	5	0	0
T75	0	14	0	0
T307	0	90	0	0
T312	0	10	0	0
T313	0	22	0	0
T314	0	7	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	1053	0	0
T9	115966	36	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	8	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	26	0	0
T53	139081	0	0	0
T73	0	40	0	0
T74	0	26	0	0
T75	0	47	0	0
T301	20574	0	0	0
T307	0	73	0	0
T313	0	13	0	0
T314	0	1	0	0
T315	0	7	0	0
T316	15034	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	4278	0	0
T9	115966	19	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	3	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	128	0	0
T53	139081	0	0	0
T73	0	26	0	0
T74	0	11	0	0
T75	0	46	0	0
T301	20574	0	0	0
T307	0	241	0	0
T312	0	14	0	0
T313	0	15	0	0
T314	0	3	0	0
T316	15034	0	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	4239	0	0
T9	115966	58	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	20	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	171	0	0
T53	139081	0	0	0
T73	0	19	0	0
T74	0	30	0	0
T75	0	38	0	0
T301	20574	0	0	0
T307	0	178	0	0
T312	0	12	0	0
T313	0	24	0	0
T315	0	13	0	0
T316	15034	0	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	4326	0	0
T9	115966	62	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	2	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	122	0	0
T53	139081	0	0	0
T73	0	18	0	0
T74	0	20	0	0
T75	0	39	0	0
T301	20574	0	0	0
T307	0	176	0	0
T312	0	8	0	0
T313	0	13	0	0
T316	15034	0	0	0
T318	0	8	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	4262	0	0
T9	115966	60	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	17	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	139	0	0
T53	139081	0	0	0
T73	0	8	0	0
T74	0	13	0	0
T75	0	20	0	0
T301	20574	0	0	0
T307	0	253	0	0
T312	0	7	0	0
T313	0	46	0	0
T316	15034	0	0	0
T318	0	6	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	4312	0	0
T9	115966	53	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	10	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	122	0	0
T53	139081	0	0	0
T73	0	43	0	0
T74	0	12	0	0
T75	0	34	0	0
T301	20574	0	0	0
T307	0	208	0	0
T312	0	22	0	0
T313	0	32	0	0
T314	0	4	0	0
T316	15034	0	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	4150	0	0
T9	115966	85	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	34	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	127	0	0
T53	139081	0	0	0
T73	0	7	0	0
T74	0	40	0	0
T75	0	19	0	0
T301	20574	0	0	0
T307	0	208	0	0
T312	0	9	0	0
T313	0	28	0	0
T314	0	7	0	0
T316	15034	0	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	4275	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	8	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	54	0	0
T13	0	24	0	0
T24	51519	0	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T35	0	118	0	0
T39	30863	0	0	0
T73	0	18	0	0
T74	0	14	0	0
T75	0	42	0	0
T307	0	273	0	0
T312	0	7	0	0
T313	0	50	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	4372	0	0
T9	115966	45	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	35	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	176	0	0
T53	139081	0	0	0
T73	0	17	0	0
T74	0	15	0	0
T75	0	33	0	0
T301	20574	0	0	0
T307	0	255	0	0
T312	0	2	0	0
T313	0	36	0	0
T314	0	4	0	0
T316	15034	0	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	2120	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	6	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	17	0	0
T13	0	7	0	0
T24	51519	0	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T35	0	64	0	0
T39	30863	0	0	0
T73	0	44	0	0
T74	0	56	0	0
T75	0	59	0	0
T307	0	67	0	0
T312	0	10	0	0
T313	0	20	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	1905	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	8	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	18	0	0
T13	0	5	0	0
T24	51519	0	0	0
T25	195401	14	0	0
T26	100910	0	0	0
T35	0	39	0	0
T39	30863	0	0	0
T73	0	22	0	0
T74	0	11	0	0
T307	0	74	0	0
T312	0	1	0	0
T319	0	14	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	2531	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	8	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	124	0	0
T13	0	2	0	0
T24	51519	0	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T35	0	220	0	0
T39	30863	0	0	0
T73	0	4	0	0
T74	0	12	0	0
T75	0	24	0	0
T307	0	463	0	0
T312	0	56	0	0
T313	0	29	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	1065	0	0
T9	115966	10	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	8	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	48	0	0
T53	139081	0	0	0
T73	0	1	0	0
T74	0	29	0	0
T75	0	44	0	0
T301	20574	0	0	0
T307	0	51	0	0
T312	0	9	0	0
T313	0	17	0	0
T314	0	3	0	0
T316	15034	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	3761	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	9	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	71	0	0
T13	0	29	0	0
T24	51519	0	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T35	0	219	0	0
T39	30863	0	0	0
T73	0	36	0	0
T74	0	39	0	0
T75	0	15	0	0
T307	0	572	0	0
T312	0	41	0	0
T313	0	9	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	4547	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	2	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	132	0	0
T13	0	9	0	0
T24	51519	0	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T35	0	274	0	0
T39	30863	0	0	0
T73	0	37	0	0
T74	0	8	0	0
T75	0	53	0	0
T307	0	378	0	0
T312	0	52	0	0
T313	0	13	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	3498	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	2	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	29	0	0
T13	0	6	0	0
T24	51519	0	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T35	0	194	0	0
T39	30863	0	0	0
T73	0	22	0	0
T74	0	8	0	0
T75	0	69	0	0
T307	0	304	0	0
T312	0	30	0	0
T313	0	21	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	3560	0	0
T9	115966	60	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	36	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	211	0	0
T53	139081	0	0	0
T73	0	14	0	0
T74	0	20	0	0
T75	0	74	0	0
T301	20574	0	0	0
T307	0	294	0	0
T312	0	9	0	0
T313	0	17	0	0
T315	0	3	0	0
T316	15034	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	1858	0	0
T9	115966	23	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	6	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	44	0	0
T53	139081	0	0	0
T73	0	6	0	0
T74	0	33	0	0
T75	0	109	0	0
T301	20574	0	0	0
T307	0	74	0	0
T313	0	13	0	0
T314	0	5	0	0
T316	15034	0	0	0
T318	0	149	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	1203	0	0
T1	538055	0	0	0
T2	44866	0	0	0
T3	101277	0	0	0
T5	56447	11	0	0
T6	50958	0	0	0
T7	198999	0	0	0
T9	0	25	0	0
T13	0	2	0	0
T24	51519	0	0	0
T25	195401	0	0	0
T26	100910	0	0	0
T35	0	13	0	0
T39	30863	0	0	0
T73	0	24	0	0
T74	0	18	0	0
T75	0	38	0	0
T307	0	69	0	0
T312	0	5	0	0
T313	0	29	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	1342	0	0
T9	115966	32	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	7	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	56	0	0
T53	139081	0	0	0
T73	0	15	0	0
T74	0	11	0	0
T75	0	30	0	0
T301	20574	0	0	0
T307	0	49	0	0
T312	0	4	0	0
T314	0	3	0	0
T315	0	14	0	0
T316	15034	0	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	1255	0	0
T9	115966	22	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	9	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	20	0	0
T53	139081	0	0	0
T73	0	32	0	0
T74	0	13	0	0
T75	0	54	0	0
T301	20574	0	0	0
T307	0	74	0	0
T313	0	23	0	0
T314	0	4	0	0
T316	15034	0	0	0
T318	0	4	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147135699	1257	0	0
T9	115966	18	0	0
T10	556591	0	0	0
T11	639363	0	0	0
T12	210529	0	0	0
T13	43650	4	0	0
T33	538025	0	0	0
T34	118843	0	0	0
T35	0	60	0	0
T53	139081	0	0	0
T73	0	14	0	0
T74	0	18	0	0
T75	0	66	0	0
T301	20574	0	0	0
T307	0	63	0	0
T312	0	5	0	0
T313	0	21	0	0
T316	15034	0	0	0
T318	0	17	0	0