Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T14,T26
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T14,T26
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T36,T16,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T36,T16,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T36,T16,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T36,T16,T29
1	0	Covered	T36,T14,T26
1	1	Covered	T36,T16,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T16,T29
0	1	Covered	T29,T70,T59
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T16,T29
0	1	Covered	T36,T16,T29
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T16,T29
1	-	Covered	T36,T16,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T16,T29
0	1	Covered	T36,T16,T29
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T16,T29
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T16,T29
IdleSt	0	-	-	-	-	-	-	Covered	T36,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T16,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T45,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T16,T29
DetectSt	-	-	-	-	1	-	-	Covered	T29,T70,T59
DetectSt	-	-	-	-	0	1	-	Covered	T36,T16,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T16,T29
StableSt	-	-	-	-	-	-	0	Covered	T36,T16,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	284	0	0
CntIncr_A	7942109	276576	0	0
CntNoWrap_A	7942109	7276799	0	0
DetectStDropOut_A	7942109	3	0	0
DetectedOut_A	7942109	805	0	0
DetectedPulseOut_A	7942109	125	0	0
DisabledIdleSt_A	7942109	6993896	0	0
DisabledNoDetection_A	7942109	6996121	0	0
EnterDebounceSt_A	7942109	157	0	0
EnterDetectSt_A	7942109	128	0	0
EnterStableSt_A	7942109	125	0	0
PulseIsPulse_A	7942109	125	0	0
StayInStableSt	7942109	680	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7942109	6908	0	0
gen_low_level_sva.LowLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	125	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	284	0	0
T13	499	0	0	0
T14	195034	0	0	0
T15	35944	0	0	0
T16	261725	3	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	4	0	0
T30	402	0	0	0
T36	742	2	0	0
T45	0	3	0	0
T55	0	4	0	0
T78	0	2	0	0
T80	0	6	0	0
T81	0	2	0	0
T82	0	2	0	0
T83	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	276576	0	0
T13	499	0	0	0
T14	195034	0	0	0
T15	35944	0	0	0
T16	261725	125	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	141	0	0
T30	402	0	0	0
T36	742	46	0	0
T45	0	193	0	0
T55	0	34579	0	0
T78	0	6365	0	0
T80	0	111	0	0
T81	0	49	0	0
T82	0	16	0	0
T83	0	171	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276799	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254619	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	310	0	0
T30	402	1	0	0
T36	742	339	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	3	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	12806	0	0	0
T29	715	1	0	0
T30	402	0	0	0
T31	488	0	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	1	0	0
T62	503	0	0	0
T70	0	1	0	0
T78	35761	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	805	0	0
T13	499	0	0	0
T14	195034	0	0	0
T15	35944	0	0	0
T16	261725	6	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	9	0	0
T30	402	0	0	0
T36	742	3	0	0
T45	0	10	0	0
T55	0	8	0	0
T78	0	4	0	0
T80	0	13	0	0
T81	0	11	0	0
T82	0	5	0	0
T83	0	6	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	125	0	0
T13	499	0	0	0
T14	195034	0	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	1	0	0
T30	402	0	0	0
T36	742	1	0	0
T45	0	1	0	0
T55	0	2	0	0
T78	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6993896	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254412	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	98	0	0
T30	402	1	0	0
T36	742	265	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6996121	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254433	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	98	0	0
T30	402	2	0	0
T36	742	265	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	157	0	0
T13	499	0	0	0
T14	195034	0	0	0
T15	35944	0	0	0
T16	261725	2	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	2	0	0
T30	402	0	0	0
T36	742	1	0	0
T45	0	2	0	0
T55	0	2	0	0
T78	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	128	0	0
T13	499	0	0	0
T14	195034	0	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	2	0	0
T30	402	0	0	0
T36	742	1	0	0
T45	0	1	0	0
T55	0	2	0	0
T78	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	125	0	0
T13	499	0	0	0
T14	195034	0	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	1	0	0
T30	402	0	0	0
T36	742	1	0	0
T45	0	1	0	0
T55	0	2	0	0
T78	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	125	0	0
T13	499	0	0	0
T14	195034	0	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	1	0	0
T30	402	0	0	0
T36	742	1	0	0
T45	0	1	0	0
T55	0	2	0	0
T78	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	680	0	0
T13	499	0	0	0
T14	195034	0	0	0
T15	35944	0	0	0
T16	261725	5	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	8	0	0
T30	402	0	0	0
T36	742	2	0	0
T45	0	9	0	0
T55	0	6	0	0
T78	0	3	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	0	4	0	0
T83	0	4	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6908	0	0
T13	499	0	0	0
T14	195034	3	0	0
T15	35944	8	0	0
T16	261725	44	0	0
T17	0	1	0	0
T26	421	3	0	0
T27	5633	27	0	0
T28	437	1	0	0
T29	715	3	0	0
T30	402	0	0	0
T31	0	9	0	0
T36	742	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	125	0	0
T13	499	0	0	0
T14	195034	0	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	1	0	0
T30	402	0	0	0
T36	742	1	0	0
T45	0	1	0	0
T55	0	2	0	0
T78	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T14,T26
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T14,T26
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T14,T16,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T37
1	0	Covered	T36,T26,T15
1	1	Covered	T14,T16,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T37
0	1	Covered	T45,T75,T76
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T37
0	1	Unreachable
1	0	Covered	T14,T16,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T16,T37
0	1	Covered	T14,T16,T37
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T37
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T16,T37
IdleSt	0	-	-	-	-	-	-	Covered	T36,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T16,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T75,T114,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T16,T37
DetectSt	-	-	-	-	1	-	-	Covered	T45,T75,T76
DetectSt	-	-	-	-	0	1	-	Covered	T14,T16,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T16,T37
StableSt	-	-	-	-	-	-	0	Covered	T14,T16,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	151	0	0
CntIncr_A	7942109	106205	0	0
CntNoWrap_A	7942109	7276932	0	0
DetectStDropOut_A	7942109	13	0	0
DetectedOut_A	7942109	469783	0	0
DetectedPulseOut_A	7942109	55	0	0
DisabledIdleSt_A	7942109	6393888	0	0
DisabledNoDetection_A	7942109	6396174	0	0
EnterDebounceSt_A	7942109	83	0	0
EnterDetectSt_A	7942109	68	0	0
EnterStableSt_A	7942109	55	0	0
PulseIsPulse_A	7942109	55	0	0
StayInStableSt	7942109	469728	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7942109	6908	0	0
gen_low_level_sva.LowLevelEvent_A	7942109	7279371	0	0
gen_sticky_sva.StableStDropOut_A	7942109	304831	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	151	0	0
T14	195034	2	0	0
T15	35944	0	0	0
T16	261725	2	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	4	0	0
T45	0	8	0	0
T47	0	2	0	0
T54	726	0	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	4	0	0
T59	0	2	0	0
T60	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	106205	0	0
T14	195034	48	0	0
T15	35944	0	0	0
T16	261725	65	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	58	0	0
T45	0	256	0	0
T47	0	51	0	0
T54	726	0	0	0
T56	0	87	0	0
T57	0	62554	0	0
T58	0	156	0	0
T59	0	72	0	0
T60	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276932	0	0
T13	499	98	0	0
T14	195034	194631	0	0
T15	35944	35446	0	0
T16	261725	254620	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	13	0	0
T45	24990	4	0	0
T46	482	0	0	0
T75	0	3	0	0
T76	0	1	0	0
T77	726	0	0	0
T99	583	0	0	0
T100	2172	0	0	0
T101	522	0	0	0
T114	0	1	0	0
T115	0	2	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	550	0	0	0
T119	402	0	0	0
T120	425	0	0	0
T121	527	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	469783	0	0
T14	195034	215	0	0
T15	35944	0	0	0
T16	261725	225	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	180	0	0
T54	726	0	0	0
T56	0	367	0	0
T57	0	205136	0	0
T58	0	61	0	0
T59	0	360	0	0
T60	0	13	0	0
T61	0	330	0	0
T111	0	308	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	55	0	0
T14	195034	1	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	2	0	0
T54	726	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T111	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6393888	0	0
T13	499	98	0	0
T14	195034	21	0	0
T15	35944	35446	0	0
T16	261725	254240	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6396174	0	0
T13	499	99	0	0
T14	195034	22	0	0
T15	35944	35461	0	0
T16	261725	254261	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	83	0	0
T14	195034	1	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	2	0	0
T45	0	4	0	0
T47	0	2	0	0
T54	726	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	68	0	0
T14	195034	1	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	2	0	0
T45	0	4	0	0
T54	726	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	55	0	0
T14	195034	1	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	2	0	0
T54	726	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T111	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	55	0	0
T14	195034	1	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	2	0	0
T54	726	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T111	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	469728	0	0
T14	195034	214	0	0
T15	35944	0	0	0
T16	261725	224	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	178	0	0
T54	726	0	0	0
T56	0	366	0	0
T57	0	205135	0	0
T58	0	59	0	0
T59	0	359	0	0
T60	0	12	0	0
T61	0	329	0	0
T111	0	307	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6908	0	0
T13	499	0	0	0
T14	195034	3	0	0
T15	35944	8	0	0
T16	261725	44	0	0
T17	0	1	0	0
T26	421	3	0	0
T27	5633	27	0	0
T28	437	1	0	0
T29	715	3	0	0
T30	402	0	0	0
T31	0	9	0	0
T36	742	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	304831	0	0
T14	195034	194331	0	0
T15	35944	0	0	0
T16	261725	84	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	556	0	0
T54	726	0	0	0
T56	0	188	0	0
T57	0	88	0	0
T58	0	71	0	0
T59	0	84	0	0
T60	0	153	0	0
T61	0	298	0	0
T111	0	343	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T26,T16

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T13,T14
1	0	Covered	T14,T26,T16
1	1	Covered	T14,T26,T16

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T14,T16,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T37
1	0	Covered	T26,T16,T28
1	1	Covered	T14,T16,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T45
0	1	Covered	T14,T56,T61
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T45
0	1	Unreachable
1	0	Covered	T14,T16,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T16,T37
0	1	Covered	T14,T16,T37
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T45
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T16,T37
IdleSt	0	-	-	-	-	-	-	Covered	T14,T26,T16
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T16,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T37,T58,T61
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T16,T37
DetectSt	-	-	-	-	1	-	-	Covered	T14,T56,T61
DetectSt	-	-	-	-	0	1	-	Covered	T14,T16,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T16,T45
StableSt	-	-	-	-	-	-	0	Covered	T14,T16,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	175	0	0
CntIncr_A	7942109	40830	0	0
CntNoWrap_A	7942109	7276908	0	0
DetectStDropOut_A	7942109	20	0	0
DetectedOut_A	7942109	33702	0	0
DetectedPulseOut_A	7942109	44	0	0
DisabledIdleSt_A	7942109	6393888	0	0
DisabledNoDetection_A	7942109	6396174	0	0
EnterDebounceSt_A	7942109	111	0	0
EnterDetectSt_A	7942109	64	0	0
EnterStableSt_A	7942109	44	0	0
PulseIsPulse_A	7942109	44	0	0
StayInStableSt	7942109	33658	0	0
gen_high_level_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_sticky_sva.StableStDropOut_A	7942109	633062	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	175	0	0
T14	195034	6	0	0
T15	35944	0	0	0
T16	261725	2	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	6	0	0
T45	0	2	0	0
T47	0	2	0	0
T54	726	0	0	0
T56	0	4	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	2	0	0
T60	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	40830	0	0
T14	195034	282	0	0
T15	35944	0	0	0
T16	261725	37	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	372	0	0
T45	0	34	0	0
T47	0	52	0	0
T54	726	0	0	0
T56	0	174	0	0
T57	0	13	0	0
T58	0	86	0	0
T59	0	27	0	0
T60	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276908	0	0
T13	499	98	0	0
T14	195034	194627	0	0
T15	35944	35446	0	0
T16	261725	254620	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	20	0	0
T14	195034	2	0	0
T15	35944	0	0	0
T16	261725	0	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T54	726	0	0	0
T56	0	1	0	0
T61	0	4	0	0
T73	0	1	0	0
T111	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	33702	0	0
T14	195034	1	0	0
T15	35944	0	0	0
T16	261725	124	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T45	0	123	0	0
T54	726	0	0	0
T56	0	265	0	0
T57	0	67	0	0
T59	0	171	0	0
T60	0	41	0	0
T111	0	72	0	0
T112	0	27146	0	0
T113	0	362	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	44	0	0
T14	195034	1	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T45	0	1	0	0
T54	726	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6393888	0	0
T13	499	98	0	0
T14	195034	21	0	0
T15	35944	35446	0	0
T16	261725	254240	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6396174	0	0
T13	499	99	0	0
T14	195034	22	0	0
T15	35944	35461	0	0
T16	261725	254261	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	111	0	0
T14	195034	3	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	6	0	0
T45	0	1	0	0
T47	0	2	0	0
T54	726	0	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	64	0	0
T14	195034	3	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T45	0	1	0	0
T54	726	0	0	0
T56	0	2	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	4	0	0
T111	0	2	0	0
T112	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	44	0	0
T14	195034	1	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T45	0	1	0	0
T54	726	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	44	0	0
T14	195034	1	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T45	0	1	0	0
T54	726	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	33658	0	0
T16	261725	123	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T45	0	122	0	0
T54	726	0	0	0
T55	35116	0	0	0
T56	0	264	0	0
T57	0	66	0	0
T59	0	170	0	0
T60	0	40	0	0
T111	0	71	0	0
T112	0	27145	0	0
T113	0	361	0	0
T127	0	1222	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	633062	0	0
T14	195034	64782	0	0
T15	35944	0	0	0
T16	261725	202	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T45	0	180	0	0
T54	726	0	0	0
T56	0	165	0	0
T57	0	267694	0	0
T59	0	326	0	0
T60	0	72	0	0
T111	0	466	0	0
T112	0	27	0	0
T113	0	223	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T26,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T14,T16,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T37
1	0	Covered	T26,T15,T16
1	1	Covered	T14,T16,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T37
0	1	Covered	T16,T59,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T37
0	1	Unreachable
1	0	Covered	T14,T16,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T16,T37
0	1	Covered	T14,T16,T37
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T37
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T16,T37
IdleSt	0	-	-	-	-	-	-	Covered	T14,T26,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T16,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T59,T128
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T16,T37
DetectSt	-	-	-	-	1	-	-	Covered	T16,T59,T73
DetectSt	-	-	-	-	0	1	-	Covered	T14,T16,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T16,T37
StableSt	-	-	-	-	-	-	0	Covered	T14,T16,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	146	0	0
CntIncr_A	7942109	43263	0	0
CntNoWrap_A	7942109	7276937	0	0
DetectStDropOut_A	7942109	6	0	0
DetectedOut_A	7942109	206666	0	0
DetectedPulseOut_A	7942109	49	0	0
DisabledIdleSt_A	7942109	6393888	0	0
DisabledNoDetection_A	7942109	6396174	0	0
EnterDebounceSt_A	7942109	91	0	0
EnterDetectSt_A	7942109	55	0	0
EnterStableSt_A	7942109	49	0	0
PulseIsPulse_A	7942109	49	0	0
StayInStableSt	7942109	206617	0	0
gen_high_event_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_high_level_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_sticky_sva.StableStDropOut_A	7942109	629987	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	146	0	0
T14	195034	2	0	0
T15	35944	0	0	0
T16	261725	4	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	4	0	0
T45	0	2	0	0
T47	0	2	0	0
T54	726	0	0	0
T56	0	5	0	0
T57	0	2	0	0
T58	0	4	0	0
T59	0	7	0	0
T60	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	43263	0	0
T14	195034	32745	0	0
T15	35944	0	0	0
T16	261725	80	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	98	0	0
T45	0	11	0	0
T47	0	52	0	0
T54	726	0	0	0
T56	0	140	0	0
T57	0	70	0	0
T58	0	180	0	0
T59	0	340	0	0
T60	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276937	0	0
T13	499	98	0	0
T14	195034	194631	0	0
T15	35944	35446	0	0
T16	261725	254618	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6	0	0
T16	261725	1	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	3	0	0
T73	0	1	0	0
T96	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	206666	0	0
T14	195034	161824	0	0
T15	35944	0	0	0
T16	261725	44	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	429	0	0
T45	0	67	0	0
T54	726	0	0	0
T57	0	344	0	0
T58	0	52	0	0
T60	0	79	0	0
T61	0	571	0	0
T111	0	584	0	0
T112	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	49	0	0
T14	195034	1	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	2	0	0
T45	0	1	0	0
T54	726	0	0	0
T57	0	1	0	0
T58	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6393888	0	0
T13	499	98	0	0
T14	195034	21	0	0
T15	35944	35446	0	0
T16	261725	254240	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6396174	0	0
T13	499	99	0	0
T14	195034	22	0	0
T15	35944	35461	0	0
T16	261725	254261	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	91	0	0
T14	195034	1	0	0
T15	35944	0	0	0
T16	261725	2	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	2	0	0
T45	0	1	0	0
T47	0	2	0	0
T54	726	0	0	0
T56	0	5	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	4	0	0
T60	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	55	0	0
T14	195034	1	0	0
T15	35944	0	0	0
T16	261725	2	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	2	0	0
T45	0	1	0	0
T54	726	0	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	3	0	0
T60	0	1	0	0
T61	0	1	0	0
T111	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	49	0	0
T14	195034	1	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	2	0	0
T45	0	1	0	0
T54	726	0	0	0
T57	0	1	0	0
T58	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	49	0	0
T14	195034	1	0	0
T15	35944	0	0	0
T16	261725	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	2	0	0
T45	0	1	0	0
T54	726	0	0	0
T57	0	1	0	0
T58	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	206617	0	0
T14	195034	161823	0	0
T15	35944	0	0	0
T16	261725	43	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	427	0	0
T45	0	66	0	0
T54	726	0	0	0
T57	0	343	0	0
T58	0	50	0	0
T60	0	78	0	0
T61	0	570	0	0
T111	0	583	0	0
T112	0	8	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	629987	0	0
T14	195034	37	0	0
T15	35944	0	0	0
T16	261725	186	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T37	0	293	0	0
T45	0	270	0	0
T54	726	0	0	0
T57	0	267370	0	0
T58	0	76	0	0
T60	0	25	0	0
T61	0	60	0	0
T111	0	55	0	0
T112	0	61896	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T13,T14
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T16,T43,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T16,T43,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T16,T43,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T45
1	0	Covered	T36,T13,T14
1	1	Covered	T16,T43,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T43,T42
0	1	Covered	T61
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T43,T42
0	1	Covered	T16,T42,T129
1	0	Covered	T47,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T43,T42
1	-	Covered	T16,T42,T129

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T43,T42
0	1	Covered	T16,T43,T42
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T43,T42
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T43,T42
IdleSt	0	-	-	-	-	-	-	Covered	T36,T13,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T43,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T130,T131,T132
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T43,T42
DetectSt	-	-	-	-	1	-	-	Covered	T61
DetectSt	-	-	-	-	0	1	-	Covered	T16,T43,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T42,T47
StableSt	-	-	-	-	-	-	0	Covered	T16,T43,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	87	0	0
CntIncr_A	7942109	89385	0	0
CntNoWrap_A	7942109	7276996	0	0
DetectStDropOut_A	7942109	1	0	0
DetectedOut_A	7942109	14622	0	0
DetectedPulseOut_A	7942109	41	0	0
DisabledIdleSt_A	7942109	6788124	0	0
DisabledNoDetection_A	7942109	6790350	0	0
EnterDebounceSt_A	7942109	46	0	0
EnterDetectSt_A	7942109	42	0	0
EnterStableSt_A	7942109	41	0	0
PulseIsPulse_A	7942109	41	0	0
StayInStableSt	7942109	14559	0	0
gen_high_level_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	87	0	0
T16	261725	2	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T47	0	2	0	0
T54	726	0	0	0
T55	35116	0	0	0
T61	0	2	0	0
T74	0	2	0	0
T129	0	4	0	0
T130	0	1	0	0
T133	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	89385	0	0
T16	261725	30	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	65	0	0
T42	0	55	0	0
T43	0	67	0	0
T47	0	36	0	0
T54	726	0	0	0
T55	35116	0	0	0
T61	0	47	0	0
T74	0	48	0	0
T129	0	36	0	0
T130	0	66	0	0
T133	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276996	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254620	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	1	0	0
T61	6041	1	0	0
T134	409	0	0	0
T135	439	0	0	0
T136	31897	0	0	0
T137	9664	0	0	0
T138	8661	0	0	0
T139	527	0	0	0
T140	2098	0	0	0
T141	504	0	0	0
T142	14097	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	14622	0	0
T16	261725	86	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	114	0	0
T42	0	39	0	0
T43	0	55	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T74	0	39	0	0
T112	0	525	0	0
T129	0	52	0	0
T133	0	104	0	0
T143	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	41	0	0
T16	261725	1	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T74	0	1	0	0
T112	0	1	0	0
T129	0	2	0	0
T133	0	1	0	0
T143	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6788124	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254401	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6790350	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254421	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	46	0	0
T16	261725	1	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T61	0	1	0	0
T74	0	1	0	0
T129	0	2	0	0
T130	0	1	0	0
T133	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	42	0	0
T16	261725	1	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T61	0	1	0	0
T74	0	1	0	0
T112	0	1	0	0
T129	0	2	0	0
T133	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	41	0	0
T16	261725	1	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T74	0	1	0	0
T112	0	1	0	0
T129	0	2	0	0
T133	0	1	0	0
T143	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	41	0	0
T16	261725	1	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T74	0	1	0	0
T112	0	1	0	0
T129	0	2	0	0
T133	0	1	0	0
T143	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	14559	0	0
T16	261725	85	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	112	0	0
T42	0	38	0	0
T43	0	53	0	0
T54	726	0	0	0
T55	35116	0	0	0
T74	0	37	0	0
T112	0	523	0	0
T129	0	49	0	0
T133	0	102	0	0
T143	0	42	0	0
T144	0	79	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	17	0	0
T16	261725	1	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T42	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T73	0	1	0	0
T92	0	2	0	0
T129	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T13,T14
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T16,T17,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T16,T17,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T16,T17,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T46
1	0	Covered	T26,T15,T16
1	1	Covered	T16,T17,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T46
0	1	Covered	T16,T149
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T46
0	1	Covered	T42,T41,T130
1	0	Covered	T47,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T17,T46
1	-	Covered	T42,T41,T130

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T17,T46
0	1	Covered	T16,T17,T46
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T46
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T17,T46
IdleSt	0	-	-	-	-	-	-	Covered	T36,T13,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T17,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T61,T150,T151
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T17,T46
DetectSt	-	-	-	-	1	-	-	Covered	T16,T149
DetectSt	-	-	-	-	0	1	-	Covered	T16,T17,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T41,T130
StableSt	-	-	-	-	-	-	0	Covered	T16,T17,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	137	0	0
CntIncr_A	7942109	16838	0	0
CntNoWrap_A	7942109	7276946	0	0
DetectStDropOut_A	7942109	2	0	0
DetectedOut_A	7942109	9323	0	0
DetectedPulseOut_A	7942109	65	0	0
DisabledIdleSt_A	7942109	7180142	0	0
DisabledNoDetection_A	7942109	7182374	0	0
EnterDebounceSt_A	7942109	70	0	0
EnterDetectSt_A	7942109	67	0	0
EnterStableSt_A	7942109	65	0	0
PulseIsPulse_A	7942109	65	0	0
StayInStableSt	7942109	9230	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7942109	2738	0	0
gen_low_level_sva.LowLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	137	0	0
T16	261725	4	0	0
T17	569	2	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	2	0	0
T42	0	4	0	0
T46	0	2	0	0
T47	0	2	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	6	0	0
T61	0	5	0	0
T130	0	4	0	0
T133	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	16838	0	0
T16	261725	60	0	0
T17	569	16	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	65	0	0
T42	0	110	0	0
T46	0	15	0	0
T47	0	36	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	219	0	0
T61	0	186	0	0
T130	0	132	0	0
T133	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276946	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254618	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	2	0	0
T16	261725	1	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T54	726	0	0	0
T55	35116	0	0	0
T149	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	9323	0	0
T16	261725	37	0	0
T17	569	144	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	158	0	0
T42	0	212	0	0
T46	0	41	0	0
T47	0	2	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	127	0	0
T61	0	336	0	0
T130	0	133	0	0
T133	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	65	0	0
T16	261725	1	0	0
T17	569	1	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	3	0	0
T61	0	2	0	0
T130	0	2	0	0
T133	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7180142	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254202	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7182374	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254221	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	70	0	0
T16	261725	2	0	0
T17	569	1	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	3	0	0
T61	0	3	0	0
T130	0	2	0	0
T133	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	67	0	0
T16	261725	2	0	0
T17	569	1	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	3	0	0
T61	0	2	0	0
T130	0	2	0	0
T133	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	65	0	0
T16	261725	1	0	0
T17	569	1	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	3	0	0
T61	0	2	0	0
T130	0	2	0	0
T133	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	65	0	0
T16	261725	1	0	0
T17	569	1	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	3	0	0
T61	0	2	0	0
T130	0	2	0	0
T133	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	9230	0	0
T16	261725	35	0	0
T17	569	142	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	157	0	0
T42	0	209	0	0
T46	0	39	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	123	0	0
T61	0	333	0	0
T130	0	130	0	0
T133	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	2738	0	0
T15	35944	0	0	0
T16	261725	40	0	0
T17	569	1	0	0
T18	0	1	0	0
T26	421	5	0	0
T27	5633	0	0	0
T28	437	2	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	3	0	0
T54	726	0	0	0
T62	0	6	0	0
T105	0	8	0	0
T108	0	2	0	0
T109	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	35	0	0
T41	812	1	0	0
T42	12850	1	0	0
T44	580	0	0	0
T59	0	2	0	0
T61	0	1	0	0
T71	8599	0	0	0
T85	5566	0	0	0
T112	0	1	0	0
T129	0	2	0	0
T130	0	1	0	0
T133	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	440	0	0	0
T155	16283	0	0	0
T156	526	0	0	0
T157	528	0	0	0
T158	502	0	0	0