Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	88.34	89.13	90.48		83.33	85.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	89.69	91.30	90.48		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	89.77	91.30	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	89.77	91.30	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
88.34	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.77	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.77	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
89.69	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T15,T16
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T13,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T13,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T13,T15,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T15,T16,T27
1	1	Covered	T13,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T16
0	1	Covered	T52,T66,T67
1	0	Covered	T47,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T16
0	1	Covered	T13,T15,T16
1	0	Covered	T38,T47,T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T15,T16
1	-	Covered	T13,T15,T16

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
88.34	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.77	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.77	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T13,T14
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T36,T16,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T36,T16,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T36,T16,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T36,T16,T29
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T16,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T16,T29
0	1	Covered	T16,T29,T70
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T16,T29
0	1	Covered	T36,T16,T29
1	0	Covered	T47,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T16,T29
1	-	Covered	T36,T16,T29

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T19,T20
1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T19,T20
1	0	Covered	T19,T20,T21
1	1	Covered	T27,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T19,T20
0	1	Covered	T27,T19,T21
1	0	Covered	T19,T20,T21

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
1	0	Covered	T71,T47,T72

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T21
1	-	Covered	T19,T20,T21

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T26,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T37
1	0	Covered	T26,T15,T16
1	1	Covered	T14,T16,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T37
0	1	Covered	T16,T59,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T37
0	1	Unreachable
1	0	Covered	T14,T16,T37

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
89.69	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T13,T14
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T16,T17,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T16,T17,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T16,T17,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T36,T13,T14
1	1	Covered	T16,T17,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T40
0	1	Covered	T46,T74,T61
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T40
0	1	Covered	T16,T40,T45
1	0	Covered	T47,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T18,T40
1	-	Covered	T16,T40,T45

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T26,T16

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T13,T14
1	0	Covered	T14,T26,T16
1	1	Covered	T14,T26,T16

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T37
1	0	Covered	T26,T16,T28
1	1	Covered	T14,T16,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T45
0	1	Covered	T14,T56,T61
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T45
0	1	Unreachable
1	0	Covered	T14,T16,T45

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T14,T26
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T14,T26
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T14,T16,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T16,T37
1	0	Covered	T36,T26,T15
1	1	Covered	T14,T16,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T37
0	1	Covered	T45,T75,T76
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T37
0	1	Unreachable
1	0	Covered	T14,T16,T37

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
88.34	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.77	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.77	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
89.69	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T36,T16,T29
0	1	Covered	T36,T16,T29
0	0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T16,T29
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T36,T16,T29
IdleSt	0	-	-	-	-	-	-	Covered	T36,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T16,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T45,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T16,T29
DetectSt	-	-	-	-	1	-	-	Covered	T14,T16,T29
DetectSt	-	-	-	-	0	1	-	Covered	T36,T16,T29
DetectSt	-	-	-	-	0	0	-	Covered	T13,T15,T16
StableSt	-	-	-	-	-	-	1	Covered	T36,T16,T29
StableSt	-	-	-	-	-	-	0	Covered	T36,T16,T29
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T16,T27
0	1	Covered	T14,T16,T27
0	0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T27
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T16,T27
IdleSt	0	-	-	-	-	-	-	Covered	T14,T26,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T16,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T47,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T16,T27
DetectSt	-	-	-	-	1	-	-	Covered	T16,T27,T19
DetectSt	-	-	-	-	0	1	-	Covered	T14,T16,T19
DetectSt	-	-	-	-	0	0	-	Covered	T27,T19,T20
StableSt	-	-	-	-	-	-	1	Covered	T14,T16,T19
StableSt	-	-	-	-	-	-	0	Covered	T14,T16,T19
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	206494834	17701	0	0
CntIncr_A	206494834	2199440	0	0
CntNoWrap_A	206494834	189186457	0	0
DetectStDropOut_A	206494834	2099	0	0
DetectedOut_A	206494834	1700684	0	0
DetectedPulseOut_A	206494834	5607	0	0
DisabledIdleSt_A	206494834	177633716	0	0
DisabledNoDetection_A	206494834	177689208	0	0
EnterDebounceSt_A	206494834	9101	0	0
EnterDetectSt_A	206494834	8618	0	0
EnterStableSt_A	206494834	5607	0	0
PulseIsPulse_A	206494834	5607	0	0
StayInStableSt	206494834	1694298	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	71478981	52243	0	0
gen_high_event_sva.HighLevelEvent_A	39710545	36396855	0	0
gen_high_level_sva.HighLevelEvent_A	135015853	123749307	0	0
gen_low_level_sva.LowLevelEvent_A	71478981	65514339	0	0
gen_not_sticky_sva.StableStDropOut_A	182668507	4593	0	0
gen_sticky_sva.StableStDropOut_A	23826327	1567880	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206494834	17701	0	0
T13	998	2	0	0
T14	390068	0	0	0
T15	179720	6	0	0
T16	2093800	5	0	0
T17	5690	0	0	0
T18	4858	0	0	0
T19	0	56	0	0
T20	0	4	0	0
T22	0	2	0	0
T26	842	0	0	0
T27	67596	28	0	0
T28	5244	0	0	0
T29	8580	4	0	0
T30	4824	0	0	0
T31	5368	0	0	0
T36	742	2	0	0
T38	0	38	0	0
T39	0	8	0	0
T40	691	0	0	0
T45	0	3	0	0
T49	16946	0	0	0
T52	0	2	0	0
T54	7260	0	0	0
T55	351160	4	0	0
T62	2012	0	0	0
T66	0	6	0	0
T67	30384	0	0	0
T78	0	2	0	0
T79	0	3	0	0
T80	0	6	0	0
T81	16055	2	0	0
T82	0	2	0	0
T83	0	4	0	0
T84	656	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206494834	2199440	0	0
T13	998	25	0	0
T14	390068	0	0	0
T15	179720	366	0	0
T16	2093800	150	0	0
T17	5690	0	0	0
T18	4858	0	0	0
T19	0	1679	0	0
T20	0	120	0	0
T22	0	137	0	0
T26	842	0	0	0
T27	67596	832	0	0
T28	5244	0	0	0
T29	8580	141	0	0
T30	4824	0	0	0
T31	5368	0	0	0
T36	742	46	0	0
T38	0	1268	0	0
T39	0	456	0	0
T40	691	0	0	0
T45	0	193	0	0
T49	16946	0	0	0
T52	0	101	0	0
T54	7260	0	0	0
T55	351160	34579	0	0
T62	2012	0	0	0
T66	0	291	0	0
T67	30384	0	0	0
T78	0	6365	0	0
T79	0	41	0	0
T80	0	111	0	0
T81	16055	49	0	0
T82	0	16	0	0
T83	0	171	0	0
T84	656	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206494834	189186457	0	0
T13	12974	2546	0	0
T14	5070884	5060448	0	0
T15	934544	921547	0	0
T16	6804850	6620139	0	0
T26	10946	520	0	0
T27	146458	135930	0	0
T28	11362	936	0	0
T29	18590	8160	0	0
T30	10452	26	0	0
T36	19292	8864	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206494834	2099	0	0
T17	1138	0	0	0
T18	1388	0	0	0
T19	12806	0	0	0
T21	0	10	0	0
T27	5633	14	0	0
T29	1430	1	0	0
T30	804	0	0	0
T31	976	0	0	0
T38	16606	0	0	0
T39	19085	0	0	0
T45	24990	1	0	0
T47	0	1	0	0
T52	11456	1	0	0
T53	17932	0	0	0
T54	1452	0	0	0
T55	70232	0	0	0
T59	0	1	0	0
T62	1006	0	0	0
T70	0	1	0	0
T77	726	0	0	0
T78	35761	0	0	0
T85	0	25	0	0
T86	0	5	0	0
T87	0	14	0	0
T88	0	5	0	0
T89	0	4	0	0
T90	0	3	0	0
T91	0	25	0	0
T92	0	8	0	0
T93	0	7	0	0
T94	0	6	0	0
T95	0	8	0	0
T96	0	1	0	0
T97	0	3	0	0
T98	528	0	0	0
T99	583	0	0	0
T100	2172	0	0	0
T101	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206494834	1700684	0	0
T13	998	3	0	0
T14	390068	0	0	0
T15	71888	217	0	0
T16	523450	9	0	0
T19	12806	2854	0	0
T20	14286	22	0	0
T22	0	20	0	0
T26	842	0	0	0
T27	11266	0	0	0
T28	874	0	0	0
T29	1430	9	0	0
T30	804	0	0	0
T31	488	0	0	0
T36	742	3	0	0
T38	0	1335	0	0
T39	0	230	0	0
T45	0	10	0	0
T50	0	433	0	0
T55	0	8	0	0
T66	0	21	0	0
T67	0	834	0	0
T78	35761	4	0	0
T80	0	13	0	0
T81	0	11	0	0
T82	0	5	0	0
T83	0	6	0	0
T102	0	1216	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206494834	5607	0	0
T13	998	1	0	0
T14	390068	0	0	0
T15	71888	3	0	0
T16	523450	2	0	0
T19	12806	28	0	0
T20	14286	2	0	0
T22	0	1	0	0
T26	842	0	0	0
T27	11266	0	0	0
T28	874	0	0	0
T29	1430	1	0	0
T30	804	0	0	0
T31	488	0	0	0
T36	742	1	0	0
T38	0	19	0	0
T39	0	4	0	0
T45	0	1	0	0
T50	0	17	0	0
T55	0	2	0	0
T66	0	3	0	0
T67	0	11	0	0
T78	35761	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T102	0	16	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206494834	177633716	0	0
T13	12974	2454	0	0
T14	5070884	4476622	0	0
T15	934544	900680	0	0
T16	6804850	6614783	0	0
T26	10946	520	0	0
T27	146458	123164	0	0
T28	11362	936	0	0
T29	18590	7948	0	0
T30	10452	26	0	0
T36	19292	8790	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206494834	177689208	0	0
T13	12974	2479	0	0
T14	5070884	4476648	0	0
T15	934544	901010	0	0
T16	6804850	6615307	0	0
T26	10946	546	0	0
T27	146458	123186	0	0
T28	11362	962	0	0
T29	18590	7973	0	0
T30	10452	52	0	0
T36	19292	8815	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206494834	9101	0	0
T13	998	1	0	0
T14	390068	0	0	0
T15	179720	3	0	0
T16	2093800	3	0	0
T17	5690	0	0	0
T18	4858	0	0	0
T19	0	28	0	0
T20	0	2	0	0
T22	0	1	0	0
T26	842	0	0	0
T27	67596	14	0	0
T28	5244	0	0	0
T29	8580	2	0	0
T30	4824	0	0	0
T31	5368	0	0	0
T36	742	1	0	0
T38	0	19	0	0
T39	0	4	0	0
T40	691	0	0	0
T45	0	2	0	0
T49	16946	0	0	0
T52	0	1	0	0
T54	7260	0	0	0
T55	351160	2	0	0
T62	2012	0	0	0
T66	0	3	0	0
T67	30384	0	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	0	3	0	0
T81	16055	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	656	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206494834	8618	0	0
T13	998	1	0	0
T14	390068	0	0	0
T15	179720	3	0	0
T16	2093800	2	0	0
T17	5690	0	0	0
T18	4858	0	0	0
T19	0	28	0	0
T20	0	2	0	0
T22	0	1	0	0
T26	842	0	0	0
T27	67596	14	0	0
T28	5244	0	0	0
T29	8580	2	0	0
T30	4824	0	0	0
T31	5368	0	0	0
T36	742	1	0	0
T38	0	19	0	0
T39	0	4	0	0
T40	691	0	0	0
T45	0	1	0	0
T49	16946	0	0	0
T52	0	1	0	0
T54	7260	0	0	0
T55	351160	2	0	0
T62	2012	0	0	0
T66	0	3	0	0
T67	30384	11	0	0
T78	0	1	0	0
T80	0	3	0	0
T81	16055	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T84	656	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206494834	5607	0	0
T13	998	1	0	0
T14	390068	0	0	0
T15	71888	3	0	0
T16	523450	2	0	0
T19	12806	28	0	0
T20	14286	2	0	0
T22	0	1	0	0
T26	842	0	0	0
T27	11266	0	0	0
T28	874	0	0	0
T29	1430	1	0	0
T30	804	0	0	0
T31	488	0	0	0
T36	742	1	0	0
T38	0	19	0	0
T39	0	4	0	0
T45	0	1	0	0
T50	0	17	0	0
T55	0	2	0	0
T66	0	3	0	0
T67	0	11	0	0
T78	35761	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T102	0	16	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206494834	5607	0	0
T13	998	1	0	0
T14	390068	0	0	0
T15	71888	3	0	0
T16	523450	2	0	0
T19	12806	28	0	0
T20	14286	2	0	0
T22	0	1	0	0
T26	842	0	0	0
T27	11266	0	0	0
T28	874	0	0	0
T29	1430	1	0	0
T30	804	0	0	0
T31	488	0	0	0
T36	742	1	0	0
T38	0	19	0	0
T39	0	4	0	0
T45	0	1	0	0
T50	0	17	0	0
T55	0	2	0	0
T66	0	3	0	0
T67	0	11	0	0
T78	35761	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T102	0	16	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	206494834	1694298	0	0
T13	998	2	0	0
T14	390068	0	0	0
T15	71888	214	0	0
T16	523450	7	0	0
T19	12806	2824	0	0
T20	14286	20	0	0
T22	0	19	0	0
T26	842	0	0	0
T27	11266	0	0	0
T28	874	0	0	0
T29	1430	8	0	0
T30	804	0	0	0
T31	488	0	0	0
T36	742	2	0	0
T38	0	1315	0	0
T39	0	226	0	0
T45	0	9	0	0
T50	0	416	0	0
T55	0	6	0	0
T66	0	18	0	0
T67	0	823	0	0
T78	35761	3	0	0
T80	0	10	0	0
T81	0	10	0	0
T82	0	4	0	0
T83	0	4	0	0
T102	0	1200	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71478981	52243	0	0
T13	2994	1	0	0
T14	1365238	6	0	0
T15	323496	30	0	0
T16	2355525	198	0	0
T17	1138	3	0	0
T18	0	2	0	0
T19	0	59	0	0
T20	0	24	0	0
T26	3789	13	0	0
T27	50697	76	0	0
T28	3933	8	0	0
T29	6435	3	0	0
T30	3618	0	0	0
T31	2928	31	0	0
T36	2226	3	0	0
T54	2178	4	0	0
T62	0	26	0	0
T104	0	3	0	0
T105	0	20	0	0
T108	0	2	0	0
T109	0	10	0	0
T110	0	5	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39710545	36396855	0	0
T13	2495	495	0	0
T14	975170	973170	0	0
T15	179720	177305	0	0
T16	1308625	1273215	0	0
T26	2105	105	0	0
T27	28165	26165	0	0
T28	2185	185	0	0
T29	3575	1575	0	0
T30	2010	10	0	0
T36	3710	1710	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135015853	123749307	0	0
T13	8483	1683	0	0
T14	3315578	3308778	0	0
T15	611048	602837	0	0
T16	4449325	4328931	0	0
T26	7157	357	0	0
T27	95761	88961	0	0
T28	7429	629	0	0
T29	12155	5355	0	0
T30	6834	34	0	0
T36	12614	5814	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71478981	65514339	0	0
T13	4491	891	0	0
T14	1755306	1751706	0	0
T15	323496	319149	0	0
T16	2355525	2291787	0	0
T26	3789	189	0	0
T27	50697	47097	0	0
T28	3933	333	0	0
T29	6435	2835	0	0
T30	3618	18	0	0
T36	6678	3078	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182668507	4593	0	0
T13	998	1	0	0
T14	390068	0	0	0
T15	71888	3	0	0
T16	523450	2	0	0
T19	12806	26	0	0
T20	14286	2	0	0
T22	0	1	0	0
T26	842	0	0	0
T27	11266	0	0	0
T28	874	0	0	0
T29	1430	1	0	0
T30	804	0	0	0
T31	488	0	0	0
T36	742	1	0	0
T38	0	17	0	0
T39	0	4	0	0
T45	0	1	0	0
T50	0	17	0	0
T55	0	2	0	0
T66	0	3	0	0
T67	0	11	0	0
T78	35761	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T102	0	16	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23826327	1567880	0	0
T14	585102	259150	0	0
T15	107832	0	0	0
T16	785175	472	0	0
T26	1263	0	0	0
T27	16899	0	0	0
T28	1311	0	0	0
T29	2145	0	0	0
T30	1206	0	0	0
T31	1464	0	0	0
T37	0	849	0	0
T45	0	450	0	0
T54	2178	0	0	0
T56	0	353	0	0
T57	0	535152	0	0
T58	0	147	0	0
T59	0	410	0	0
T60	0	250	0	0
T61	0	358	0	0
T111	0	864	0	0
T112	0	61923	0	0
T113	0	223	0	0