Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T13,T26,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T13,T14
1	0	Covered	T13,T26,T15
1	1	Covered	T13,T26,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T16,T17,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T16,T17,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T16,T17,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T46
1	0	Covered	T13,T26,T15
1	1	Covered	T16,T17,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T47
0	1	Covered	T46,T74,T175
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T47
0	1	Covered	T17,T48,T59
1	0	Covered	T47,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T17,T47
1	-	Covered	T17,T48,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T17,T46
0	1	Covered	T16,T17,T46
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T46
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T17,T46
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T15
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T17,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T145,T202,T203
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T17,T46
DetectSt	-	-	-	-	1	-	-	Covered	T46,T74,T175
DetectSt	-	-	-	-	0	1	-	Covered	T16,T17,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T47,T48
StableSt	-	-	-	-	-	-	0	Covered	T16,T17,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	169	0	0
CntIncr_A	7942109	193450	0	0
CntNoWrap_A	7942109	7276914	0	0
DetectStDropOut_A	7942109	4	0	0
DetectedOut_A	7942109	67504	0	0
DetectedPulseOut_A	7942109	79	0	0
DisabledIdleSt_A	7942109	6763558	0	0
DisabledNoDetection_A	7942109	6765782	0	0
EnterDebounceSt_A	7942109	87	0	0
EnterDetectSt_A	7942109	83	0	0
EnterStableSt_A	7942109	79	0	0
PulseIsPulse_A	7942109	79	0	0
StayInStableSt	7942109	67393	0	0
gen_high_level_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	45	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	169	0	0
T16	261725	2	0	0
T17	569	2	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	4	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	4	0	0
T74	0	2	0	0
T112	0	2	0	0
T129	0	4	0	0
T133	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	193450	0	0
T16	261725	225	0	0
T17	569	16	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T46	0	15	0	0
T47	0	36	0	0
T48	0	58	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	146	0	0
T74	0	48	0	0
T112	0	72	0	0
T129	0	36	0	0
T133	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276914	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254620	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	4	0	0
T42	12850	0	0	0
T43	645	0	0	0
T44	580	0	0	0
T46	482	1	0	0
T48	765	0	0	0
T74	9103	1	0	0
T120	425	0	0	0
T121	527	0	0	0
T175	0	2	0	0
T204	11818	0	0	0
T205	447	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	67504	0	0
T16	261725	154	0	0
T17	569	7	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T47	0	2	0	0
T48	0	227	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	310	0	0
T112	0	410	0	0
T129	0	87	0	0
T133	0	131	0	0
T152	0	282	0	0
T198	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	79	0	0
T16	261725	1	0	0
T17	569	1	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T47	0	1	0	0
T48	0	2	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	2	0	0
T112	0	1	0	0
T129	0	2	0	0
T133	0	3	0	0
T152	0	1	0	0
T198	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6763558	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254202	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6765782	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254221	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	87	0	0
T16	261725	2	0	0
T17	569	1	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	2	0	0
T74	0	1	0	0
T112	0	1	0	0
T129	0	2	0	0
T133	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	83	0	0
T16	261725	1	0	0
T17	569	1	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	2	0	0
T74	0	1	0	0
T112	0	1	0	0
T129	0	2	0	0
T133	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	79	0	0
T16	261725	1	0	0
T17	569	1	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T47	0	1	0	0
T48	0	2	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	2	0	0
T112	0	1	0	0
T129	0	2	0	0
T133	0	3	0	0
T152	0	1	0	0
T198	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	79	0	0
T16	261725	1	0	0
T17	569	1	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T47	0	1	0	0
T48	0	2	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	2	0	0
T112	0	1	0	0
T129	0	2	0	0
T133	0	3	0	0
T152	0	1	0	0
T198	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	67393	0	0
T16	261725	152	0	0
T17	569	6	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T47	0	1	0	0
T48	0	224	0	0
T54	726	0	0	0
T55	35116	0	0	0
T59	0	307	0	0
T112	0	409	0	0
T129	0	85	0	0
T133	0	127	0	0
T152	0	281	0	0
T198	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	45	0	0
T17	569	1	0	0
T18	694	0	0	0
T19	12806	0	0	0
T48	765	1	0	0
T55	35116	0	0	0
T59	0	1	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	1	0	0
T129	0	2	0	0
T133	0	2	0	0
T144	0	1	0	0
T152	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T206	16461	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T26,T15
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T26,T15
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T17,T43,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T17,T43,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T17,T43,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T13,T26,T15
1	1	Covered	T17,T43,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T43,T44
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T43,T44
0	1	Covered	T44,T159,T59
1	0	Covered	T47,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T43,T44
1	-	Covered	T44,T159,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T43,T44
0	1	Covered	T17,T43,T44
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T43,T44
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T43,T44
IdleSt	0	-	-	-	-	-	-	Covered	T36,T13,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T43,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T128
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T43,T44
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T17,T43,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T47,T159
StableSt	-	-	-	-	-	-	0	Covered	T17,T43,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	103	0	0
CntIncr_A	7942109	110511	0	0
CntNoWrap_A	7942109	7276980	0	0
DetectStDropOut_A	7942109	0	0	0
DetectedOut_A	7942109	48558	0	0
DetectedPulseOut_A	7942109	51	0	0
DisabledIdleSt_A	7942109	6578494	0	0
DisabledNoDetection_A	7942109	6580719	0	0
EnterDebounceSt_A	7942109	52	0	0
EnterDetectSt_A	7942109	51	0	0
EnterStableSt_A	7942109	51	0	0
PulseIsPulse_A	7942109	51	0	0
StayInStableSt	7942109	48478	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7942109	6351	0	0
gen_low_level_sva.LowLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	103	0	0
T17	569	2	0	0
T18	694	0	0	0
T19	12806	0	0	0
T42	12850	0	0	0
T43	645	2	0	0
T44	0	4	0	0
T47	0	2	0	0
T55	35116	0	0	0
T59	0	2	0	0
T61	0	2	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	2	0	0
T133	0	4	0	0
T159	0	2	0	0
T207	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	110511	0	0
T17	569	16	0	0
T18	694	0	0	0
T19	12806	0	0	0
T42	12850	0	0	0
T43	645	67	0	0
T44	0	48	0	0
T47	0	36	0	0
T55	35116	0	0	0
T59	0	73	0	0
T61	0	92	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	72	0	0
T133	0	64	0	0
T159	0	100	0	0
T207	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276980	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	48558	0	0
T17	569	44	0	0
T18	694	0	0	0
T19	12806	0	0	0
T42	12850	0	0	0
T43	645	56	0	0
T44	0	83	0	0
T47	0	2	0	0
T55	35116	0	0	0
T59	0	1	0	0
T61	0	540	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	42	0	0
T133	0	48	0	0
T159	0	40	0	0
T207	0	69	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	51	0	0
T17	569	1	0	0
T18	694	0	0	0
T19	12806	0	0	0
T42	12850	0	0	0
T43	645	1	0	0
T44	0	2	0	0
T47	0	1	0	0
T55	35116	0	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	1	0	0
T133	0	2	0	0
T159	0	1	0	0
T207	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6578494	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254423	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6580719	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254443	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	52	0	0
T17	569	1	0	0
T18	694	0	0	0
T19	12806	0	0	0
T42	12850	0	0	0
T43	645	1	0	0
T44	0	2	0	0
T47	0	1	0	0
T55	35116	0	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	1	0	0
T133	0	2	0	0
T159	0	1	0	0
T207	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	51	0	0
T17	569	1	0	0
T18	694	0	0	0
T19	12806	0	0	0
T42	12850	0	0	0
T43	645	1	0	0
T44	0	2	0	0
T47	0	1	0	0
T55	35116	0	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	1	0	0
T133	0	2	0	0
T159	0	1	0	0
T207	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	51	0	0
T17	569	1	0	0
T18	694	0	0	0
T19	12806	0	0	0
T42	12850	0	0	0
T43	645	1	0	0
T44	0	2	0	0
T47	0	1	0	0
T55	35116	0	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	1	0	0
T133	0	2	0	0
T159	0	1	0	0
T207	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	51	0	0
T17	569	1	0	0
T18	694	0	0	0
T19	12806	0	0	0
T42	12850	0	0	0
T43	645	1	0	0
T44	0	2	0	0
T47	0	1	0	0
T55	35116	0	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	1	0	0
T133	0	2	0	0
T159	0	1	0	0
T207	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	48478	0	0
T17	569	42	0	0
T18	694	0	0	0
T19	12806	0	0	0
T42	12850	0	0	0
T43	645	54	0	0
T44	0	80	0	0
T47	0	1	0	0
T55	35116	0	0	0
T61	0	538	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	40	0	0
T133	0	46	0	0
T144	0	38	0	0
T159	0	39	0	0
T207	0	67	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6351	0	0
T13	499	1	0	0
T14	195034	0	0	0
T15	35944	14	0	0
T16	261725	37	0	0
T17	0	1	0	0
T19	0	35	0	0
T26	421	1	0	0
T27	5633	24	0	0
T28	437	2	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	8	0	0
T62	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	20	0	0
T44	580	1	0	0
T59	7564	1	0	0
T88	20734	0	0	0
T133	0	2	0	0
T144	0	1	0	0
T145	0	1	0	0
T159	19415	1	0	0
T165	0	1	0	0
T175	0	1	0	0
T200	0	1	0	0
T208	0	1	0	0
T209	7875	0	0	0
T210	524	0	0	0
T211	422	0	0	0
T212	522	0	0	0
T213	56847	0	0	0
T214	7109	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T13,T26,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T13,T14
1	0	Covered	T13,T26,T15
1	1	Covered	T13,T26,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T18,T46,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T16,T18,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T18,T46,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T46
1	0	Covered	T13,T26,T15
1	1	Covered	T16,T18,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T46,T44
0	1	Covered	T164,T175
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T46,T44
0	1	Covered	T44,T130,T48
1	0	Covered	T47,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T46,T44
1	-	Covered	T44,T130,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T46,T44
0	1	Covered	T16,T18,T46
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T46,T44
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T46
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T15
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T46,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T165,T186
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T46
DetectSt	-	-	-	-	1	-	-	Covered	T164,T175
DetectSt	-	-	-	-	0	1	-	Covered	T18,T46,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T130,T47
StableSt	-	-	-	-	-	-	0	Covered	T18,T46,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	120	0	0
CntIncr_A	7942109	16269	0	0
CntNoWrap_A	7942109	7276963	0	0
DetectStDropOut_A	7942109	2	0	0
DetectedOut_A	7942109	14961	0	0
DetectedPulseOut_A	7942109	57	0	0
DisabledIdleSt_A	7942109	7089534	0	0
DisabledNoDetection_A	7942109	7091770	0	0
EnterDebounceSt_A	7942109	62	0	0
EnterDetectSt_A	7942109	59	0	0
EnterStableSt_A	7942109	57	0	0
PulseIsPulse_A	7942109	57	0	0
StayInStableSt	7942109	14880	0	0
gen_high_level_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	120	0	0
T18	694	2	0	0
T19	12806	0	0	0
T44	0	2	0	0
T46	482	2	0	0
T47	0	2	0	0
T48	0	6	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T120	425	0	0	0
T121	527	0	0	0
T130	0	2	0	0
T133	0	4	0	0
T159	0	4	0	0
T189	0	2	0	0
T204	11818	0	0	0
T207	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	16269	0	0
T16	261725	195	0	0
T17	569	0	0	0
T18	694	82	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T44	0	24	0	0
T46	0	15	0	0
T47	0	36	0	0
T48	0	87	0	0
T54	726	0	0	0
T55	35116	0	0	0
T130	0	66	0	0
T159	0	200	0	0
T189	0	64	0	0
T207	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276963	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	2	0	0
T164	47670	1	0	0
T165	2362	0	0	0
T175	0	1	0	0
T215	2319	0	0	0
T216	502	0	0	0
T217	689	0	0	0
T218	9110	0	0	0
T219	1020	0	0	0
T220	1020	0	0	0
T221	586	0	0	0
T222	488	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	14961	0	0
T18	694	45	0	0
T19	12806	0	0	0
T44	0	44	0	0
T46	482	41	0	0
T47	0	3	0	0
T48	0	124	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T120	425	0	0	0
T121	527	0	0	0
T130	0	258	0	0
T133	0	48	0	0
T159	0	189	0	0
T189	0	107	0	0
T204	11818	0	0	0
T207	0	119	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	57	0	0
T18	694	1	0	0
T19	12806	0	0	0
T44	0	1	0	0
T46	482	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T120	425	0	0	0
T121	527	0	0	0
T130	0	1	0	0
T133	0	2	0	0
T159	0	2	0	0
T189	0	1	0	0
T204	11818	0	0	0
T207	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7089534	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254423	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7091770	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254443	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	62	0	0
T16	261725	1	0	0
T17	569	0	0	0
T18	694	1	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T54	726	0	0	0
T55	35116	0	0	0
T130	0	1	0	0
T159	0	2	0	0
T189	0	1	0	0
T207	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	59	0	0
T18	694	1	0	0
T19	12806	0	0	0
T44	0	1	0	0
T46	482	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T120	425	0	0	0
T121	527	0	0	0
T130	0	1	0	0
T133	0	2	0	0
T159	0	2	0	0
T189	0	1	0	0
T204	11818	0	0	0
T207	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	57	0	0
T18	694	1	0	0
T19	12806	0	0	0
T44	0	1	0	0
T46	482	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T120	425	0	0	0
T121	527	0	0	0
T130	0	1	0	0
T133	0	2	0	0
T159	0	2	0	0
T189	0	1	0	0
T204	11818	0	0	0
T207	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	57	0	0
T18	694	1	0	0
T19	12806	0	0	0
T44	0	1	0	0
T46	482	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T120	425	0	0	0
T121	527	0	0	0
T130	0	1	0	0
T133	0	2	0	0
T159	0	2	0	0
T189	0	1	0	0
T204	11818	0	0	0
T207	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	14880	0	0
T18	694	43	0	0
T19	12806	0	0	0
T44	0	43	0	0
T46	482	39	0	0
T47	0	2	0	0
T48	0	120	0	0
T62	503	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T120	425	0	0	0
T121	527	0	0	0
T130	0	257	0	0
T133	0	46	0	0
T159	0	186	0	0
T189	0	105	0	0
T204	11818	0	0	0
T207	0	117	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	31	0	0
T44	580	1	0	0
T48	765	2	0	0
T56	1100	0	0	0
T70	756	0	0	0
T86	11892	0	0	0
T128	0	1	0	0
T130	938	1	0	0
T133	0	2	0	0
T159	0	1	0	0
T164	0	1	0	0
T186	0	1	0	0
T199	0	1	0	0
T206	16461	0	0	0
T215	0	1	0	0
T223	407	0	0	0
T224	492	0	0	0
T225	489	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T26,T15
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T26,T15
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T16,T42,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T16,T42,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T16,T42,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T43,T42
1	0	Covered	T13,T26,T15
1	1	Covered	T16,T42,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T42,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T42,T41
0	1	Covered	T41,T133,T61
1	0	Covered	T47,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T42,T41
1	-	Covered	T41,T133,T61

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T42,T41
0	1	Covered	T16,T42,T41
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T42,T41
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T42,T41
IdleSt	0	-	-	-	-	-	-	Covered	T36,T13,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T42,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T124
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T42,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T16,T42,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T47,T133
StableSt	-	-	-	-	-	-	0	Covered	T16,T42,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	79	0	0
CntIncr_A	7942109	133056	0	0
CntNoWrap_A	7942109	7277004	0	0
DetectStDropOut_A	7942109	0	0	0
DetectedOut_A	7942109	107411	0	0
DetectedPulseOut_A	7942109	39	0	0
DisabledIdleSt_A	7942109	6713572	0	0
DisabledNoDetection_A	7942109	6715810	0	0
EnterDebounceSt_A	7942109	41	0	0
EnterDetectSt_A	7942109	39	0	0
EnterStableSt_A	7942109	39	0	0
PulseIsPulse_A	7942109	39	0	0
StayInStableSt	7942109	107356	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7942109	6371	0	0
gen_low_level_sva.LowLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	79	0	0
T16	261725	2	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T47	0	2	0	0
T54	726	0	0	0
T55	35116	0	0	0
T61	0	4	0	0
T68	0	2	0	0
T133	0	4	0	0
T143	0	2	0	0
T144	0	2	0	0
T153	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	133056	0	0
T16	261725	11	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	65	0	0
T42	0	55	0	0
T47	0	36	0	0
T54	726	0	0	0
T55	35116	0	0	0
T61	0	94	0	0
T68	0	27	0	0
T133	0	64	0	0
T143	0	97	0	0
T144	0	45	0	0
T153	0	75	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7277004	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254620	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	107411	0	0
T16	261725	41	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	118	0	0
T42	0	43	0	0
T47	0	3	0	0
T54	726	0	0	0
T55	35116	0	0	0
T61	0	168	0	0
T68	0	12	0	0
T133	0	201	0	0
T143	0	45	0	0
T144	0	97	0	0
T153	0	50	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	39	0	0
T16	261725	1	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T61	0	2	0	0
T68	0	1	0	0
T133	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T153	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6713572	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254486	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6715810	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254506	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	41	0	0
T16	261725	1	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T61	0	2	0	0
T68	0	1	0	0
T133	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T153	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	39	0	0
T16	261725	1	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T61	0	2	0	0
T68	0	1	0	0
T133	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T153	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	39	0	0
T16	261725	1	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T61	0	2	0	0
T68	0	1	0	0
T133	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T153	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	39	0	0
T16	261725	1	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T61	0	2	0	0
T68	0	1	0	0
T133	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T153	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	107356	0	0
T16	261725	39	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T41	0	117	0	0
T42	0	41	0	0
T47	0	2	0	0
T54	726	0	0	0
T55	35116	0	0	0
T61	0	165	0	0
T68	0	11	0	0
T133	0	198	0	0
T143	0	43	0	0
T144	0	96	0	0
T153	0	48	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6371	0	0
T13	499	1	0	0
T14	195034	0	0	0
T15	35944	12	0	0
T16	261725	35	0	0
T17	0	2	0	0
T19	0	28	0	0
T26	421	1	0	0
T27	5633	26	0	0
T28	437	2	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	10	0	0
T62	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	21	0	0
T41	812	1	0	0
T56	1100	0	0	0
T61	0	1	0	0
T71	8599	0	0	0
T85	5566	0	0	0
T124	0	1	0	0
T130	938	0	0	0
T133	0	1	0	0
T144	0	1	0	0
T148	0	1	0	0
T154	440	0	0	0
T155	16283	0	0	0
T156	526	0	0	0
T157	528	0	0	0
T158	502	0	0	0
T164	0	1	0	0
T166	0	1	0	0
T168	0	1	0	0
T208	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T36,T14,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T13,T14
1	0	Covered	T36,T14,T26
1	1	Covered	T36,T14,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T16,T17,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T16,T17,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T16,T17,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T36,T14,T26
1	1	Covered	T16,T17,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T40
0	1	Covered	T61
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T40
0	1	Covered	T17,T40,T45
1	0	Covered	T47,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T17,T40
1	-	Covered	T17,T40,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T17,T40
0	1	Covered	T16,T17,T40
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T40
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T17,T40
IdleSt	0	-	-	-	-	-	-	Covered	T36,T14,T26
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T17,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T130,T145
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T17,T40
DetectSt	-	-	-	-	1	-	-	Covered	T61
DetectSt	-	-	-	-	0	1	-	Covered	T16,T17,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T40,T45
StableSt	-	-	-	-	-	-	0	Covered	T16,T17,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	130	0	0
CntIncr_A	7942109	61330	0	0
CntNoWrap_A	7942109	7276953	0	0
DetectStDropOut_A	7942109	1	0	0
DetectedOut_A	7942109	37050	0	0
DetectedPulseOut_A	7942109	61	0	0
DisabledIdleSt_A	7942109	6940467	0	0
DisabledNoDetection_A	7942109	6942692	0	0
EnterDebounceSt_A	7942109	70	0	0
EnterDetectSt_A	7942109	62	0	0
EnterStableSt_A	7942109	61	0	0
PulseIsPulse_A	7942109	61	0	0
StayInStableSt	7942109	36962	0	0
gen_high_level_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	130	0	0
T16	261725	2	0	0
T17	569	4	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T40	0	5	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	0	2	0	0
T54	726	0	0	0
T55	35116	0	0	0
T130	0	3	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	61330	0	0
T16	261725	206	0	0
T17	569	32	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T40	0	66	0	0
T41	0	65	0	0
T42	0	55	0	0
T45	0	92	0	0
T46	0	15	0	0
T47	0	36	0	0
T54	726	0	0	0
T55	35116	0	0	0
T130	0	132	0	0
T159	0	100	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276953	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254620	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	1	0	0
T61	6041	1	0	0
T134	409	0	0	0
T135	439	0	0	0
T136	31897	0	0	0
T137	9664	0	0	0
T138	8661	0	0	0
T139	527	0	0	0
T140	2098	0	0	0
T141	504	0	0	0
T142	14097	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	37050	0	0
T16	261725	108	0	0
T17	569	102	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T40	0	83	0	0
T41	0	50	0	0
T42	0	362	0	0
T45	0	84	0	0
T46	0	41	0	0
T47	0	2	0	0
T54	726	0	0	0
T55	35116	0	0	0
T130	0	30	0	0
T159	0	188	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	61	0	0
T16	261725	1	0	0
T17	569	2	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T130	0	1	0	0
T159	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6940467	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254287	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6942692	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254306	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	70	0	0
T16	261725	2	0	0
T17	569	2	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T130	0	2	0	0
T159	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	62	0	0
T16	261725	1	0	0
T17	569	2	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T130	0	1	0	0
T159	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	61	0	0
T16	261725	1	0	0
T17	569	2	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T130	0	1	0	0
T159	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	61	0	0
T16	261725	1	0	0
T17	569	2	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T130	0	1	0	0
T159	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	36962	0	0
T16	261725	106	0	0
T17	569	99	0	0
T18	694	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T40	0	80	0	0
T41	0	49	0	0
T42	0	360	0	0
T45	0	82	0	0
T46	0	39	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T130	0	29	0	0
T159	0	187	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	32	0	0
T17	569	1	0	0
T18	694	0	0	0
T19	12806	0	0	0
T40	691	1	0	0
T41	0	1	0	0
T45	0	2	0	0
T55	35116	0	0	0
T61	0	1	0	0
T62	503	0	0	0
T67	30384	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	2	0	0
T130	0	1	0	0
T152	0	1	0	0
T159	0	1	0	0
T207	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T36,T14,T26
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T14,T26
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T17,T40,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T17,T40,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T17,T40,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T36,T14,T26
1	1	Covered	T17,T40,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T40,T41
0	1	Covered	T208
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T40,T41
0	1	Covered	T17,T40,T130
1	0	Covered	T47,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T40,T41
1	-	Covered	T17,T40,T130

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T40,T41
0	1	Covered	T17,T40,T41
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T40,T41
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T40,T41
IdleSt	0	-	-	-	-	-	-	Covered	T36,T13,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T40,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T226
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T40,T41
DetectSt	-	-	-	-	1	-	-	Covered	T208
DetectSt	-	-	-	-	0	1	-	Covered	T17,T40,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T40,T130
StableSt	-	-	-	-	-	-	0	Covered	T17,T40,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	89	0	0
CntIncr_A	7942109	8573	0	0
CntNoWrap_A	7942109	7276994	0	0
DetectStDropOut_A	7942109	1	0	0
DetectedOut_A	7942109	13163	0	0
DetectedPulseOut_A	7942109	43	0	0
DisabledIdleSt_A	7942109	6955658	0	0
DisabledNoDetection_A	7942109	6957884	0	0
EnterDebounceSt_A	7942109	45	0	0
EnterDetectSt_A	7942109	44	0	0
EnterStableSt_A	7942109	43	0	0
PulseIsPulse_A	7942109	43	0	0
StayInStableSt	7942109	13099	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7942109	6908	0	0
gen_low_level_sva.LowLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	89	0	0
T17	569	2	0	0
T18	694	0	0	0
T19	12806	0	0	0
T40	691	4	0	0
T41	0	2	0	0
T47	0	2	0	0
T55	35116	0	0	0
T59	0	4	0	0
T62	503	0	0	0
T67	30384	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	4	0	0
T129	0	2	0	0
T130	0	4	0	0
T133	0	4	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	8573	0	0
T17	569	16	0	0
T18	694	0	0	0
T19	12806	0	0	0
T40	691	44	0	0
T41	0	65	0	0
T47	0	36	0	0
T55	35116	0	0	0
T59	0	146	0	0
T62	503	0	0	0
T67	30384	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	144	0	0
T129	0	18	0	0
T130	0	132	0	0
T133	0	64	0	0
T152	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276994	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	1	0	0
T167	17828	0	0	0
T169	502	0	0	0
T170	488	0	0	0
T171	740	0	0	0
T172	15572	0	0	0
T173	2904	0	0	0
T208	597	1	0	0
T227	10535	0	0	0
T228	425	0	0	0
T229	550	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	13163	0	0
T17	569	7	0	0
T18	694	0	0	0
T19	12806	0	0	0
T40	691	85	0	0
T41	0	222	0	0
T47	0	2	0	0
T55	35116	0	0	0
T59	0	151	0	0
T62	503	0	0	0
T67	30384	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	338	0	0
T129	0	42	0	0
T130	0	249	0	0
T133	0	146	0	0
T152	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	43	0	0
T17	569	1	0	0
T18	694	0	0	0
T19	12806	0	0	0
T40	691	2	0	0
T41	0	1	0	0
T47	0	1	0	0
T55	35116	0	0	0
T59	0	2	0	0
T62	503	0	0	0
T67	30384	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	2	0	0
T129	0	1	0	0
T130	0	2	0	0
T133	0	2	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6955658	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254202	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6957884	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254221	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	45	0	0
T17	569	1	0	0
T18	694	0	0	0
T19	12806	0	0	0
T40	691	2	0	0
T41	0	1	0	0
T47	0	1	0	0
T55	35116	0	0	0
T59	0	2	0	0
T62	503	0	0	0
T67	30384	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	2	0	0
T129	0	1	0	0
T130	0	2	0	0
T133	0	2	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	44	0	0
T17	569	1	0	0
T18	694	0	0	0
T19	12806	0	0	0
T40	691	2	0	0
T41	0	1	0	0
T47	0	1	0	0
T55	35116	0	0	0
T59	0	2	0	0
T62	503	0	0	0
T67	30384	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	2	0	0
T129	0	1	0	0
T130	0	2	0	0
T133	0	2	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	43	0	0
T17	569	1	0	0
T18	694	0	0	0
T19	12806	0	0	0
T40	691	2	0	0
T41	0	1	0	0
T47	0	1	0	0
T55	35116	0	0	0
T59	0	2	0	0
T62	503	0	0	0
T67	30384	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	2	0	0
T129	0	1	0	0
T130	0	2	0	0
T133	0	2	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	43	0	0
T17	569	1	0	0
T18	694	0	0	0
T19	12806	0	0	0
T40	691	2	0	0
T41	0	1	0	0
T47	0	1	0	0
T55	35116	0	0	0
T59	0	2	0	0
T62	503	0	0	0
T67	30384	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	2	0	0
T129	0	1	0	0
T130	0	2	0	0
T133	0	2	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	13099	0	0
T17	569	6	0	0
T18	694	0	0	0
T19	12806	0	0	0
T40	691	83	0	0
T41	0	220	0	0
T47	0	1	0	0
T55	35116	0	0	0
T59	0	148	0	0
T62	503	0	0	0
T67	30384	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	335	0	0
T129	0	40	0	0
T130	0	246	0	0
T133	0	143	0	0
T152	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6908	0	0
T13	499	0	0	0
T14	195034	3	0	0
T15	35944	8	0	0
T16	261725	44	0	0
T17	0	1	0	0
T26	421	3	0	0
T27	5633	27	0	0
T28	437	1	0	0
T29	715	3	0	0
T30	402	0	0	0
T31	0	9	0	0
T36	742	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	20	0	0
T17	569	1	0	0
T18	694	0	0	0
T19	12806	0	0	0
T40	691	2	0	0
T55	35116	0	0	0
T59	0	1	0	0
T62	503	0	0	0
T67	30384	0	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T112	0	1	0	0
T130	0	1	0	0
T133	0	1	0	0
T144	0	1	0	0
T152	0	1	0	0
T167	0	1	0	0
T215	0	1	0	0