Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T19,T20
1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T19,T20
1	0	Covered	T19,T20,T21
1	1	Covered	T27,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T19,T20
0	1	Covered	T27,T21,T85
1	0	Covered	T21,T47,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T38
0	1	Covered	T19,T20,T38
1	0	Covered	T47

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T38
1	-	Covered	T19,T20,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T19,T20
0	1	Covered	T27,T19,T20
0	0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T19,T20
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T27,T19,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T19,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T68,T182
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T27,T21,T85
DetectSt	-	-	-	-	0	1	-	Covered	T19,T20,T38
DetectSt	-	-	-	-	0	0	-	Covered	T27,T19,T20
StableSt	-	-	-	-	-	-	1	Covered	T19,T20,T38
StableSt	-	-	-	-	-	-	0	Covered	T19,T20,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	2983	0	0
CntIncr_A	7942109	104830	0	0
CntNoWrap_A	7942109	7274100	0	0
DetectStDropOut_A	7942109	401	0	0
DetectedOut_A	7942109	73652	0	0
DetectedPulseOut_A	7942109	897	0	0
DisabledIdleSt_A	7942109	6825255	0	0
DisabledNoDetection_A	7942109	6827376	0	0
EnterDebounceSt_A	7942109	1503	0	0
EnterDetectSt_A	7942109	1480	0	0
EnterStableSt_A	7942109	897	0	0
PulseIsPulse_A	7942109	897	0	0
StayInStableSt	7942109	72681	0	0
gen_high_event_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_high_level_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	822	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	2983	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	50	0	0
T20	0	4	0	0
T21	0	40	0	0
T27	5633	28	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	30	0	0
T49	0	44	0	0
T50	0	34	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T79	0	2	0	0
T102	0	28	0	0
T230	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	104830	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	1400	0	0
T20	0	120	0	0
T21	0	1389	0	0
T27	5633	832	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	900	0	0
T49	0	1782	0	0
T50	0	510	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T79	0	21	0	0
T102	0	840	0	0
T230	0	255	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7274100	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	5204	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	401	0	0
T17	569	0	0	0
T18	694	0	0	0
T21	0	10	0	0
T27	5633	14	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T85	0	25	0	0
T87	0	14	0	0
T88	0	5	0	0
T90	0	3	0	0
T91	0	25	0	0
T231	0	19	0	0
T232	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	73652	0	0
T19	12806	2673	0	0
T20	14286	22	0	0
T38	0	1144	0	0
T49	0	1232	0	0
T50	0	433	0	0
T71	0	2340	0	0
T78	35761	0	0	0
T79	0	46	0	0
T102	0	1109	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T230	0	175	0	0
T233	0	1772	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	897	0	0
T19	12806	25	0	0
T20	14286	2	0	0
T38	0	15	0	0
T49	0	22	0	0
T50	0	17	0	0
T71	0	26	0	0
T78	35761	0	0	0
T79	0	1	0	0
T102	0	14	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T230	0	3	0	0
T233	0	22	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6825255	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	2015	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6827376	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	2015	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	1503	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	25	0	0
T20	0	2	0	0
T21	0	20	0	0
T27	5633	14	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	15	0	0
T49	0	22	0	0
T50	0	17	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T79	0	1	0	0
T102	0	14	0	0
T230	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	1480	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	25	0	0
T20	0	2	0	0
T21	0	20	0	0
T27	5633	14	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	15	0	0
T49	0	22	0	0
T50	0	17	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T79	0	1	0	0
T102	0	14	0	0
T230	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	897	0	0
T19	12806	25	0	0
T20	14286	2	0	0
T38	0	15	0	0
T49	0	22	0	0
T50	0	17	0	0
T71	0	26	0	0
T78	35761	0	0	0
T79	0	1	0	0
T102	0	14	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T230	0	3	0	0
T233	0	22	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	897	0	0
T19	12806	25	0	0
T20	14286	2	0	0
T38	0	15	0	0
T49	0	22	0	0
T50	0	17	0	0
T71	0	26	0	0
T78	35761	0	0	0
T79	0	1	0	0
T102	0	14	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T230	0	3	0	0
T233	0	22	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	72681	0	0
T19	12806	2646	0	0
T20	14286	20	0	0
T38	0	1128	0	0
T49	0	1210	0	0
T50	0	416	0	0
T71	0	2314	0	0
T78	35761	0	0	0
T79	0	44	0	0
T102	0	1095	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T230	0	171	0	0
T233	0	1747	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	822	0	0
T19	12806	23	0	0
T20	14286	2	0	0
T38	0	14	0	0
T47	0	4	0	0
T49	0	22	0	0
T50	0	17	0	0
T71	0	26	0	0
T78	35761	0	0	0
T102	0	14	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T230	0	2	0	0
T233	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T15,T16
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T13,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T13,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T13,T15,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T15,T16,T27
1	1	Covered	T13,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T16
0	1	Covered	T52,T45,T86
1	0	Covered	T47,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T16
0	1	Covered	T13,T15,T16
1	0	Covered	T38

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T15,T16
1	-	Covered	T13,T15,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T15,T16
0	1	Covered	T13,T15,T16
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T16
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T15,T16
IdleSt	0	-	-	-	-	-	-	Covered	T36,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T15,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T79,T67,T160
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T15,T16
DetectSt	-	-	-	-	1	-	-	Covered	T52,T45,T86
DetectSt	-	-	-	-	0	1	-	Covered	T13,T15,T16
DetectSt	-	-	-	-	0	0	-	Covered	T13,T15,T16
StableSt	-	-	-	-	-	-	1	Covered	T13,T15,T16
StableSt	-	-	-	-	-	-	0	Covered	T13,T15,T16
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	820	0	0
CntIncr_A	7942109	43969	0	0
CntNoWrap_A	7942109	7276263	0	0
DetectStDropOut_A	7942109	45	0	0
DetectedOut_A	7942109	13329	0	0
DetectedPulseOut_A	7942109	332	0	0
DisabledIdleSt_A	7942109	6903263	0	0
DisabledNoDetection_A	7942109	6904935	0	0
EnterDebounceSt_A	7942109	441	0	0
EnterDetectSt_A	7942109	381	0	0
EnterStableSt_A	7942109	332	0	0
PulseIsPulse_A	7942109	332	0	0
StayInStableSt	7942109	12980	0	0
gen_high_level_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	311	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	820	0	0
T13	499	2	0	0
T14	195034	0	0	0
T15	35944	6	0	0
T16	261725	2	0	0
T19	0	6	0	0
T22	0	2	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	8	0	0
T39	0	8	0	0
T52	0	2	0	0
T66	0	6	0	0
T79	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	43969	0	0
T13	499	25	0	0
T14	195034	0	0	0
T15	35944	366	0	0
T16	261725	25	0	0
T19	0	279	0	0
T22	0	137	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	368	0	0
T39	0	456	0	0
T52	0	101	0	0
T66	0	291	0	0
T79	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276263	0	0
T13	499	96	0	0
T14	195034	194633	0	0
T15	35944	35440	0	0
T16	261725	254620	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	45	0	0
T38	16606	0	0	0
T39	19085	0	0	0
T45	24990	1	0	0
T52	11456	1	0	0
T53	17932	0	0	0
T77	726	0	0	0
T86	0	5	0	0
T89	0	4	0	0
T92	0	8	0	0
T93	0	7	0	0
T94	0	6	0	0
T95	0	8	0	0
T96	0	1	0	0
T97	0	3	0	0
T98	528	0	0	0
T99	583	0	0	0
T100	2172	0	0	0
T101	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	13329	0	0
T13	499	3	0	0
T14	195034	0	0	0
T15	35944	217	0	0
T16	261725	3	0	0
T19	0	181	0	0
T22	0	20	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	191	0	0
T39	0	230	0	0
T66	0	21	0	0
T67	0	834	0	0
T102	0	107	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	332	0	0
T13	499	1	0	0
T14	195034	0	0	0
T15	35944	3	0	0
T16	261725	1	0	0
T19	0	3	0	0
T22	0	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T66	0	3	0	0
T67	0	11	0	0
T102	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6903263	0	0
T13	499	4	0	0
T14	195034	194633	0	0
T15	35944	30217	0	0
T16	261725	254544	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6904935	0	0
T13	499	4	0	0
T14	195034	194634	0	0
T15	35944	30217	0	0
T16	261725	254564	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	441	0	0
T13	499	1	0	0
T14	195034	0	0	0
T15	35944	3	0	0
T16	261725	1	0	0
T19	0	3	0	0
T22	0	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T52	0	1	0	0
T66	0	3	0	0
T79	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	381	0	0
T13	499	1	0	0
T14	195034	0	0	0
T15	35944	3	0	0
T16	261725	1	0	0
T19	0	3	0	0
T22	0	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T52	0	1	0	0
T66	0	3	0	0
T67	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	332	0	0
T13	499	1	0	0
T14	195034	0	0	0
T15	35944	3	0	0
T16	261725	1	0	0
T19	0	3	0	0
T22	0	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T66	0	3	0	0
T67	0	11	0	0
T102	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	332	0	0
T13	499	1	0	0
T14	195034	0	0	0
T15	35944	3	0	0
T16	261725	1	0	0
T19	0	3	0	0
T22	0	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T66	0	3	0	0
T67	0	11	0	0
T102	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	12980	0	0
T13	499	2	0	0
T14	195034	0	0	0
T15	35944	214	0	0
T16	261725	2	0	0
T19	0	178	0	0
T22	0	19	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	187	0	0
T39	0	226	0	0
T66	0	18	0	0
T67	0	823	0	0
T102	0	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	311	0	0
T13	499	1	0	0
T14	195034	0	0	0
T15	35944	3	0	0
T16	261725	1	0	0
T19	0	3	0	0
T22	0	1	0	0
T26	421	0	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	3	0	0
T39	0	4	0	0
T66	0	3	0	0
T67	0	11	0	0
T102	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T19,T20
1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T19,T20
1	0	Covered	T19,T20,T21
1	1	Covered	T27,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T19,T20
0	1	Covered	T27,T19,T21
1	0	Covered	T19,T21,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T38,T49
0	1	Covered	T20,T38,T49
1	0	Covered	T71,T47,T195

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T38,T49
1	-	Covered	T20,T38,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T19,T20
0	1	Covered	T27,T19,T20
0	0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T19,T20
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T27,T19,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T19,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T68,T182
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T27,T19,T21
DetectSt	-	-	-	-	0	1	-	Covered	T20,T38,T49
DetectSt	-	-	-	-	0	0	-	Covered	T27,T19,T20
StableSt	-	-	-	-	-	-	1	Covered	T20,T38,T49
StableSt	-	-	-	-	-	-	0	Covered	T20,T38,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	2998	0	0
CntIncr_A	7942109	104567	0	0
CntNoWrap_A	7942109	7274085	0	0
DetectStDropOut_A	7942109	498	0	0
DetectedOut_A	7942109	58840	0	0
DetectedPulseOut_A	7942109	701	0	0
DisabledIdleSt_A	7942109	6835903	0	0
DisabledNoDetection_A	7942109	6838015	0	0
EnterDebounceSt_A	7942109	1516	0	0
EnterDetectSt_A	7942109	1482	0	0
EnterStableSt_A	7942109	701	0	0
PulseIsPulse_A	7942109	701	0	0
StayInStableSt	7942109	58057	0	0
gen_high_event_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_high_level_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	609	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	2998	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	22	0	0
T20	0	50	0	0
T21	0	26	0	0
T27	5633	50	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	32	0	0
T49	0	58	0	0
T50	0	16	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T102	0	22	0	0
T230	0	38	0	0
T233	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	104567	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	905	0	0
T20	0	1300	0	0
T21	0	895	0	0
T27	5633	1505	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	1024	0	0
T49	0	1885	0	0
T50	0	428	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T102	0	495	0	0
T230	0	1254	0	0
T233	0	255	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7274085	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	5182	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	498	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	3	0	0
T21	0	7	0	0
T27	5633	25	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T71	0	14	0	0
T85	0	12	0	0
T87	0	6	0	0
T206	0	4	0	0
T209	0	12	0	0
T234	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	58840	0	0
T20	14286	2222	0	0
T38	0	1545	0	0
T47	0	355	0	0
T49	0	1863	0	0
T71	0	4	0	0
T88	0	1496	0	0
T102	0	433	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T110	502	0	0	0
T214	0	13	0	0
T230	0	2196	0	0
T233	0	180	0	0
T235	493	0	0	0
T236	491	0	0	0
T237	525	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	701	0	0
T20	14286	25	0	0
T38	0	16	0	0
T47	0	5	0	0
T49	0	29	0	0
T71	0	4	0	0
T88	0	27	0	0
T102	0	11	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T110	502	0	0	0
T214	0	1	0	0
T230	0	19	0	0
T233	0	5	0	0
T235	493	0	0	0
T236	491	0	0	0
T237	525	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6835903	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	2015	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6838015	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	2015	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	1516	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	11	0	0
T20	0	25	0	0
T21	0	13	0	0
T27	5633	25	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	16	0	0
T49	0	29	0	0
T50	0	8	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T102	0	11	0	0
T230	0	19	0	0
T233	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	1482	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	11	0	0
T20	0	25	0	0
T21	0	13	0	0
T27	5633	25	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	16	0	0
T49	0	29	0	0
T50	0	8	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T102	0	11	0	0
T230	0	19	0	0
T233	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	701	0	0
T20	14286	25	0	0
T38	0	16	0	0
T47	0	5	0	0
T49	0	29	0	0
T71	0	4	0	0
T88	0	27	0	0
T102	0	11	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T110	502	0	0	0
T214	0	1	0	0
T230	0	19	0	0
T233	0	5	0	0
T235	493	0	0	0
T236	491	0	0	0
T237	525	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	701	0	0
T20	14286	25	0	0
T38	0	16	0	0
T47	0	5	0	0
T49	0	29	0	0
T71	0	4	0	0
T88	0	27	0	0
T102	0	11	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T110	502	0	0	0
T214	0	1	0	0
T230	0	19	0	0
T233	0	5	0	0
T235	493	0	0	0
T236	491	0	0	0
T237	525	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	58057	0	0
T20	14286	2195	0	0
T38	0	1525	0	0
T47	0	350	0	0
T49	0	1830	0	0
T88	0	1462	0	0
T102	0	422	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T110	502	0	0	0
T214	0	12	0	0
T230	0	2171	0	0
T233	0	174	0	0
T235	493	0	0	0
T236	491	0	0	0
T237	525	0	0	0
T238	0	610	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	609	0	0
T20	14286	23	0	0
T38	0	12	0	0
T47	0	4	0	0
T49	0	25	0	0
T88	0	20	0	0
T102	0	11	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T110	502	0	0	0
T214	0	1	0	0
T230	0	13	0	0
T233	0	4	0	0
T235	493	0	0	0
T236	491	0	0	0
T237	525	0	0	0
T238	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T27,T19
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T27,T19
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T15,T20,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T15,T20,T22

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T15,T20,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T20,T22
1	0	Covered	T15,T16,T27
1	1	Covered	T15,T20,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T20,T22
0	1	Covered	T52,T66,T204
1	0	Covered	T47,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T20,T22
0	1	Covered	T15,T20,T22
1	0	Covered	T47

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T20,T22
1	-	Covered	T15,T20,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T20,T22
0	1	Covered	T15,T20,T22
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T20,T22
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T20,T22
IdleSt	0	-	-	-	-	-	-	Covered	T36,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T20,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T53,T39
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T20,T22
DetectSt	-	-	-	-	1	-	-	Covered	T52,T66,T204
DetectSt	-	-	-	-	0	1	-	Covered	T15,T20,T22
DetectSt	-	-	-	-	0	0	-	Covered	T15,T20,T22
StableSt	-	-	-	-	-	-	1	Covered	T15,T20,T22
StableSt	-	-	-	-	-	-	0	Covered	T15,T20,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	865	0	0
CntIncr_A	7942109	50650	0	0
CntNoWrap_A	7942109	7276218	0	0
DetectStDropOut_A	7942109	84	0	0
DetectedOut_A	7942109	15065	0	0
DetectedPulseOut_A	7942109	318	0	0
DisabledIdleSt_A	7942109	6909704	0	0
DisabledNoDetection_A	7942109	6911384	0	0
EnterDebounceSt_A	7942109	460	0	0
EnterDetectSt_A	7942109	407	0	0
EnterStableSt_A	7942109	318	0	0
PulseIsPulse_A	7942109	318	0	0
StayInStableSt	7942109	14711	0	0
gen_high_level_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	278	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	865	0	0
T15	35944	27	0	0
T16	261725	0	0	0
T17	569	0	0	0
T20	0	4	0	0
T22	0	6	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	8	0	0
T39	0	7	0	0
T49	0	8	0	0
T52	0	6	0	0
T53	0	13	0	0
T54	726	0	0	0
T55	35116	0	0	0
T66	0	18	0	0
T67	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	50650	0	0
T15	35944	1397	0	0
T16	261725	0	0	0
T17	569	0	0	0
T20	0	134	0	0
T22	0	360	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	344	0	0
T39	0	355	0	0
T49	0	312	0	0
T52	0	304	0	0
T53	0	753	0	0
T54	726	0	0	0
T55	35116	0	0	0
T66	0	883	0	0
T67	0	395	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276218	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35419	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	84	0	0
T38	16606	0	0	0
T39	19085	0	0	0
T52	11456	3	0	0
T53	17932	0	0	0
T66	15541	8	0	0
T86	0	6	0	0
T92	0	2	0	0
T94	0	1	0	0
T98	528	0	0	0
T142	0	4	0	0
T155	0	4	0	0
T204	0	3	0	0
T239	0	4	0	0
T240	0	4	0	0
T241	441	0	0	0
T242	446	0	0	0
T243	504	0	0	0
T244	1511	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	15065	0	0
T15	35944	1231	0	0
T16	261725	0	0	0
T17	569	0	0	0
T20	0	170	0	0
T22	0	111	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	215	0	0
T39	0	239	0	0
T45	0	19	0	0
T49	0	235	0	0
T53	0	130	0	0
T54	726	0	0	0
T55	35116	0	0	0
T67	0	16	0	0
T83	0	26	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	318	0	0
T15	35944	13	0	0
T16	261725	0	0	0
T17	569	0	0	0
T20	0	2	0	0
T22	0	3	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T45	0	2	0	0
T49	0	4	0	0
T53	0	6	0	0
T54	726	0	0	0
T55	35116	0	0	0
T67	0	1	0	0
T83	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6909704	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	30217	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6911384	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	30217	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	460	0	0
T15	35944	14	0	0
T16	261725	0	0	0
T17	569	0	0	0
T20	0	2	0	0
T22	0	3	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T49	0	4	0	0
T52	0	3	0	0
T53	0	7	0	0
T54	726	0	0	0
T55	35116	0	0	0
T66	0	10	0	0
T67	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	407	0	0
T15	35944	13	0	0
T16	261725	0	0	0
T17	569	0	0	0
T20	0	2	0	0
T22	0	3	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T49	0	4	0	0
T52	0	3	0	0
T53	0	6	0	0
T54	726	0	0	0
T55	35116	0	0	0
T66	0	8	0	0
T67	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	318	0	0
T15	35944	13	0	0
T16	261725	0	0	0
T17	569	0	0	0
T20	0	2	0	0
T22	0	3	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T45	0	2	0	0
T49	0	4	0	0
T53	0	6	0	0
T54	726	0	0	0
T55	35116	0	0	0
T67	0	1	0	0
T83	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	318	0	0
T15	35944	13	0	0
T16	261725	0	0	0
T17	569	0	0	0
T20	0	2	0	0
T22	0	3	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T45	0	2	0	0
T49	0	4	0	0
T53	0	6	0	0
T54	726	0	0	0
T55	35116	0	0	0
T67	0	1	0	0
T83	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	14711	0	0
T15	35944	1218	0	0
T16	261725	0	0	0
T17	569	0	0	0
T20	0	168	0	0
T22	0	108	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	211	0	0
T39	0	236	0	0
T45	0	17	0	0
T49	0	227	0	0
T53	0	124	0	0
T54	726	0	0	0
T55	35116	0	0	0
T67	0	15	0	0
T83	0	22	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	278	0	0
T15	35944	13	0	0
T16	261725	0	0	0
T17	569	0	0	0
T20	0	2	0	0
T22	0	3	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T42	0	3	0	0
T45	0	2	0	0
T53	0	6	0	0
T54	726	0	0	0
T55	35116	0	0	0
T67	0	1	0	0
T83	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T19,T20
1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T19,T20
1	0	Covered	T19,T20,T21
1	1	Covered	T27,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T19,T20
0	1	Covered	T27,T38,T102
1	0	Covered	T38,T102,T233

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
1	0	Covered	T72,T68,T245

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T21
1	-	Covered	T19,T20,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T19,T20
0	1	Covered	T27,T19,T20
0	0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T19,T20
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T27,T19,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T19,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T68,T182
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T27,T38,T102
DetectSt	-	-	-	-	0	1	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	0	0	-	Covered	T27,T19,T20
StableSt	-	-	-	-	-	-	1	Covered	T19,T20,T21
StableSt	-	-	-	-	-	-	0	Covered	T19,T20,T21
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	2876	0	0
CntIncr_A	7942109	98392	0	0
CntNoWrap_A	7942109	7274207	0	0
DetectStDropOut_A	7942109	401	0	0
DetectedOut_A	7942109	60844	0	0
DetectedPulseOut_A	7942109	803	0	0
DisabledIdleSt_A	7942109	6833934	0	0
DisabledNoDetection_A	7942109	6836055	0	0
EnterDebounceSt_A	7942109	1454	0	0
EnterDetectSt_A	7942109	1422	0	0
EnterStableSt_A	7942109	803	0	0
PulseIsPulse_A	7942109	803	0	0
StayInStableSt	7942109	59968	0	0
gen_high_event_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_high_level_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	696	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	2876	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	50	0	0
T20	0	10	0	0
T21	0	8	0	0
T27	5633	12	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	22	0	0
T49	0	30	0	0
T50	0	30	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T102	0	24	0	0
T230	0	32	0	0
T233	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	98392	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	1600	0	0
T20	0	270	0	0
T21	0	228	0	0
T27	5633	357	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	844	0	0
T49	0	795	0	0
T50	0	405	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T102	0	759	0	0
T230	0	880	0	0
T233	0	1556	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7274207	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	5220	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	401	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	6	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	1	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T71	0	8	0	0
T85	0	12	0	0
T87	0	5	0	0
T90	0	2	0	0
T102	0	5	0	0
T214	0	13	0	0
T233	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	60844	0	0
T19	12806	2473	0	0
T20	14286	407	0	0
T21	0	57	0	0
T47	0	403	0	0
T49	0	1325	0	0
T50	0	426	0	0
T78	35761	0	0	0
T88	0	955	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T206	0	309	0	0
T209	0	1226	0	0
T230	0	1772	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	803	0	0
T19	12806	25	0	0
T20	14286	5	0	0
T21	0	4	0	0
T47	0	5	0	0
T49	0	15	0	0
T50	0	15	0	0
T78	35761	0	0	0
T88	0	18	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T206	0	8	0	0
T209	0	14	0	0
T230	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6833934	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	2015	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6836055	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	2015	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	1454	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	25	0	0
T20	0	5	0	0
T21	0	4	0	0
T27	5633	6	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	11	0	0
T49	0	15	0	0
T50	0	15	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T102	0	12	0	0
T230	0	16	0	0
T233	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	1422	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	25	0	0
T20	0	5	0	0
T21	0	4	0	0
T27	5633	6	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	11	0	0
T49	0	15	0	0
T50	0	15	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T102	0	12	0	0
T230	0	16	0	0
T233	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	803	0	0
T19	12806	25	0	0
T20	14286	5	0	0
T21	0	4	0	0
T47	0	5	0	0
T49	0	15	0	0
T50	0	15	0	0
T78	35761	0	0	0
T88	0	18	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T206	0	8	0	0
T209	0	14	0	0
T230	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	803	0	0
T19	12806	25	0	0
T20	14286	5	0	0
T21	0	4	0	0
T47	0	5	0	0
T49	0	15	0	0
T50	0	15	0	0
T78	35761	0	0	0
T88	0	18	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T206	0	8	0	0
T209	0	14	0	0
T230	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	59968	0	0
T19	12806	2446	0	0
T20	14286	401	0	0
T21	0	53	0	0
T47	0	398	0	0
T49	0	1307	0	0
T50	0	411	0	0
T78	35761	0	0	0
T88	0	934	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T206	0	301	0	0
T209	0	1211	0	0
T230	0	1751	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	696	0	0
T19	12806	23	0	0
T20	14286	4	0	0
T21	0	4	0	0
T47	0	5	0	0
T49	0	12	0	0
T50	0	15	0	0
T78	35761	0	0	0
T88	0	15	0	0
T103	432	0	0	0
T104	762	0	0	0
T105	1745	0	0	0
T106	773	0	0	0
T107	406	0	0	0
T108	427	0	0	0
T109	522	0	0	0
T206	0	8	0	0
T209	0	13	0	0
T230	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T27,T19
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T27,T19
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T15,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T15,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T15,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T19,T20
1	0	Covered	T15,T16,T27
1	1	Covered	T15,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T19,T20
0	1	Covered	T52,T67,T83
1	0	Covered	T47,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T19,T20
0	1	Covered	T15,T19,T20
1	0	Covered	T47,T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T19,T20
1	-	Covered	T15,T19,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T19,T20
0	1	Covered	T15,T19,T20
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T19,T20
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T36,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T19,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T20,T22
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T52,T67,T83
DetectSt	-	-	-	-	0	1	-	Covered	T15,T19,T20
DetectSt	-	-	-	-	0	0	-	Covered	T15,T19,T20
StableSt	-	-	-	-	-	-	1	Covered	T15,T19,T20
StableSt	-	-	-	-	-	-	0	Covered	T15,T19,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	781	0	0
CntIncr_A	7942109	46812	0	0
CntNoWrap_A	7942109	7276302	0	0
DetectStDropOut_A	7942109	78	0	0
DetectedOut_A	7942109	13324	0	0
DetectedPulseOut_A	7942109	287	0	0
DisabledIdleSt_A	7942109	6912429	0	0
DisabledNoDetection_A	7942109	6914122	0	0
EnterDebounceSt_A	7942109	416	0	0
EnterDetectSt_A	7942109	368	0	0
EnterStableSt_A	7942109	287	0	0
PulseIsPulse_A	7942109	287	0	0
StayInStableSt	7942109	13018	0	0
gen_high_level_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	264	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	781	0	0
T15	35944	6	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	6	0	0
T20	0	3	0	0
T22	0	25	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	10	0	0
T49	0	6	0	0
T52	0	6	0	0
T53	0	6	0	0
T54	726	0	0	0
T55	35116	0	0	0
T67	0	7	0	0
T83	0	9	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	46812	0	0
T15	35944	570	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	262	0	0
T20	0	107	0	0
T22	0	1159	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	700	0	0
T49	0	162	0	0
T52	0	304	0	0
T53	0	339	0	0
T54	726	0	0	0
T55	35116	0	0	0
T67	0	915	0	0
T83	0	771	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276302	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35440	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	78	0	0
T38	16606	0	0	0
T39	19085	0	0	0
T47	0	1	0	0
T49	16946	0	0	0
T52	11456	3	0	0
T53	17932	0	0	0
T67	30384	3	0	0
T81	16055	0	0	0
T83	0	4	0	0
T84	656	0	0	0
T89	0	2	0	0
T98	528	0	0	0
T155	0	5	0	0
T159	0	1	0	0
T160	1264	0	0	0
T239	0	2	0	0
T246	0	7	0	0
T247	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	13324	0	0
T15	35944	13	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	137	0	0
T20	0	83	0	0
T22	0	817	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	157	0	0
T45	0	159	0	0
T49	0	249	0	0
T53	0	52	0	0
T54	726	0	0	0
T55	35116	0	0	0
T204	0	142	0	0
T230	0	260	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	287	0	0
T15	35944	3	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T22	0	12	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	5	0	0
T45	0	2	0	0
T49	0	3	0	0
T53	0	3	0	0
T54	726	0	0	0
T55	35116	0	0	0
T204	0	10	0	0
T230	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6912429	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	30217	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6914122	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	30217	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	416	0	0
T15	35944	3	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	4	0	0
T20	0	2	0	0
T22	0	13	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	5	0	0
T49	0	3	0	0
T52	0	3	0	0
T53	0	3	0	0
T54	726	0	0	0
T55	35116	0	0	0
T67	0	4	0	0
T83	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	368	0	0
T15	35944	3	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T22	0	12	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	5	0	0
T49	0	3	0	0
T52	0	3	0	0
T53	0	3	0	0
T54	726	0	0	0
T55	35116	0	0	0
T67	0	3	0	0
T83	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	287	0	0
T15	35944	3	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T22	0	12	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	5	0	0
T45	0	2	0	0
T49	0	3	0	0
T53	0	3	0	0
T54	726	0	0	0
T55	35116	0	0	0
T204	0	10	0	0
T230	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	287	0	0
T15	35944	3	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T22	0	12	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	5	0	0
T45	0	2	0	0
T49	0	3	0	0
T53	0	3	0	0
T54	726	0	0	0
T55	35116	0	0	0
T204	0	10	0	0
T230	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	13018	0	0
T15	35944	10	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	135	0	0
T20	0	82	0	0
T22	0	805	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	152	0	0
T45	0	157	0	0
T49	0	243	0	0
T53	0	49	0	0
T54	726	0	0	0
T55	35116	0	0	0
T204	0	132	0	0
T230	0	256	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	264	0	0
T15	35944	3	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T22	0	12	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	5	0	0
T45	0	2	0	0
T53	0	3	0	0
T54	726	0	0	0
T55	35116	0	0	0
T88	0	1	0	0
T204	0	10	0	0
T230	0	4	0	0