Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T19,T20
1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T27,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T19,T20
1	0	Covered	T19,T20,T21
1	1	Covered	T27,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T19,T20
0	1	Covered	T27,T233,T85
1	0	Covered	T20,T38,T102

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T50
0	1	Covered	T19,T21,T50
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T21,T50
1	-	Covered	T19,T21,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T19,T20
0	1	Covered	T27,T19,T20
0	0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T19,T20
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T27,T19,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T19,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T68,T182
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T27,T20,T38
DetectSt	-	-	-	-	0	1	-	Covered	T19,T21,T50
DetectSt	-	-	-	-	0	0	-	Covered	T27,T19,T20
StableSt	-	-	-	-	-	-	1	Covered	T19,T21,T50
StableSt	-	-	-	-	-	-	0	Covered	T19,T21,T50
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	3227	0	0
CntIncr_A	7942109	113206	0	0
CntNoWrap_A	7942109	7273856	0	0
DetectStDropOut_A	7942109	469	0	0
DetectedOut_A	7942109	79014	0	0
DetectedPulseOut_A	7942109	923	0	0
DisabledIdleSt_A	7942109	6820233	0	0
DisabledNoDetection_A	7942109	6822327	0	0
EnterDebounceSt_A	7942109	1621	0	0
EnterDetectSt_A	7942109	1606	0	0
EnterStableSt_A	7942109	923	0	0
PulseIsPulse_A	7942109	923	0	0
StayInStableSt	7942109	77991	0	0
gen_high_event_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_high_level_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	823	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	3227	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	50	0	0
T20	0	22	0	0
T21	0	46	0	0
T27	5633	12	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	6	0	0
T49	0	16	0	0
T50	0	40	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T102	0	12	0	0
T230	0	54	0	0
T233	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	113206	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	1500	0	0
T20	0	766	0	0
T21	0	1058	0	0
T27	5633	359	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	229	0	0
T49	0	648	0	0
T50	0	620	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T102	0	384	0	0
T230	0	1512	0	0
T233	0	1556	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7273856	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	5220	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	469	0	0
T17	569	0	0	0
T18	694	0	0	0
T27	5633	6	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T47	0	1	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T85	0	25	0	0
T87	0	23	0	0
T88	0	8	0	0
T90	0	26	0	0
T91	0	11	0	0
T209	0	12	0	0
T214	0	27	0	0
T233	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	79014	0	0
T19	12806	2573	0	0
T21	11995	4415	0	0
T22	30509	0	0	0
T47	0	381	0	0
T49	0	172	0	0
T50	0	1513	0	0
T52	11456	0	0	0
T71	0	50	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T206	0	956	0	0
T230	0	3249	0	0
T234	0	2158	0	0
T238	0	365	0	0
T248	725	0	0	0
T249	408	0	0	0
T250	407	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	923	0	0
T19	12806	25	0	0
T21	11995	23	0	0
T22	30509	0	0	0
T47	0	5	0	0
T49	0	8	0	0
T50	0	20	0	0
T52	11456	0	0	0
T71	0	2	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T206	0	9	0	0
T230	0	27	0	0
T234	0	27	0	0
T238	0	7	0	0
T248	725	0	0	0
T249	408	0	0	0
T250	407	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6820233	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35446	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	2015	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6822327	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	2015	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	1621	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	25	0	0
T20	0	11	0	0
T21	0	23	0	0
T27	5633	6	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	3	0	0
T49	0	8	0	0
T50	0	20	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T102	0	6	0	0
T230	0	27	0	0
T233	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	1606	0	0
T17	569	0	0	0
T18	694	0	0	0
T19	0	25	0	0
T20	0	11	0	0
T21	0	23	0	0
T27	5633	6	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T38	0	3	0	0
T49	0	8	0	0
T50	0	20	0	0
T54	726	0	0	0
T55	35116	0	0	0
T62	503	0	0	0
T102	0	6	0	0
T230	0	27	0	0
T233	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	923	0	0
T19	12806	25	0	0
T21	11995	23	0	0
T22	30509	0	0	0
T47	0	5	0	0
T49	0	8	0	0
T50	0	20	0	0
T52	11456	0	0	0
T71	0	2	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T206	0	9	0	0
T230	0	27	0	0
T234	0	27	0	0
T238	0	7	0	0
T248	725	0	0	0
T249	408	0	0	0
T250	407	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	923	0	0
T19	12806	25	0	0
T21	11995	23	0	0
T22	30509	0	0	0
T47	0	5	0	0
T49	0	8	0	0
T50	0	20	0	0
T52	11456	0	0	0
T71	0	2	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T206	0	9	0	0
T230	0	27	0	0
T234	0	27	0	0
T238	0	7	0	0
T248	725	0	0	0
T249	408	0	0	0
T250	407	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	77991	0	0
T19	12806	2546	0	0
T21	11995	4391	0	0
T22	30509	0	0	0
T47	0	376	0	0
T49	0	163	0	0
T50	0	1493	0	0
T52	11456	0	0	0
T71	0	48	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T206	0	945	0	0
T230	0	3214	0	0
T234	0	2128	0	0
T238	0	357	0	0
T248	725	0	0	0
T249	408	0	0	0
T250	407	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	823	0	0
T19	12806	23	0	0
T21	11995	22	0	0
T22	30509	0	0	0
T47	0	5	0	0
T49	0	7	0	0
T50	0	20	0	0
T52	11456	0	0	0
T71	0	2	0	0
T78	35761	0	0	0
T103	432	0	0	0
T104	762	0	0	0
T206	0	7	0	0
T230	0	19	0	0
T234	0	24	0	0
T238	0	6	0	0
T248	725	0	0	0
T249	408	0	0	0
T250	407	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T27,T19
1	Covered	T36,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T27,T19
1	0	Covered	T36,T13,T14
1	1	Covered	T36,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T15,T19,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T13,T14	VC_COV_UNR
1	Covered	T15,T19,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T13,T14
1	Covered	T15,T19,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T19,T21
1	0	Covered	T15,T16,T27
1	1	Covered	T15,T19,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T19,T21
0	1	Covered	T83,T45,T204
1	0	Covered	T47,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T19,T21
0	1	Covered	T15,T19,T21
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T19,T21
1	-	Covered	T15,T19,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T19,T21
0	1	Covered	T15,T19,T21
0	0	Excluded	T36,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T19,T21
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T19,T21
IdleSt	0	-	-	-	-	-	-	Covered	T36,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T47,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T19,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T53,T39
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T19,T21
DetectSt	-	-	-	-	1	-	-	Covered	T83,T45,T204
DetectSt	-	-	-	-	0	1	-	Covered	T15,T19,T21
DetectSt	-	-	-	-	0	0	-	Covered	T15,T19,T21
StableSt	-	-	-	-	-	-	1	Covered	T15,T19,T21
StableSt	-	-	-	-	-	-	0	Covered	T15,T19,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T13,T14
0	Covered	T36,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7942109	794	0	0
CntIncr_A	7942109	43375	0	0
CntNoWrap_A	7942109	7276289	0	0
DetectStDropOut_A	7942109	66	0	0
DetectedOut_A	7942109	16136	0	0
DetectedPulseOut_A	7942109	304	0	0
DisabledIdleSt_A	7942109	6897771	0	0
DisabledNoDetection_A	7942109	6899465	0	0
EnterDebounceSt_A	7942109	422	0	0
EnterDetectSt_A	7942109	373	0	0
EnterStableSt_A	7942109	304	0	0
PulseIsPulse_A	7942109	304	0	0
StayInStableSt	7942109	15804	0	0
gen_high_level_sva.HighLevelEvent_A	7942109	7279371	0	0
gen_not_sticky_sva.StableStDropOut_A	7942109	274	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	794	0	0
T15	35944	10	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	16	0	0
T21	0	2	0	0
T22	0	14	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	7	0	0
T50	0	1	0	0
T52	0	6	0	0
T53	0	13	0	0
T54	726	0	0	0
T55	35116	0	0	0
T66	0	4	0	0
T67	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	43375	0	0
T15	35944	780	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	568	0	0
T21	0	63	0	0
T22	0	1064	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	565	0	0
T50	0	13	0	0
T52	0	279	0	0
T53	0	783	0	0
T54	726	0	0	0
T55	35116	0	0	0
T66	0	180	0	0
T67	0	480	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7276289	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	35436	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	66	0	0
T45	24990	1	0	0
T46	482	0	0	0
T68	0	1	0	0
T77	726	0	0	0
T83	62611	2	0	0
T99	583	0	0	0
T100	2172	0	0	0
T101	522	0	0	0
T118	550	0	0	0
T119	402	0	0	0
T120	425	0	0	0
T167	0	1	0	0
T204	0	3	0	0
T227	0	2	0	0
T251	0	4	0	0
T252	0	4	0	0
T253	0	3	0	0
T254	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	16136	0	0
T15	35944	164	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	666	0	0
T21	0	279	0	0
T22	0	39	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	27	0	0
T49	0	89	0	0
T52	0	25	0	0
T53	0	100	0	0
T54	726	0	0	0
T55	35116	0	0	0
T66	0	29	0	0
T67	0	21	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	304	0	0
T15	35944	4	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	8	0	0
T21	0	1	0	0
T22	0	7	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	3	0	0
T49	0	1	0	0
T52	0	3	0	0
T53	0	6	0	0
T54	726	0	0	0
T55	35116	0	0	0
T66	0	2	0	0
T67	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6897771	0	0
T13	499	98	0	0
T14	195034	194633	0	0
T15	35944	30217	0	0
T16	261725	254622	0	0
T26	421	20	0	0
T27	5633	5232	0	0
T28	437	36	0	0
T29	715	314	0	0
T30	402	1	0	0
T36	742	341	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	6899465	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	30217	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	422	0	0
T15	35944	6	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	8	0	0
T21	0	1	0	0
T22	0	7	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	4	0	0
T50	0	1	0	0
T52	0	3	0	0
T53	0	7	0	0
T54	726	0	0	0
T55	35116	0	0	0
T66	0	2	0	0
T67	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	373	0	0
T15	35944	4	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	8	0	0
T21	0	1	0	0
T22	0	7	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	3	0	0
T49	0	1	0	0
T52	0	3	0	0
T53	0	6	0	0
T54	726	0	0	0
T55	35116	0	0	0
T66	0	2	0	0
T67	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	304	0	0
T15	35944	4	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	8	0	0
T21	0	1	0	0
T22	0	7	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	3	0	0
T49	0	1	0	0
T52	0	3	0	0
T53	0	6	0	0
T54	726	0	0	0
T55	35116	0	0	0
T66	0	2	0	0
T67	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	304	0	0
T15	35944	4	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	8	0	0
T21	0	1	0	0
T22	0	7	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	3	0	0
T49	0	1	0	0
T52	0	3	0	0
T53	0	6	0	0
T54	726	0	0	0
T55	35116	0	0	0
T66	0	2	0	0
T67	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	15804	0	0
T15	35944	160	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	658	0	0
T21	0	278	0	0
T22	0	32	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	24	0	0
T49	0	87	0	0
T52	0	22	0	0
T53	0	94	0	0
T54	726	0	0	0
T55	35116	0	0	0
T66	0	27	0	0
T67	0	19	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	7279371	0	0
T13	499	99	0	0
T14	195034	194634	0	0
T15	35944	35461	0	0
T16	261725	254643	0	0
T26	421	21	0	0
T27	5633	5233	0	0
T28	437	37	0	0
T29	715	315	0	0
T30	402	2	0	0
T36	742	342	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7942109	274	0	0
T15	35944	4	0	0
T16	261725	0	0	0
T17	569	0	0	0
T19	0	8	0	0
T21	0	1	0	0
T22	0	7	0	0
T27	5633	0	0	0
T28	437	0	0	0
T29	715	0	0	0
T30	402	0	0	0
T31	488	0	0	0
T39	0	3	0	0
T45	0	1	0	0
T52	0	3	0	0
T53	0	6	0	0
T54	726	0	0	0
T55	35116	0	0	0
T66	0	2	0	0
T67	0	2	0	0