Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T13,T14
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T13,T14
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T41,T14,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T41,T14,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T41,T14,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T41,T14,T17
1	0	Covered	T41,T13,T14
1	1	Covered	T41,T14,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T41,T14,T17
0	1	Covered	T65,T52,T97
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T14,T17
0	1	Covered	T41,T14,T17
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T41,T14,T17
1	-	Covered	T41,T14,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T41,T14,T17
0	1	Covered	T41,T14,T17
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T41,T14,T17
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T41,T14,T17
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T41,T14,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T111,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T41,T14,T17
DetectSt	-	-	-	-	1	-	-	Covered	T65,T52,T97
DetectSt	-	-	-	-	0	1	-	Covered	T41,T14,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T14,T17
StableSt	-	-	-	-	-	-	0	Covered	T41,T14,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	267	0	0
CntIncr_A	8198376	66152	0	0
CntNoWrap_A	8198376	7499188	0	0
DetectStDropOut_A	8198376	3	0	0
DetectedOut_A	8198376	864	0	0
DetectedPulseOut_A	8198376	121	0	0
DisabledIdleSt_A	8198376	7427109	0	0
DisabledNoDetection_A	8198376	7429478	0	0
EnterDebounceSt_A	8198376	145	0	0
EnterDetectSt_A	8198376	124	0	0
EnterStableSt_A	8198376	121	0	0
PulseIsPulse_A	8198376	121	0	0
StayInStableSt	8198376	743	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8198376	7192	0	0
gen_low_level_sva.LowLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	121	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	267	0	0
T13	11076	0	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	0	3	0	0
T21	0	2	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T41	2031	6	0	0
T52	0	10	0	0
T53	0	6	0	0
T65	0	4	0	0
T80	0	2	0	0
T83	0	2	0	0
T84	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	66152	0	0
T13	11076	0	0	0
T14	19815	25	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	0	29	0	0
T21	0	48	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T41	2031	147	0	0
T52	0	4100	0	0
T53	0	144	0	0
T65	0	344	0	0
T80	0	95	0	0
T83	0	40	0	0
T84	0	233	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499188	0	0
T13	11076	10667	0	0
T14	19815	7026	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	823	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	3	0	0
T18	830	0	0	0
T19	555	0	0	0
T44	23959	0	0	0
T52	23803	1	0	0
T59	497	0	0	0
T65	2235	1	0	0
T87	427	0	0	0
T97	0	1	0	0
T101	4144	0	0	0
T102	522	0	0	0
T103	488	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	864	0	0
T13	11076	0	0	0
T14	19815	12	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	0	5	0	0
T21	0	7	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T41	2031	17	0	0
T52	0	39	0	0
T53	0	23	0	0
T65	0	11	0	0
T80	0	1	0	0
T83	0	12	0	0
T84	0	25	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	121	0	0
T13	11076	0	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	0	1	0	0
T21	0	1	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T41	2031	3	0	0
T52	0	4	0	0
T53	0	3	0	0
T65	0	1	0	0
T80	0	1	0	0
T83	0	1	0	0
T84	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7427109	0	0
T13	11076	10667	0	0
T14	19815	6947	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	528	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7429478	0	0
T13	11076	10669	0	0
T14	19815	6981	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	529	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	145	0	0
T13	11076	0	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	0	2	0	0
T21	0	1	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T41	2031	3	0	0
T52	0	6	0	0
T53	0	3	0	0
T65	0	2	0	0
T80	0	1	0	0
T83	0	1	0	0
T84	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	124	0	0
T13	11076	0	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	0	1	0	0
T21	0	1	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T41	2031	3	0	0
T52	0	5	0	0
T53	0	3	0	0
T65	0	2	0	0
T80	0	1	0	0
T83	0	1	0	0
T84	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	121	0	0
T13	11076	0	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	0	1	0	0
T21	0	1	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T41	2031	3	0	0
T52	0	4	0	0
T53	0	3	0	0
T65	0	1	0	0
T80	0	1	0	0
T83	0	1	0	0
T84	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	121	0	0
T13	11076	0	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	0	1	0	0
T21	0	1	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T41	2031	3	0	0
T52	0	4	0	0
T53	0	3	0	0
T65	0	1	0	0
T80	0	1	0	0
T83	0	1	0	0
T84	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	743	0	0
T13	11076	0	0	0
T14	19815	11	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	0	4	0	0
T21	0	6	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T41	2031	14	0	0
T52	0	35	0	0
T53	0	20	0	0
T65	0	10	0	0
T83	0	11	0	0
T84	0	21	0	0
T109	0	2	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7192	0	0
T13	11076	35	0	0
T14	19815	106	0	0
T15	12035	12	0	0
T16	8305	28	0	0
T30	405	0	0	0
T31	502	6	0	0
T32	665	3	0	0
T33	497	8	0	0
T34	422	2	0	0
T35	0	23	0	0
T41	2031	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	121	0	0
T13	11076	0	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	0	1	0	0
T21	0	1	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T41	2031	3	0	0
T52	0	4	0	0
T53	0	3	0	0
T65	0	1	0	0
T80	0	1	0	0
T83	0	1	0	0
T84	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T13,T14
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T13,T14
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T18,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T18,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T18,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T18,T42
1	0	Covered	T41,T13,T14
1	1	Covered	T14,T18,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T42
0	1	Covered	T73,T74,T75
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T42
0	1	Unreachable
1	0	Covered	T14,T18,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T18,T42
0	1	Covered	T14,T18,T42
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T18,T42
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T18,T42
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T18,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T56,T73
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T18,T42
DetectSt	-	-	-	-	1	-	-	Covered	T73,T74,T75
DetectSt	-	-	-	-	0	1	-	Covered	T14,T18,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T18,T42
StableSt	-	-	-	-	-	-	0	Covered	T14,T18,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	215	0	0
CntIncr_A	8198376	105243	0	0
CntNoWrap_A	8198376	7499240	0	0
DetectStDropOut_A	8198376	19	0	0
DetectedOut_A	8198376	106364	0	0
DetectedPulseOut_A	8198376	54	0	0
DisabledIdleSt_A	8198376	6015806	0	0
DisabledNoDetection_A	8198376	6018226	0	0
EnterDebounceSt_A	8198376	143	0	0
EnterDetectSt_A	8198376	73	0	0
EnterStableSt_A	8198376	54	0	0
PulseIsPulse_A	8198376	54	0	0
StayInStableSt	8198376	106310	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8198376	7192	0	0
gen_low_level_sva.LowLevelEvent_A	8198376	7501877	0	0
gen_sticky_sva.StableStDropOut_A	8198376	643999	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	215	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	2	0	0
T43	0	2	0	0
T52	0	5	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	6	0	0
T56	0	7	0	0
T57	503	0	0	0
T58	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	105243	0	0
T14	19815	86	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	21	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	42	0	0
T43	0	94	0	0
T52	0	135	0	0
T53	0	96	0	0
T54	0	88	0	0
T55	0	249	0	0
T56	0	482	0	0
T57	503	0	0	0
T58	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499240	0	0
T13	11076	10667	0	0
T14	19815	7026	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	19	0	0
T73	1560	4	0	0
T74	3074	3	0	0
T75	766	2	0	0
T93	15630	0	0	0
T112	0	2	0	0
T113	0	3	0	0
T114	0	4	0	0
T115	0	1	0	0
T116	12989	0	0	0
T117	494	0	0	0
T118	129008	0	0	0
T119	418	0	0	0
T120	403	0	0	0
T121	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	106364	0	0
T14	19815	509	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	8	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	183	0	0
T43	0	266	0	0
T53	0	38	0	0
T54	0	240	0	0
T55	0	354	0	0
T56	0	408	0	0
T57	503	0	0	0
T58	0	204	0	0
T110	0	306	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	54	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	503	0	0	0
T58	0	1	0	0
T110	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6015806	0	0
T13	11076	10667	0	0
T14	19815	6339	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6018226	0	0
T13	11076	10669	0	0
T14	19815	6374	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	143	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T52	0	5	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T56	0	6	0	0
T57	503	0	0	0
T58	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	73	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	503	0	0	0
T58	0	1	0	0
T73	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	54	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	503	0	0	0
T58	0	1	0	0
T110	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	54	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	503	0	0	0
T58	0	1	0	0
T110	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	106310	0	0
T14	19815	508	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	7	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	182	0	0
T43	0	265	0	0
T53	0	37	0	0
T54	0	239	0	0
T55	0	351	0	0
T56	0	407	0	0
T57	503	0	0	0
T58	0	203	0	0
T110	0	305	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7192	0	0
T13	11076	35	0	0
T14	19815	106	0	0
T15	12035	12	0	0
T16	8305	28	0	0
T30	405	0	0	0
T31	502	6	0	0
T32	665	3	0	0
T33	497	8	0	0
T34	422	2	0	0
T35	0	23	0	0
T41	2031	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	643999	0	0
T14	19815	85	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	108	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	24277	0	0
T43	0	58	0	0
T53	0	26	0	0
T54	0	27	0	0
T55	0	149193	0	0
T56	0	319	0	0
T57	503	0	0	0
T58	0	254	0	0
T110	0	57	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T31,T33

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T13,T30
1	0	Covered	T14,T31,T33
1	1	Covered	T14,T31,T33

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T18,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T18,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T18,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T18,T42
1	0	Covered	T14,T31,T33
1	1	Covered	T14,T18,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T42,T43
0	1	Covered	T14,T43,T71
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T42,T43
0	1	Unreachable
1	0	Covered	T18,T42,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T18,T42
0	1	Covered	T14,T18,T42
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T18,T42
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T18,T42
IdleSt	0	-	-	-	-	-	-	Covered	T14,T31,T33
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T18,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T55,T56
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T18,T42
DetectSt	-	-	-	-	1	-	-	Covered	T14,T43,T71
DetectSt	-	-	-	-	0	1	-	Covered	T18,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T42,T43
StableSt	-	-	-	-	-	-	0	Covered	T18,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	212	0	0
CntIncr_A	8198376	65188	0	0
CntNoWrap_A	8198376	7499243	0	0
DetectStDropOut_A	8198376	20	0	0
DetectedOut_A	8198376	287061	0	0
DetectedPulseOut_A	8198376	50	0	0
DisabledIdleSt_A	8198376	6015806	0	0
DisabledNoDetection_A	8198376	6018226	0	0
EnterDebounceSt_A	8198376	143	0	0
EnterDetectSt_A	8198376	70	0	0
EnterStableSt_A	8198376	50	0	0
PulseIsPulse_A	8198376	50	0	0
StayInStableSt	8198376	287011	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_sticky_sva.StableStDropOut_A	8198376	313326	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	212	0	0
T14	19815	6	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	2	0	0
T43	0	4	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	6	0	0
T56	0	6	0	0
T57	503	0	0	0
T58	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	65188	0	0
T14	19815	376	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	97	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	56	0	0
T43	0	48	0	0
T52	0	26	0	0
T53	0	15	0	0
T54	0	13	0	0
T55	0	144	0	0
T56	0	365	0	0
T57	503	0	0	0
T58	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499243	0	0
T13	11076	10667	0	0
T14	19815	7022	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	20	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T57	503	0	0	0
T71	0	2	0	0
T114	0	4	0	0
T122	0	4	0	0
T123	0	2	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	287061	0	0
T18	830	11	0	0
T19	555	0	0	0
T42	29850	469	0	0
T43	24553	26	0	0
T45	1104	0	0	0
T51	9693	0	0	0
T52	0	214	0	0
T53	0	9	0	0
T54	0	19	0	0
T56	0	304	0	0
T58	0	96	0	0
T71	0	65	0	0
T74	0	144	0	0
T82	11966	0	0	0
T87	427	0	0	0
T99	1158	0	0	0
T100	8236	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	50	0	0
T18	830	1	0	0
T19	555	0	0	0
T42	29850	1	0	0
T43	24553	1	0	0
T45	1104	0	0	0
T51	9693	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T71	0	2	0	0
T74	0	1	0	0
T82	11966	0	0	0
T87	427	0	0	0
T99	1158	0	0	0
T100	8236	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6015806	0	0
T13	11076	10667	0	0
T14	19815	6339	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6018226	0	0
T13	11076	10669	0	0
T14	19815	6374	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	143	0	0
T14	19815	4	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	6	0	0
T56	0	5	0	0
T57	503	0	0	0
T58	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	70	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	1	0	0
T43	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	503	0	0	0
T58	0	1	0	0
T74	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	50	0	0
T18	830	1	0	0
T19	555	0	0	0
T42	29850	1	0	0
T43	24553	1	0	0
T45	1104	0	0	0
T51	9693	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T71	0	2	0	0
T74	0	1	0	0
T82	11966	0	0	0
T87	427	0	0	0
T99	1158	0	0	0
T100	8236	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	50	0	0
T18	830	1	0	0
T19	555	0	0	0
T42	29850	1	0	0
T43	24553	1	0	0
T45	1104	0	0	0
T51	9693	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T71	0	2	0	0
T74	0	1	0	0
T82	11966	0	0	0
T87	427	0	0	0
T99	1158	0	0	0
T100	8236	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	287011	0	0
T18	830	10	0	0
T19	555	0	0	0
T42	29850	468	0	0
T43	24553	25	0	0
T45	1104	0	0	0
T51	9693	0	0	0
T52	0	213	0	0
T53	0	8	0	0
T54	0	18	0	0
T56	0	303	0	0
T58	0	95	0	0
T71	0	63	0	0
T74	0	143	0	0
T82	11966	0	0	0
T87	427	0	0	0
T99	1158	0	0	0
T100	8236	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	313326	0	0
T18	830	25	0	0
T19	555	0	0	0
T42	29850	23964	0	0
T43	24553	222	0	0
T45	1104	0	0	0
T51	9693	0	0	0
T52	0	168	0	0
T53	0	146	0	0
T54	0	323	0	0
T56	0	373	0	0
T58	0	359	0	0
T71	0	407	0	0
T74	0	84	0	0
T82	11966	0	0	0
T87	427	0	0	0
T99	1158	0	0	0
T100	8236	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T14,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T18,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T18,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T18,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T18,T42
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T18,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T43
0	1	Covered	T14,T54,T69
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T43
0	1	Unreachable
1	0	Covered	T14,T18,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T18,T42
0	1	Covered	T14,T18,T42
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T18,T43
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T18,T42
IdleSt	0	-	-	-	-	-	-	Covered	T13,T14,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T18,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T77,T124
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T18,T42
DetectSt	-	-	-	-	1	-	-	Covered	T14,T54,T69
DetectSt	-	-	-	-	0	1	-	Covered	T14,T18,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T18,T43
StableSt	-	-	-	-	-	-	0	Covered	T14,T18,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	204	0	0
CntIncr_A	8198376	255622	0	0
CntNoWrap_A	8198376	7499251	0	0
DetectStDropOut_A	8198376	17	0	0
DetectedOut_A	8198376	692090	0	0
DetectedPulseOut_A	8198376	67	0	0
DisabledIdleSt_A	8198376	6015806	0	0
DisabledNoDetection_A	8198376	6018226	0	0
EnterDebounceSt_A	8198376	121	0	0
EnterDetectSt_A	8198376	84	0	0
EnterStableSt_A	8198376	67	0	0
PulseIsPulse_A	8198376	67	0	0
StayInStableSt	8198376	692023	0	0
gen_high_event_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_sticky_sva.StableStDropOut_A	8198376	488924	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	204	0	0
T14	19815	4	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	5	0	0
T43	0	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	4	0	0
T55	0	6	0	0
T56	0	4	0	0
T57	503	0	0	0
T58	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	255622	0	0
T14	19815	38	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	29	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	24445	0	0
T43	0	34	0	0
T52	0	40	0	0
T53	0	67	0	0
T54	0	84	0	0
T55	0	62253	0	0
T56	0	102	0	0
T57	503	0	0	0
T58	0	59	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499251	0	0
T13	11076	10667	0	0
T14	19815	7024	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	17	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T54	0	2	0	0
T57	503	0	0	0
T69	0	1	0	0
T125	0	1	0	0
T128	0	2	0	0
T129	0	6	0	0
T130	0	2	0	0
T131	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	692090	0	0
T14	19815	42	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	5	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	157	0	0
T52	0	286	0	0
T53	0	50	0	0
T55	0	117413	0	0
T56	0	475	0	0
T57	503	0	0	0
T58	0	383	0	0
T73	0	419	0	0
T74	0	71	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	67	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	3	0	0
T56	0	2	0	0
T57	503	0	0	0
T58	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6015806	0	0
T13	11076	10667	0	0
T14	19815	6339	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6018226	0	0
T13	11076	10669	0	0
T14	19815	6374	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	121	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T42	0	5	0	0
T43	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	3	0	0
T56	0	2	0	0
T57	503	0	0	0
T58	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	84	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	0	3	0	0
T56	0	2	0	0
T57	503	0	0	0
T58	0	1	0	0
T73	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	67	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	3	0	0
T56	0	2	0	0
T57	503	0	0	0
T58	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	67	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	3	0	0
T56	0	2	0	0
T57	503	0	0	0
T58	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	692023	0	0
T14	19815	41	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	4	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	156	0	0
T52	0	285	0	0
T53	0	49	0	0
T55	0	117410	0	0
T56	0	473	0	0
T57	503	0	0	0
T58	0	382	0	0
T73	0	417	0	0
T74	0	70	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	488924	0	0
T14	19815	464	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T18	0	115	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	238	0	0
T52	0	85	0	0
T53	0	59	0	0
T55	0	133	0	0
T56	0	981	0	0
T57	503	0	0	0
T58	0	56	0	0
T73	0	94	0	0
T74	0	163	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T13,T30
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T17,T21,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T17,T21,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T17,T21,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T21
1	0	Covered	T41,T13,T30
1	1	Covered	T17,T21,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T21,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T21,T43
0	1	Covered	T43,T45,T53
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T21,T43
1	-	Covered	T43,T45,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T21,T43
0	1	Covered	T17,T21,T43
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T21,T43
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T21,T43
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T21,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T132
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T21,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T17,T21,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T45,T53
StableSt	-	-	-	-	-	-	0	Covered	T17,T21,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	92	0	0
CntIncr_A	8198376	37388	0	0
CntNoWrap_A	8198376	7499363	0	0
DetectStDropOut_A	8198376	0	0	0
DetectedOut_A	8198376	70729	0	0
DetectedPulseOut_A	8198376	45	0	0
DisabledIdleSt_A	8198376	7300714	0	0
DisabledNoDetection_A	8198376	7303081	0	0
EnterDebounceSt_A	8198376	47	0	0
EnterDetectSt_A	8198376	45	0	0
EnterStableSt_A	8198376	45	0	0
PulseIsPulse_A	8198376	45	0	0
StayInStableSt	8198376	70662	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	92	0	0
T17	36108	2	0	0
T18	830	0	0	0
T19	555	0	0	0
T21	21341	2	0	0
T43	0	2	0	0
T45	0	4	0	0
T47	0	2	0	0
T53	0	2	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T70	0	4	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T111	0	2	0	0
T133	0	2	0	0
T134	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	37388	0	0
T17	36108	95	0	0
T18	830	0	0	0
T19	555	0	0	0
T21	21341	25	0	0
T43	0	68	0	0
T45	0	182	0	0
T47	0	34981	0	0
T53	0	60	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T70	0	116	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T111	0	81	0	0
T133	0	36	0	0
T134	0	36	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499363	0	0
T13	11076	10667	0	0
T14	19815	7028	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	70729	0	0
T17	36108	220	0	0
T18	830	0	0	0
T19	555	0	0	0
T21	21341	46	0	0
T43	0	41	0	0
T45	0	216	0	0
T47	0	66835	0	0
T53	0	44	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T70	0	147	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T111	0	339	0	0
T133	0	42	0	0
T134	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	45	0	0
T17	36108	1	0	0
T18	830	0	0	0
T19	555	0	0	0
T21	21341	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T70	0	2	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T111	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7300714	0	0
T13	11076	10667	0	0
T14	19815	6945	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7303081	0	0
T13	11076	10669	0	0
T14	19815	6979	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	47	0	0
T17	36108	1	0	0
T18	830	0	0	0
T19	555	0	0	0
T21	21341	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T70	0	2	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T111	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	45	0	0
T17	36108	1	0	0
T18	830	0	0	0
T19	555	0	0	0
T21	21341	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T70	0	2	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T111	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	45	0	0
T17	36108	1	0	0
T18	830	0	0	0
T19	555	0	0	0
T21	21341	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T70	0	2	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T111	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	45	0	0
T17	36108	1	0	0
T18	830	0	0	0
T19	555	0	0	0
T21	21341	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T70	0	2	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T111	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	70662	0	0
T17	36108	218	0	0
T18	830	0	0	0
T19	555	0	0	0
T21	21341	44	0	0
T43	0	40	0	0
T45	0	213	0	0
T47	0	66833	0	0
T53	0	43	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T70	0	144	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T111	0	338	0	0
T133	0	40	0	0
T134	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	22	0	0
T43	24553	1	0	0
T44	23959	0	0	0
T45	1104	1	0	0
T51	9693	0	0	0
T52	23803	0	0	0
T53	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T101	4144	0	0	0
T102	522	0	0	0
T103	488	0	0	0
T104	507	0	0	0
T105	402	0	0	0
T111	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T13,T30
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T17,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T17,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T17,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T19
1	0	Covered	T41,T13,T14
1	1	Covered	T14,T17,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T19
0	1	Covered	T19,T139
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T19
0	1	Covered	T14,T17,T19
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T17,T19
1	-	Covered	T14,T17,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T17,T19
0	1	Covered	T14,T17,T19
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T19
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T19
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T140,T111
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T19
DetectSt	-	-	-	-	1	-	-	Covered	T19,T139
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T17,T19
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	146	0	0
CntIncr_A	8198376	21585	0	0
CntNoWrap_A	8198376	7499309	0	0
DetectStDropOut_A	8198376	2	0	0
DetectedOut_A	8198376	4665	0	0
DetectedPulseOut_A	8198376	68	0	0
DisabledIdleSt_A	8198376	7451533	0	0
DisabledNoDetection_A	8198376	7453896	0	0
EnterDebounceSt_A	8198376	76	0	0
EnterDetectSt_A	8198376	70	0	0
EnterStableSt_A	8198376	68	0	0
PulseIsPulse_A	8198376	68	0	0
StayInStableSt	8198376	4570	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8198376	2727	0	0
gen_low_level_sva.LowLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	146	0	0
T14	19815	6	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	2	0	0
T19	0	4	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	4	0	0
T45	0	3	0	0
T50	0	2	0	0
T53	0	4	0	0
T57	503	0	0	0
T109	0	2	0	0
T133	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	21585	0	0
T14	19815	39	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	95	0	0
T19	0	28	0	0
T21	0	85	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	136	0	0
T45	0	182	0	0
T50	0	73	0	0
T53	0	120	0	0
T57	503	0	0	0
T109	0	92	0	0
T133	0	36	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499309	0	0
T13	11076	10667	0	0
T14	19815	7022	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	2	0	0
T19	555	1	0	0
T139	8198	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	4665	0	0
T14	19815	130	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	136	0	0
T19	0	4	0	0
T21	0	45	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	87	0	0
T45	0	168	0	0
T50	0	310	0	0
T53	0	111	0	0
T57	503	0	0	0
T109	0	162	0	0
T133	0	135	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	68	0	0
T14	19815	3	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T50	0	1	0	0
T53	0	2	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7451533	0	0
T13	11076	10667	0	0
T14	19815	6719	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7453896	0	0
T13	11076	10669	0	0
T14	19815	6752	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	76	0	0
T14	19815	3	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	2	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	2	0	0
T45	0	2	0	0
T50	0	1	0	0
T53	0	2	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	70	0	0
T14	19815	3	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	2	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T50	0	1	0	0
T53	0	2	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	68	0	0
T14	19815	3	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T50	0	1	0	0
T53	0	2	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	68	0	0
T14	19815	3	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T50	0	1	0	0
T53	0	2	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	4570	0	0
T14	19815	126	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	135	0	0
T19	0	3	0	0
T21	0	43	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	84	0	0
T45	0	167	0	0
T50	0	308	0	0
T53	0	108	0	0
T57	503	0	0	0
T109	0	161	0	0
T133	0	134	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	2727	0	0
T14	19815	82	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	9	0	0
T19	0	2	0	0
T31	502	5	0	0
T32	665	0	0	0
T33	497	5	0	0
T34	422	1	0	0
T35	10465	0	0	0
T57	503	7	0	0
T59	0	6	0	0
T86	0	4	0	0
T87	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	40	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	1	0	0
T141	0	2	0	0
T142	0	1	0	0