Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	248683	0	0
SrcPulseCheck_M	2147483647	252175	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	248683
T1	2903934	33
T2	4860120	400
T3	1567449	62
T4	165279	630
T5	422	132
T6	574	140
T9	1985	704
T10	0	722
T11	0	795
T12	0	84
T23	3273303	0
T24	3286992	0
T25	6590118	0
T26	6382488	0
T27	6742698	8448
T28	1695089	0
T29	3377593	0
T39	15059	0
T40	0	173

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	252175
T1	3269720	107
T2	5441258	400
T3	1753981	62
T4	0	661
T5	0	132
T6	0	140
T8	1986110	34
T9	0	706
T10	0	495
T11	0	387
T12	0	10
T23	3683399	0
T24	3682433	0
T25	7385960	0
T26	7152712	0
T27	7432722	8448
T28	1897101	0
T29	331089	29
T49	0	6

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	2136	0	0
SrcPulseCheck_M	1088100268	2231	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	2136
T2	1082	9
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	10
T10	0	13
T11	0	9
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	2231
T1	87998	2
T2	146096	9
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	10
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	2205	0	0
SrcPulseCheck_M	8478194	2205	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	2205
T1	87998	1
T2	146096	9
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T9	0	10
T10	0	13
T11	0	9
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	2205
T1	418	1
T2	1082	9
T3	408	1
T4	0	9
T5	0	2
T6	0	2
T9	0	10
T10	0	13
T11	0	9
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T2,T27,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1133	0	0
SrcPulseCheck_M	1088100268	1227	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1133
T2	1082	4
T3	408	1
T4	4467	9
T5	0	1
T6	0	2
T9	0	4
T10	0	12
T11	0	11
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	1227
T1	87998	2
T2	146096	4
T3	47041	1
T4	0	10
T5	0	1
T6	0	2
T8	58415	1
T9	0	4
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	1201	0	0
SrcPulseCheck_M	8478194	1201	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	1201
T1	87998	1
T2	146096	4
T3	47041	1
T4	0	10
T5	0	1
T6	0	2
T9	0	4
T10	0	12
T11	0	11
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	1201
T1	418	1
T2	1082	4
T3	408	1
T4	0	10
T5	0	1
T6	0	2
T9	0	4
T10	0	12
T11	0	11
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1161	0	0
SrcPulseCheck_M	1088100268	1255	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1161
T2	1082	3
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	16
T10	0	13
T11	0	11
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	1255
T1	87998	2
T2	146096	3
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	16
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	1228	0	0
SrcPulseCheck_M	8478194	1228	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	1228
T1	87998	1
T2	146096	3
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T9	0	16
T10	0	13
T11	0	11
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	1228
T1	418	1
T2	1082	3
T3	408	1
T4	0	10
T5	0	2
T6	0	2
T9	0	16
T10	0	13
T11	0	11
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1175	0	0
SrcPulseCheck_M	1088100268	1267	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1175
T2	1082	9
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	8
T10	0	10
T11	0	9
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	1267
T1	87998	2
T2	146096	9
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	8
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	1240	0	0
SrcPulseCheck_M	8478194	1240	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	1240
T1	87998	1
T2	146096	9
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T9	0	8
T10	0	10
T11	0	9
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	1240
T1	418	1
T2	1082	9
T3	408	1
T4	0	9
T5	0	2
T6	0	2
T9	0	8
T10	0	10
T11	0	9
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T2,T27,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1215	0	0
SrcPulseCheck_M	1088100268	1307	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1215
T2	1082	5
T3	408	1
T4	4467	9
T5	0	1
T6	0	2
T9	0	16
T10	0	13
T11	0	16
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	1307
T1	87998	2
T2	146096	5
T3	47041	1
T4	0	10
T5	0	1
T6	0	2
T8	58415	1
T9	0	16
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	1282	0	0
SrcPulseCheck_M	8478194	1282	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	1282
T1	87998	1
T2	146096	5
T3	47041	1
T4	0	10
T5	0	1
T6	0	2
T9	0	16
T10	0	13
T11	0	16
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	1282
T1	418	1
T2	1082	5
T3	408	1
T4	0	10
T5	0	1
T6	0	2
T9	0	16
T10	0	13
T11	0	16
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T5,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	508	0	0
SrcPulseCheck_M	1088100268	605	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	508
T2	1082	10
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	11
T10	0	5
T11	0	5
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	0
T28	407	0
T29	811	0
T39	407	0
T40	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	605
T1	87998	2
T2	146096	10
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	11
T10	0	6
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	0
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T5,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1089	0	0
SrcPulseCheck_M	1088100268	1210	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1089
T2	1082	11
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	16
T10	0	6
T11	0	14
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	0
T28	407	0
T29	811	0
T39	407	0
T40	0	19

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	1210
T1	87998	2
T2	146096	11
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	16
T10	0	7
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	0
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	3208	0	0
SrcPulseCheck_M	1088100268	3300	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	3208
T2	1082	6
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	10
T10	0	6
T11	0	19
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	3300
T1	87998	2
T2	146096	6
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	10
T10	0	6
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	3274	0	0
SrcPulseCheck_M	8478194	3274	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	3274
T1	87998	1
T2	146096	6
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T9	0	10
T10	0	6
T11	0	19
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	3274
T1	418	1
T2	1082	6
T3	408	1
T4	0	9
T5	0	2
T6	0	2
T9	0	10
T10	0	6
T11	0	19
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	6924	0	0
SrcPulseCheck_M	1088100268	7019	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	6924
T2	1082	4
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	11
T10	0	2
T11	0	15
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	7019
T1	87998	2
T2	146096	4
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	11
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	6991	0	0
SrcPulseCheck_M	8478194	6991	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	6991
T1	87998	1
T2	146096	4
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T9	0	11
T10	0	2
T11	0	15
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	6991
T1	418	1
T2	1082	4
T3	408	1
T4	0	9
T5	0	2
T6	0	2
T9	0	11
T10	0	2
T11	0	15
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T27
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T27

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	8068	0	0
SrcPulseCheck_M	1088100268	8162	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	8068
T2	1082	6
T3	408	0
T4	4467	8
T5	0	2
T6	0	2
T9	0	13
T10	0	15
T11	0	13
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0
T40	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	8162
T1	87998	2
T2	146096	6
T3	47041	0
T4	0	9
T5	0	2
T6	0	2
T8	58415	1
T9	0	13
T10	0	15
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T27
1	0	Covered	T2,T27,T4
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T27
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T27

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	8136	0	0
SrcPulseCheck_M	8478194	8136	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	8136
T1	87998	1
T2	146096	6
T3	47041	0
T4	0	9
T5	0	2
T6	0	2
T9	0	13
T10	0	15
T11	0	13
T12	0	2
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	8136
T1	418	1
T2	1082	6
T3	408	0
T4	0	9
T5	0	2
T6	0	2
T9	0	13
T10	0	15
T11	0	13
T12	0	2
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	6792	0	0
SrcPulseCheck_M	1088100268	6886	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	6792
T2	1082	9
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	10
T10	0	20
T11	0	14
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	6886
T1	87998	2
T2	146096	9
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	10
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	6860	0	0
SrcPulseCheck_M	8478194	6860	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	6860
T1	87998	1
T2	146096	9
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T9	0	10
T10	0	20
T11	0	14
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	6860
T1	418	1
T2	1082	9
T3	408	1
T4	0	10
T5	0	2
T6	0	2
T9	0	10
T10	0	20
T11	0	14
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1183	0	0
SrcPulseCheck_M	1088100268	1274	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1183
T2	1082	4
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	3
T10	0	9
T11	0	9
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	1274
T1	87998	2
T2	146096	4
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	3
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	1248	0	0
SrcPulseCheck_M	8478194	1248	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	1248
T1	87998	1
T2	146096	4
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T9	0	3
T10	0	9
T11	0	9
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	1248
T1	418	1
T2	1082	4
T3	408	1
T4	0	10
T5	0	2
T6	0	2
T9	0	3
T10	0	9
T11	0	9
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T3
1	0	Covered	T8,T1,T3
1	1	Covered	T27,T5,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T3,T27
1	0	Covered	T27,T5,T6
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	2154	0	0
SrcPulseCheck_M	1088100268	2246	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	2154
T3	408	1
T4	4467	8
T5	422	2
T6	574	2
T9	1985	9
T10	0	9
T11	0	7
T12	0	2
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0
T40	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	2246
T1	87998	2
T2	146096	0
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T8	58415	1
T9	0	9
T10	0	9
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T3,T27
1	0	Covered	T3,T27,T4
1	1	Covered	T27,T5,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T3,T27
1	0	Covered	T27,T5,T6
1	1	Covered	T1,T3,T27

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	2219	0	0
SrcPulseCheck_M	8478194	2219	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	2219
T1	87998	1
T2	146096	0
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T9	0	9
T10	0	9
T11	0	7
T12	0	2
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	2219
T1	418	1
T2	1082	0
T3	408	1
T4	0	9
T5	0	2
T6	0	2
T9	0	9
T10	0	9
T11	0	7
T12	0	2
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T27
1	0	Covered	T1,T2,T27
1	1	Covered	T2,T27,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T27
1	0	Covered	T2,T27,T6
1	1	Covered	T1,T2,T27

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1424	0	0
SrcPulseCheck_M	1088100268	1519	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1424
T2	1082	10
T3	408	0
T4	4467	8
T5	0	1
T6	0	2
T9	0	8
T10	0	10
T11	0	13
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0
T40	0	19

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	1519
T1	87998	2
T2	146096	10
T3	47041	0
T4	0	9
T5	0	1
T6	0	2
T9	0	8
T10	0	10
T11	0	13
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0
T49	0	2

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T27
1	0	Covered	T2,T27,T4
1	1	Covered	T2,T27,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T27
1	0	Covered	T2,T27,T6
1	1	Covered	T1,T2,T27

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	1493	0	0
SrcPulseCheck_M	8478194	1493	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	1493
T1	87998	1
T2	146096	10
T3	47041	0
T4	0	9
T5	0	1
T6	0	2
T9	0	8
T10	0	10
T11	0	13
T12	0	2
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	1493
T1	418	1
T2	1082	10
T3	408	0
T4	0	9
T5	0	1
T6	0	2
T9	0	8
T10	0	10
T11	0	13
T12	0	2
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1272	0	0
SrcPulseCheck_M	1088100268	1365	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1272
T2	1082	3
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	11
T10	0	2
T11	0	7
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	1365
T1	87998	2
T2	146096	3
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	11
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	1340	0	0
SrcPulseCheck_M	8478194	1340	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	1340
T1	87998	1
T2	146096	3
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T9	0	11
T10	0	2
T11	0	7
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	1340
T1	418	1
T2	1082	3
T3	408	1
T4	0	10
T5	0	2
T6	0	2
T9	0	11
T10	0	2
T11	0	7
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T27
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	7558	0	0
SrcPulseCheck_M	1088100268	7655	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	7558
T2	1082	2
T3	408	0
T4	4467	8
T5	0	2
T6	0	2
T9	0	19
T10	0	9
T11	0	17
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0
T40	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	7655
T1	87998	2
T2	146096	2
T3	47041	0
T4	0	9
T5	0	2
T6	0	2
T8	58415	1
T9	0	19
T10	0	9
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T27
1	0	Covered	T2,T27,T4
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T27
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	7629	0	0
SrcPulseCheck_M	8478194	7629	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	7629
T1	87998	1
T2	146096	2
T3	47041	0
T4	0	9
T5	0	2
T6	0	2
T9	0	19
T10	0	9
T11	0	17
T12	0	2
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	7629
T1	418	1
T2	1082	2
T3	408	0
T4	0	9
T5	0	2
T6	0	2
T9	0	19
T10	0	9
T11	0	17
T12	0	2
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	7506	0	0
SrcPulseCheck_M	1088100268	7604	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	7506
T2	1082	3
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	13
T10	0	10
T11	0	7
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	7604
T1	87998	2
T2	146096	3
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	13
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	7577	0	0
SrcPulseCheck_M	8478194	7577	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	7577
T1	87998	1
T2	146096	3
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T9	0	13
T10	0	10
T11	0	7
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	7577
T1	418	1
T2	1082	3
T3	408	1
T4	0	10
T5	0	2
T6	0	2
T9	0	13
T10	0	10
T11	0	7
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	7384	0	0
SrcPulseCheck_M	1088100268	7479	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	7384
T2	1082	5
T3	408	1
T4	4467	8
T5	0	2
T6	0	2
T9	0	5
T10	0	14
T11	0	17
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	7479
T1	87998	2
T2	146096	5
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T8	58415	1
T9	0	5
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	7454	0	0
SrcPulseCheck_M	8478194	7454	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	7454
T1	87998	1
T2	146096	5
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T9	0	5
T10	0	14
T11	0	17
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	7454
T1	418	1
T2	1082	5
T3	408	1
T4	0	9
T5	0	2
T6	0	2
T9	0	5
T10	0	14
T11	0	17
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	7537	0	0
SrcPulseCheck_M	1088100268	7628	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	7537
T2	1082	11
T3	408	1
T4	4467	8
T5	0	2
T6	0	2
T9	0	11
T10	0	6
T11	0	9
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	7628
T1	87998	2
T2	146096	11
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T8	58415	1
T9	0	11
T10	0	6
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	7605	0	0
SrcPulseCheck_M	8478194	7605	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	7605
T1	87998	1
T2	146096	11
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T9	0	11
T10	0	6
T11	0	9
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	7605
T1	418	1
T2	1082	11
T3	408	1
T4	0	9
T5	0	2
T6	0	2
T9	0	11
T10	0	6
T11	0	9
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1345	0	0
SrcPulseCheck_M	1088100268	1439	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1345
T2	1082	3
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	5
T10	0	10
T11	0	3
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	1439
T1	87998	2
T2	146096	3
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T8	58415	1
T9	0	6
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	1412	0	0
SrcPulseCheck_M	8478194	1412	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	1412
T1	87998	1
T2	146096	3
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T9	0	6
T10	0	10
T11	0	3
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	1412
T1	418	1
T2	1082	3
T3	408	1
T4	0	9
T5	0	2
T6	0	2
T9	0	6
T10	0	10
T11	0	3
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1346	0	0
SrcPulseCheck_M	1088100268	1437	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1346
T2	1082	2
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	5
T10	0	4
T11	0	8
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	1437
T1	87998	2
T2	146096	2
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	5
T10	0	4
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	1413	0	0
SrcPulseCheck_M	8478194	1413	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	1413
T1	87998	1
T2	146096	2
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T9	0	5
T10	0	4
T11	0	8
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	1413
T1	418	1
T2	1082	2
T3	408	1
T4	0	10
T5	0	2
T6	0	2
T9	0	5
T10	0	4
T11	0	8
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T27,T5,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T5,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1356	0	0
SrcPulseCheck_M	1088100268	1448	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1356
T2	1082	1
T3	408	1
T4	4467	8
T5	0	2
T6	0	2
T9	0	13
T10	0	9
T11	0	10
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	1448
T1	87998	2
T2	146096	1
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T8	58415	1
T9	0	13
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T27,T5,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T5,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	1423	0	0
SrcPulseCheck_M	8478194	1423	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	1423
T1	87998	1
T2	146096	1
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T9	0	13
T10	0	9
T11	0	10
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	1423
T1	418	1
T2	1082	1
T3	408	1
T4	0	9
T5	0	2
T6	0	2
T9	0	13
T10	0	9
T11	0	10
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1377	0	0
SrcPulseCheck_M	1088100268	1468	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1377
T2	1082	11
T3	408	1
T4	4467	8
T5	0	2
T6	0	2
T9	0	5
T10	0	20
T11	0	8
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	1468
T1	87998	2
T2	146096	11
T3	47041	1
T4	0	8
T5	0	2
T6	0	2
T8	58415	1
T9	0	5
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	1444	0	0
SrcPulseCheck_M	8478194	1444	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	1444
T1	87998	1
T2	146096	11
T3	47041	1
T4	0	8
T5	0	2
T6	0	2
T9	0	5
T10	0	20
T11	0	9
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	1444
T1	418	1
T2	1082	11
T3	408	1
T4	0	8
T5	0	2
T6	0	2
T9	0	5
T10	0	20
T11	0	9
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	8245	0	0
SrcPulseCheck_M	1088100268	8339	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	8245
T2	1082	10
T3	408	1
T4	4467	8
T5	0	2
T6	0	2
T9	0	6
T10	0	13
T11	0	19
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	8339
T1	87998	2
T2	146096	10
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T8	58415	1
T9	0	6
T10	0	13
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	8314	0	0
SrcPulseCheck_M	8478194	8314	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	8314
T1	87998	1
T2	146096	10
T3	47041	1
T4	0	8
T5	0	2
T6	0	2
T9	0	6
T10	0	13
T11	0	19
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	8314
T1	418	1
T2	1082	10
T3	408	1
T4	0	8
T5	0	2
T6	0	2
T9	0	6
T10	0	13
T11	0	19
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T2,T27,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	8110	0	0
SrcPulseCheck_M	1088100268	8208	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	8110
T2	1082	2
T3	408	1
T4	4467	9
T5	0	1
T6	0	2
T9	0	13
T10	0	12
T11	0	11
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	8208
T1	87998	2
T2	146096	2
T3	47041	1
T4	0	10
T5	0	1
T6	0	2
T8	58415	1
T9	0	13
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	8182	0	0
SrcPulseCheck_M	8478194	8182	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	8182
T1	87998	1
T2	146096	2
T3	47041	1
T4	0	10
T5	0	1
T6	0	2
T9	0	13
T10	0	12
T11	0	11
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	8182
T1	418	1
T2	1082	2
T3	408	1
T4	0	10
T5	0	1
T6	0	2
T9	0	13
T10	0	12
T11	0	11
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	7990	0	0
SrcPulseCheck_M	1088100268	8082	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	7990
T2	1082	7
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	14
T10	0	6
T11	0	12
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	8082
T1	87998	2
T2	146096	7
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T8	58415	1
T9	0	14
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	8056	0	0
SrcPulseCheck_M	8478194	8056	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	8056
T1	87998	1
T2	146096	7
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T9	0	14
T10	0	6
T11	0	12
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	8056
T1	418	1
T2	1082	7
T3	408	1
T4	0	9
T5	0	2
T6	0	2
T9	0	14
T10	0	6
T11	0	12
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	8150	0	0
SrcPulseCheck_M	1088100268	8246	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	8150
T2	1082	9
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	14
T10	0	6
T11	0	2
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	8246
T1	87998	2
T2	146096	9
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	14
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	8219	0	0
SrcPulseCheck_M	8478194	8219	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	8219
T1	87998	1
T2	146096	9
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T9	0	14
T10	0	6
T11	0	2
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	8219
T1	418	1
T2	1082	9
T3	408	1
T4	0	10
T5	0	2
T6	0	2
T9	0	14
T10	0	6
T11	0	2
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	2060	0	0
SrcPulseCheck_M	1088100268	2152	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	2060
T2	1082	6
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	8
T10	0	7
T11	0	16
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	2152
T1	87998	2
T2	146096	6
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T8	58415	1
T9	0	8
T10	0	7
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	2127	0	0
SrcPulseCheck_M	8478194	2127	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	2127
T1	87998	1
T2	146096	6
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T9	0	8
T10	0	7
T11	0	16
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	2127
T1	418	1
T2	1082	6
T3	408	1
T4	0	9
T5	0	2
T6	0	2
T9	0	8
T10	0	7
T11	0	16
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1954	0	0
SrcPulseCheck_M	1088100268	2048	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1954
T2	1082	5
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	9
T10	0	1
T11	0	11
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	2048
T1	87998	2
T2	146096	5
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T8	58415	1
T9	0	10
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	2021	0	0
SrcPulseCheck_M	8478194	2021	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	2021
T1	87998	1
T2	146096	5
T3	47041	1
T4	0	9
T5	0	2
T6	0	2
T9	0	9
T10	0	1
T11	0	11
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	2021
T1	418	1
T2	1082	5
T3	408	1
T4	0	9
T5	0	2
T6	0	2
T9	0	9
T10	0	1
T11	0	11
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1972	0	0
SrcPulseCheck_M	1088100268	2063	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1972
T2	1082	5
T3	408	1
T4	4467	7
T5	0	2
T6	0	2
T9	0	18
T10	0	10
T11	0	9
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	2063
T1	87998	2
T2	146096	5
T3	47041	1
T4	0	8
T5	0	2
T6	0	2
T8	58415	1
T9	0	18
T10	0	10
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	2038	0	0
SrcPulseCheck_M	8478194	2038	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	2038
T1	87998	1
T2	146096	5
T3	47041	1
T4	0	8
T5	0	2
T6	0	2
T9	0	18
T10	0	10
T11	0	9
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	2038
T1	418	1
T2	1082	5
T3	408	1
T4	0	8
T5	0	2
T6	0	2
T9	0	18
T10	0	10
T11	0	9
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T27,T5,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T5,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1937	0	0
SrcPulseCheck_M	1088100268	2035	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1937
T2	1082	1
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	13
T10	0	12
T11	0	15
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	2035
T1	87998	2
T2	146096	1
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T9	0	13
T10	0	12
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T27,T5,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T5,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	2012	0	0
SrcPulseCheck_M	8478194	2012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	2012
T1	87998	1
T2	146096	1
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T9	0	13
T10	0	12
T11	0	15
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	2012
T1	418	1
T2	1082	1
T3	408	1
T4	0	10
T5	0	2
T6	0	2
T9	0	13
T10	0	12
T11	0	15
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	2009	0	0
SrcPulseCheck_M	1088100268	2103	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	2009
T2	1082	6
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	10
T10	0	6
T11	0	15
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	2103
T1	87998	2
T2	146096	6
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	10
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	2076	0	0
SrcPulseCheck_M	8478194	2076	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	2076
T1	87998	1
T2	146096	6
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T9	0	10
T10	0	6
T11	0	15
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	2076
T1	418	1
T2	1082	6
T3	408	1
T4	0	10
T5	0	2
T6	0	2
T9	0	10
T10	0	6
T11	0	15
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T27
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1977	0	0
SrcPulseCheck_M	1088100268	2069	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1977
T2	1082	6
T3	408	0
T4	4467	9
T5	0	2
T6	0	2
T9	0	2
T10	0	16
T11	0	9
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0
T40	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	2069
T1	87998	2
T2	146096	6
T3	47041	0
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	2
T10	0	16
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T27
1	0	Covered	T2,T27,T4
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T27
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	2042	0	0
SrcPulseCheck_M	8478194	2042	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	2042
T1	87998	1
T2	146096	6
T3	47041	0
T4	0	10
T5	0	2
T6	0	2
T9	0	2
T10	0	16
T11	0	9
T12	0	2
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	2042
T1	418	1
T2	1082	6
T3	408	0
T4	0	10
T5	0	2
T6	0	2
T9	0	2
T10	0	16
T11	0	9
T12	0	2
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1970	0	0
SrcPulseCheck_M	1088100268	2066	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1970
T2	1082	13
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	8
T10	0	22
T11	0	13
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	2066
T1	87998	2
T2	146096	13
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	8
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	2039	0	0
SrcPulseCheck_M	8478194	2039	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	2039
T1	87998	1
T2	146096	13
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T9	0	8
T10	0	22
T11	0	13
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	2039
T1	418	1
T2	1082	13
T3	408	1
T4	0	10
T5	0	2
T6	0	2
T9	0	8
T10	0	22
T11	0	13
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1972	0	0
SrcPulseCheck_M	1088100268	2064	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1972
T2	1082	2
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	3
T10	0	19
T11	0	9
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0
T39	407	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	2064
T1	87998	2
T2	146096	2
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	3
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T27
1	1	Covered	T2,T27,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T27,T5
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1088100268	2037	0	0
SrcPulseCheck_M	8478194	2037	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1088100268	2037
T1	87998	1
T2	146096	2
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T9	0	3
T10	0	19
T11	0	9
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	128
T28	50910	0
T29	101442	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8478194	2037
T1	418	1
T2	1082	2
T3	408	1
T4	0	10
T5	0	2
T6	0	2
T9	0	3
T10	0	19
T11	0	9
T23	404	0
T24	405	0
T25	402	0
T26	402	0
T27	15000	128
T28	407	0
T29	811	0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T8,T1,T2
1	0	Covered	T8,T1,T2
1	1	Covered	T2,T5,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	1002	0	0
SrcPulseCheck_M	1088100268	1093	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	1002
T2	1082	3
T3	408	1
T4	4467	9
T5	0	2
T6	0	2
T9	0	13
T10	0	16
T11	0	13
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	0
T28	407	0
T29	811	0
T39	407	0
T40	0	19

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	1093
T1	87998	2
T2	146096	3
T3	47041	1
T4	0	10
T5	0	2
T6	0	2
T8	58415	1
T9	0	13
T10	0	16
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	0
T28	50910	0
T49	0	2

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T1
0	Covered	T7,T8,T1

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8478194	647	0	0
SrcPulseCheck_M	1088100268	739	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8478194	647
T2	1082	12
T3	408	1
T4	4467	8
T5	0	2
T6	0	2
T9	0	17
T10	0	3
T11	0	16
T12	0	2
T24	405	0
T25	402	0
T26	402	0
T27	15000	0
T28	407	0
T29	811	0
T39	407	0
T40	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1088100268	739
T1	87998	2
T2	146096	12
T3	47041	1
T4	0	8
T5	0	2
T6	0	2
T9	0	17
T10	0	3
T23	99191	0
T24	99164	0
T25	199262	0
T26	192958	0
T27	187506	0
T28	50910	0
T29	101442	1
T49	0	2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc