Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T38,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T78,T88,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T78,T15,T88

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T78,T88,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T78,T15,T88
1	0	Covered	T38,T39,T40
1	1	Covered	T78,T15,T88

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T78,T88,T41
0	1	Covered	T54,T108,T109
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T78,T88,T41
0	1	Covered	T78,T88,T41
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T78,T88,T41
1	-	Covered	T78,T88,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T78,T88,T41
0	1	Covered	T78,T15,T88
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T78,T88,T41
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T78,T15,T88
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T78,T88,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T44,T121
DebounceSt	-	0	0	-	-	-	-	Covered	T78,T15,T88
DetectSt	-	-	-	-	1	-	-	Covered	T54,T108,T109
DetectSt	-	-	-	-	0	1	-	Covered	T78,T88,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T78,T88,T41
StableSt	-	-	-	-	-	-	0	Covered	T78,T88,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	265	0	0
CntIncr_A	7290145	72649	0	0
CntNoWrap_A	7290145	6635764	0	0
DetectStDropOut_A	7290145	3	0	0
DetectedOut_A	7290145	842	0	0
DetectedPulseOut_A	7290145	121	0	0
DisabledIdleSt_A	7290145	6556834	0	0
DisabledNoDetection_A	7290145	6559181	0	0
EnterDebounceSt_A	7290145	146	0	0
EnterDetectSt_A	7290145	124	0	0
EnterStableSt_A	7290145	121	0	0
PulseIsPulse_A	7290145	121	0	0
StayInStableSt	7290145	721	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7290145	6983	0	0
gen_low_level_sva.LowLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	121	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	265	0	0
T14	26284	0	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T41	0	2	0	0
T42	0	5	0	0
T44	0	7	0	0
T53	0	2	0	0
T54	0	10	0	0
T78	681	4	0	0
T88	0	2	0	0
T90	0	6	0	0
T91	0	2	0	0
T92	0	4	0	0
T93	526	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	72649	0	0
T14	26284	0	0	0
T15	22719	2111	0	0
T16	26814	0	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T41	0	71	0	0
T42	0	139	0	0
T44	0	252	0	0
T53	0	74	0	0
T54	0	13986	0	0
T78	681	143	0	0
T88	0	28	0	0
T90	0	105	0	0
T91	0	65	0	0
T93	526	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635764	0	0
T14	26284	25826	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	276	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	3	0	0
T54	71313	1	0	0
T55	3168	0	0	0
T92	2246	0	0	0
T108	0	1	0	0
T109	0	1	0	0
T111	21167	0	0	0
T112	1807	0	0	0
T113	403	0	0	0
T114	526	0	0	0
T115	522	0	0	0
T116	501	0	0	0
T117	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	842	0	0
T14	26284	0	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T41	0	11	0	0
T42	0	6	0	0
T44	0	16	0	0
T53	0	6	0	0
T54	0	19	0	0
T78	681	12	0	0
T88	0	7	0	0
T90	0	24	0	0
T91	0	10	0	0
T92	0	22	0	0
T93	526	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	121	0	0
T14	26284	0	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	3	0	0
T53	0	1	0	0
T54	0	4	0	0
T78	681	2	0	0
T88	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	526	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6556834	0	0
T14	26284	25826	0	0
T15	22719	10405	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	55	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6559181	0	0
T14	26284	25835	0	0
T15	22719	10437	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	56	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	146	0	0
T14	26284	0	0	0
T15	22719	1	0	0
T16	26814	0	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T41	0	1	0	0
T42	0	3	0	0
T44	0	4	0	0
T53	0	1	0	0
T54	0	6	0	0
T78	681	2	0	0
T88	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T93	526	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	124	0	0
T14	26284	0	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	3	0	0
T53	0	1	0	0
T54	0	5	0	0
T78	681	2	0	0
T88	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	526	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	121	0	0
T14	26284	0	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	3	0	0
T53	0	1	0	0
T54	0	4	0	0
T78	681	2	0	0
T88	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	526	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	121	0	0
T14	26284	0	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	3	0	0
T53	0	1	0	0
T54	0	4	0	0
T78	681	2	0	0
T88	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	526	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	721	0	0
T14	26284	0	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T41	0	10	0	0
T42	0	4	0	0
T44	0	13	0	0
T53	0	5	0	0
T54	0	15	0	0
T78	681	10	0	0
T88	0	6	0	0
T90	0	21	0	0
T91	0	9	0	0
T92	0	20	0	0
T93	526	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6983	0	0
T14	26284	26	0	0
T15	22719	80	0	0
T27	406	0	0	0
T28	713	3	0	0
T29	0	8	0	0
T38	423	3	0	0
T39	422	1	0	0
T40	502	7	0	0
T78	681	3	0	0
T93	526	2	0	0
T94	502	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	121	0	0
T14	26284	0	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	3	0	0
T53	0	1	0	0
T54	0	4	0	0
T78	681	2	0	0
T88	0	1	0	0
T90	0	3	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	526	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T38,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T41,T42,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T41,T42,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T41,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T38,T39,T40
1	1	Covered	T41,T42,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T41,T42,T43
0	1	Covered	T85,T86,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T42,T43
0	1	Unreachable
1	0	Covered	T41,T42,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T41,T42,T43
0	1	Covered	T41,T42,T43
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T41,T42,T43
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T41,T42,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T45,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T41,T42,T43
DetectSt	-	-	-	-	1	-	-	Covered	T85,T86,T87
DetectSt	-	-	-	-	0	1	-	Covered	T41,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T42,T43
StableSt	-	-	-	-	-	-	0	Covered	T41,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	168	0	0
CntIncr_A	7290145	52439	0	0
CntNoWrap_A	7290145	6635861	0	0
DetectStDropOut_A	7290145	8	0	0
DetectedOut_A	7290145	17286	0	0
DetectedPulseOut_A	7290145	46	0	0
DisabledIdleSt_A	7290145	5482481	0	0
DisabledNoDetection_A	7290145	5484876	0	0
EnterDebounceSt_A	7290145	115	0	0
EnterDetectSt_A	7290145	54	0	0
EnterStableSt_A	7290145	46	0	0
PulseIsPulse_A	7290145	46	0	0
StayInStableSt	7290145	17240	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7290145	6983	0	0
gen_low_level_sva.LowLevelEvent_A	7290145	6638427	0	0
gen_sticky_sva.StableStDropOut_A	7290145	892861	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	168	0	0
T41	74252	8	0	0
T42	12699	2	0	0
T43	0	2	0	0
T45	0	2	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	2	0	0
T55	0	2	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	4	0	0
T65	0	2	0	0
T66	0	2	0	0
T68	23449	0	0	0
T83	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	52439	0	0
T41	74252	481	0	0
T42	12699	87	0	0
T43	0	61	0	0
T45	0	42	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	67	0	0
T55	0	99	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	132	0	0
T65	0	41	0	0
T66	0	46	0	0
T68	23449	0	0	0
T83	0	224	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635861	0	0
T14	26284	25826	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	8	0	0
T85	878	1	0	0
T86	273139	1	0	0
T87	0	2	0	0
T122	0	2	0	0
T123	0	2	0	0
T124	2766	0	0	0
T125	4670	0	0	0
T126	534	0	0	0
T127	37498	0	0	0
T128	230882	0	0	0
T129	502	0	0	0
T130	638	0	0	0
T131	772	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	17286	0	0
T41	74252	141	0	0
T42	12699	527	0	0
T43	0	277	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	512	0	0
T55	0	556	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	408	0	0
T65	0	83	0	0
T66	0	80	0	0
T67	0	420	0	0
T68	23449	0	0	0
T119	0	393	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	46	0	0
T41	74252	2	0	0
T42	12699	1	0	0
T43	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	23449	0	0	0
T119	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	5482481	0	0
T14	26284	25826	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	5484876	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	115	0	0
T41	74252	6	0	0
T42	12699	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T68	23449	0	0	0
T83	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	54	0	0
T41	74252	2	0	0
T42	12699	1	0	0
T43	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	23449	0	0	0
T119	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	46	0	0
T41	74252	2	0	0
T42	12699	1	0	0
T43	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	23449	0	0	0
T119	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	46	0	0
T41	74252	2	0	0
T42	12699	1	0	0
T43	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	23449	0	0	0
T119	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	17240	0	0
T41	74252	139	0	0
T42	12699	526	0	0
T43	0	276	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	511	0	0
T55	0	555	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	406	0	0
T65	0	82	0	0
T66	0	79	0	0
T67	0	419	0	0
T68	23449	0	0	0
T119	0	392	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6983	0	0
T14	26284	26	0	0
T15	22719	80	0	0
T27	406	0	0	0
T28	713	3	0	0
T29	0	8	0	0
T38	423	3	0	0
T39	422	1	0	0
T40	502	7	0	0
T78	681	3	0	0
T93	526	2	0	0
T94	502	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	892861	0	0
T41	74252	115	0	0
T42	12699	83	0	0
T43	0	65	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	205	0	0
T55	0	124	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	234	0	0
T65	0	235	0	0
T66	0	135	0	0
T67	0	208592	0	0
T68	23449	0	0	0
T119	0	108	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T38,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T41,T42,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T41,T42,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T41,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T38,T39,T40
1	1	Covered	T41,T42,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T41,T42,T43
0	1	Covered	T41,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T42,T43
0	1	Unreachable
1	0	Covered	T41,T42,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T41,T42,T43
0	1	Covered	T41,T42,T43
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T41,T42,T43
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T41,T42,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T53,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T41,T42,T43
DetectSt	-	-	-	-	1	-	-	Covered	T41,T83,T84
DetectSt	-	-	-	-	0	1	-	Covered	T41,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T42,T43
StableSt	-	-	-	-	-	-	0	Covered	T41,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	186	0	0
CntIncr_A	7290145	59044	0	0
CntNoWrap_A	7290145	6635843	0	0
DetectStDropOut_A	7290145	18	0	0
DetectedOut_A	7290145	22823	0	0
DetectedPulseOut_A	7290145	46	0	0
DisabledIdleSt_A	7290145	5482481	0	0
DisabledNoDetection_A	7290145	5484876	0	0
EnterDebounceSt_A	7290145	123	0	0
EnterDetectSt_A	7290145	64	0	0
EnterStableSt_A	7290145	46	0	0
PulseIsPulse_A	7290145	46	0	0
StayInStableSt	7290145	22777	0	0
gen_high_level_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_sticky_sva.StableStDropOut_A	7290145	719827	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	186	0	0
T41	74252	11	0	0
T42	12699	2	0	0
T43	0	2	0	0
T45	0	2	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	5	0	0
T55	0	2	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	4	0	0
T65	0	2	0	0
T66	0	2	0	0
T68	23449	0	0	0
T83	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	59044	0	0
T41	74252	43637	0	0
T42	12699	75	0	0
T43	0	53	0	0
T45	0	91	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	295	0	0
T55	0	20	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	124	0	0
T65	0	92	0	0
T66	0	74	0	0
T68	23449	0	0	0
T83	0	384	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635843	0	0
T14	26284	25826	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	18	0	0
T41	74252	2	0	0
T48	32768	0	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T83	18600	2	0	0
T84	0	2	0	0
T120	0	3	0	0
T132	0	1	0	0
T133	0	3	0	0
T134	0	3	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	7328	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	22823	0	0
T41	74252	14523	0	0
T42	12699	494	0	0
T43	0	261	0	0
T45	0	166	0	0
T48	32768	0	0	0
T52	504	0	0	0
T55	0	91	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	477	0	0
T65	0	203	0	0
T66	0	137	0	0
T67	0	640	0	0
T68	23449	0	0	0
T118	0	509	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	46	0	0
T41	74252	3	0	0
T42	12699	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	23449	0	0	0
T118	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	5482481	0	0
T14	26284	25826	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	5484876	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	123	0	0
T41	74252	6	0	0
T42	12699	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	5	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T68	23449	0	0	0
T83	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	64	0	0
T41	74252	5	0	0
T42	12699	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	23449	0	0	0
T83	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	46	0	0
T41	74252	3	0	0
T42	12699	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	23449	0	0	0
T118	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	46	0	0
T41	74252	3	0	0
T42	12699	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	23449	0	0	0
T118	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	22777	0	0
T41	74252	14520	0	0
T42	12699	493	0	0
T43	0	260	0	0
T45	0	165	0	0
T48	32768	0	0	0
T52	504	0	0	0
T55	0	90	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	475	0	0
T65	0	202	0	0
T66	0	136	0	0
T67	0	639	0	0
T68	23449	0	0	0
T118	0	508	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	719827	0	0
T41	74252	217	0	0
T42	12699	142	0	0
T43	0	105	0	0
T45	0	89	0	0
T48	32768	0	0	0
T52	504	0	0	0
T55	0	665	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	162	0	0
T65	0	78	0	0
T66	0	57	0	0
T67	0	208363	0	0
T68	23449	0	0	0
T118	0	320	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T41,T42,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T41,T42,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T41,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T38,T39,T40
1	1	Covered	T41,T42,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T41,T42,T43
0	1	Covered	T45,T66,T67
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T42,T43
0	1	Unreachable
1	0	Covered	T41,T42,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T41,T42,T43
0	1	Covered	T41,T42,T43
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T41,T42,T43
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T41,T42,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T83,T65
DebounceSt	-	0	0	-	-	-	-	Covered	T41,T42,T43
DetectSt	-	-	-	-	1	-	-	Covered	T45,T66,T67
DetectSt	-	-	-	-	0	1	-	Covered	T41,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T42,T43
StableSt	-	-	-	-	-	-	0	Covered	T41,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	170	0	0
CntIncr_A	7290145	239676	0	0
CntNoWrap_A	7290145	6635859	0	0
DetectStDropOut_A	7290145	13	0	0
DetectedOut_A	7290145	781266	0	0
DetectedPulseOut_A	7290145	50	0	0
DisabledIdleSt_A	7290145	5482481	0	0
DisabledNoDetection_A	7290145	5484876	0	0
EnterDebounceSt_A	7290145	108	0	0
EnterDetectSt_A	7290145	63	0	0
EnterStableSt_A	7290145	50	0	0
PulseIsPulse_A	7290145	50	0	0
StayInStableSt	7290145	781216	0	0
gen_high_event_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_high_level_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_sticky_sva.StableStDropOut_A	7290145	128079	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	170	0	0
T41	74252	6	0	0
T42	12699	2	0	0
T43	0	2	0	0
T45	0	4	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	2	0	0
T55	0	5	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	4	0	0
T65	0	2	0	0
T66	0	3	0	0
T68	23449	0	0	0
T83	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	239676	0	0
T41	74252	172	0	0
T42	12699	88	0	0
T43	0	62	0	0
T45	0	98	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	37	0	0
T55	0	375	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	96	0	0
T65	0	70	0	0
T66	0	196	0	0
T68	23449	0	0	0
T83	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635859	0	0
T14	26284	25826	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	13	0	0
T45	41261	2	0	0
T66	7563	1	0	0
T67	251346	1	0	0
T91	753	0	0	0
T98	5271	0	0	0
T99	5668	0	0	0
T119	0	1	0	0
T135	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	5	0	0
T141	524	0	0	0
T142	592	0	0	0
T143	19105	0	0	0
T144	1572	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	781266	0	0
T41	74252	452	0	0
T42	12699	458	0	0
T43	0	127	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	222	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	342	0	0
T67	0	125420	0	0
T68	23449	0	0	0
T85	0	66	0	0
T103	0	28	0	0
T119	0	289	0	0
T120	0	567	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	50	0	0
T41	74252	3	0	0
T42	12699	1	0	0
T43	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T67	0	1	0	0
T68	23449	0	0	0
T85	0	1	0	0
T103	0	1	0	0
T119	0	1	0	0
T120	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	5482481	0	0
T14	26284	25826	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	5484876	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	108	0	0
T41	74252	3	0	0
T42	12699	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	1	0	0
T55	0	5	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T65	0	2	0	0
T66	0	2	0	0
T68	23449	0	0	0
T83	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	63	0	0
T41	74252	3	0	0
T42	12699	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	23449	0	0	0
T103	0	1	0	0
T119	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	50	0	0
T41	74252	3	0	0
T42	12699	1	0	0
T43	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T67	0	1	0	0
T68	23449	0	0	0
T85	0	1	0	0
T103	0	1	0	0
T119	0	1	0	0
T120	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	50	0	0
T41	74252	3	0	0
T42	12699	1	0	0
T43	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	2	0	0
T67	0	1	0	0
T68	23449	0	0	0
T85	0	1	0	0
T103	0	1	0	0
T119	0	1	0	0
T120	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	781216	0	0
T41	74252	449	0	0
T42	12699	457	0	0
T43	0	126	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	221	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	340	0	0
T67	0	125419	0	0
T68	23449	0	0	0
T85	0	65	0	0
T103	0	27	0	0
T119	0	288	0	0
T120	0	564	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	128079	0	0
T41	74252	57963	0	0
T42	12699	170	0	0
T43	0	235	0	0
T48	32768	0	0	0
T52	504	0	0	0
T53	0	529	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T64	0	358	0	0
T67	0	58	0	0
T68	23449	0	0	0
T85	0	187	0	0
T103	0	8736	0	0
T119	0	73	0	0
T120	0	35475	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T38,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T15,T41,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T15,T41,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T15,T41,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T19,T41
1	0	Covered	T38,T39,T40
1	1	Covered	T15,T41,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T41,T44
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T41,T44
0	1	Covered	T15,T44,T45
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T41,T44
1	-	Covered	T15,T44,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T41,T44
0	1	Covered	T15,T41,T44
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T41,T44
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T41,T44
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T41,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T145
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T41,T44
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T15,T41,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T44,T45
StableSt	-	-	-	-	-	-	0	Covered	T15,T41,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	85	0	0
CntIncr_A	7290145	2315	0	0
CntNoWrap_A	7290145	6635944	0	0
DetectStDropOut_A	7290145	0	0	0
DetectedOut_A	7290145	2445	0	0
DetectedPulseOut_A	7290145	41	0	0
DisabledIdleSt_A	7290145	6615023	0	0
DisabledNoDetection_A	7290145	6617359	0	0
EnterDebounceSt_A	7290145	44	0	0
EnterDetectSt_A	7290145	41	0	0
EnterStableSt_A	7290145	41	0	0
PulseIsPulse_A	7290145	41	0	0
StayInStableSt	7290145	2384	0	0
gen_high_level_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	85	0	0
T15	22719	2	0	0
T16	26814	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	6	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T74	0	1	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	2315	0	0
T15	22719	45	0	0
T16	26814	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	32	0	0
T44	0	42	0	0
T45	0	196	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T74	0	16	0	0
T146	0	55	0	0
T147	0	98	0	0
T148	0	21	0	0
T149	0	73	0	0
T150	0	184	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635944	0	0
T14	26284	25826	0	0
T15	22719	12526	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	2445	0	0
T15	22719	109	0	0
T16	26814	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	43	0	0
T44	0	33	0	0
T45	0	278	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	45	0	0
T147	0	59	0	0
T148	0	71	0	0
T149	0	43	0	0
T150	0	86	0	0
T151	0	33	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	41	0	0
T15	22719	1	0	0
T16	26814	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6615023	0	0
T14	26284	25826	0	0
T15	22719	12133	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6617359	0	0
T14	26284	25835	0	0
T15	22719	12165	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	44	0	0
T15	22719	1	0	0
T16	26814	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T74	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	41	0	0
T15	22719	1	0	0
T16	26814	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	41	0	0
T15	22719	1	0	0
T16	26814	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	41	0	0
T15	22719	1	0	0
T16	26814	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	3	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0
T151	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	2384	0	0
T15	22719	108	0	0
T16	26814	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	41	0	0
T44	0	32	0	0
T45	0	274	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	43	0	0
T147	0	57	0	0
T148	0	70	0	0
T149	0	42	0	0
T150	0	83	0	0
T151	0	32	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	21	0	0
T15	22719	1	0	0
T16	26814	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	1	0	0
T45	0	2	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T82	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T38,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T48,T44,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T48,T44,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T48,T44,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T48,T44,T45
1	0	Covered	T38,T39,T40
1	1	Covered	T48,T44,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T48,T44,T45
0	1	Covered	T152
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T48,T44,T45
0	1	Covered	T48,T44,T45
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T48,T44,T45
1	-	Covered	T48,T44,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T48,T44,T45
0	1	Covered	T48,T44,T45
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T48,T44,T45
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T48,T44,T45
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T48,T44,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T150
DebounceSt	-	0	0	-	-	-	-	Covered	T48,T44,T45
DetectSt	-	-	-	-	1	-	-	Covered	T152
DetectSt	-	-	-	-	0	1	-	Covered	T48,T44,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T48,T44,T45
StableSt	-	-	-	-	-	-	0	Covered	T48,T44,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	127	0	0
CntIncr_A	7290145	32133	0	0
CntNoWrap_A	7290145	6635902	0	0
DetectStDropOut_A	7290145	1	0	0
DetectedOut_A	7290145	5094	0	0
DetectedPulseOut_A	7290145	61	0	0
DisabledIdleSt_A	7290145	6558592	0	0
DisabledNoDetection_A	7290145	6560940	0	0
EnterDebounceSt_A	7290145	65	0	0
EnterDetectSt_A	7290145	62	0	0
EnterStableSt_A	7290145	61	0	0
PulseIsPulse_A	7290145	61	0	0
StayInStableSt	7290145	5004	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7290145	2544	0	0
gen_low_level_sva.LowLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	127	0	0
T43	859	0	0	0
T44	19144	4	0	0
T45	0	6	0	0
T46	0	4	0	0
T48	32768	2	0	0
T52	504	0	0	0
T54	0	2	0	0
T55	0	2	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T74	0	1	0	0
T146	0	2	0	0
T147	0	2	0	0
T154	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	32133	0	0
T43	859	0	0	0
T44	19144	194	0	0
T45	0	228	0	0
T46	0	36	0	0
T48	32768	84	0	0
T52	504	0	0	0
T54	0	79	0	0
T55	0	13	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T74	0	17	0	0
T146	0	55	0	0
T147	0	98	0	0
T154	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635902	0	0
T14	26284	25826	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	1	0	0
T152	584	1	0	0
T155	1305	0	0	0
T156	428	0	0	0
T157	426	0	0	0
T158	492	0	0	0
T159	21462	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	5094	0	0
T43	859	0	0	0
T44	19144	188	0	0
T45	0	377	0	0
T46	0	111	0	0
T47	0	42	0	0
T48	32768	127	0	0
T52	504	0	0	0
T54	0	44	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T146	0	7	0	0
T147	0	17	0	0
T154	0	111	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	61	0	0
T43	859	0	0	0
T44	19144	2	0	0
T45	0	3	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	32768	1	0	0
T52	504	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T154	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6558592	0	0
T14	26284	25826	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6560940	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	65	0	0
T43	859	0	0	0
T44	19144	2	0	0
T45	0	3	0	0
T46	0	2	0	0
T48	32768	1	0	0
T52	504	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T74	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T154	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	62	0	0
T43	859	0	0	0
T44	19144	2	0	0
T45	0	3	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	32768	1	0	0
T52	504	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T154	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	61	0	0
T43	859	0	0	0
T44	19144	2	0	0
T45	0	3	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	32768	1	0	0
T52	504	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T154	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	61	0	0
T43	859	0	0	0
T44	19144	2	0	0
T45	0	3	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	32768	1	0	0
T52	504	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T154	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	5004	0	0
T43	859	0	0	0
T44	19144	185	0	0
T45	0	373	0	0
T46	0	109	0	0
T47	0	40	0	0
T48	32768	126	0	0
T52	504	0	0	0
T54	0	42	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T146	0	6	0	0
T147	0	16	0	0
T148	0	52	0	0
T154	0	109	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	2544	0	0
T14	26284	0	0	0
T15	22719	60	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	0	4	0	0
T30	0	6	0	0
T31	0	3	0	0
T33	0	4	0	0
T38	423	3	0	0
T39	422	2	0	0
T40	502	5	0	0
T78	681	0	0	0
T93	526	6	0	0
T94	502	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	32	0	0
T43	859	0	0	0
T44	19144	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	32768	1	0	0
T52	504	0	0	0
T55	0	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T150	0	1	0	0
T160	0	1	0	0