Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T38,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T15,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T15,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T15,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T19,T20
1	0	Covered	T38,T39,T40
1	1	Covered	T15,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T19,T20
0	1	Covered	T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T19,T20
0	1	Covered	T15,T19,T20
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T19,T20
1	-	Covered	T15,T19,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T19,T20
0	1	Covered	T15,T19,T20
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T19,T20
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T19,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T21,T52
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T82
DetectSt	-	-	-	-	0	1	-	Covered	T15,T19,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T19,T20
StableSt	-	-	-	-	-	-	0	Covered	T15,T19,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	130	0	0
CntIncr_A	7290145	32504	0	0
CntNoWrap_A	7290145	6635899	0	0
DetectStDropOut_A	7290145	1	0	0
DetectedOut_A	7290145	4585	0	0
DetectedPulseOut_A	7290145	60	0	0
DisabledIdleSt_A	7290145	6555687	0	0
DisabledNoDetection_A	7290145	6558034	0	0
EnterDebounceSt_A	7290145	69	0	0
EnterDetectSt_A	7290145	61	0	0
EnterStableSt_A	7290145	60	0	0
PulseIsPulse_A	7290145	60	0	0
StayInStableSt	7290145	4503	0	0
gen_high_level_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	130	0	0
T15	22719	3	0	0
T16	26814	0	0	0
T19	0	4	0	0
T20	0	2	0	0
T21	0	3	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	2	0	0
T47	0	2	0	0
T52	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T74	0	1	0	0
T146	0	2	0	0
T154	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	32504	0	0
T15	22719	90	0	0
T16	26814	0	0	0
T19	0	142	0	0
T20	0	83	0	0
T21	0	118	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	92	0	0
T47	0	39	0	0
T52	0	49	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T74	0	17	0	0
T146	0	55	0	0
T154	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635899	0	0
T14	26284	25826	0	0
T15	22719	12525	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	1	0	0
T82	605	1	0	0
T165	861	0	0	0
T177	946	0	0	0
T193	549	0	0	0
T194	1061	0	0	0
T195	407	0	0	0
T196	639	0	0	0
T197	437	0	0	0
T198	24557	0	0	0
T199	5283	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	4585	0	0
T15	22719	11	0	0
T16	26814	0	0	0
T19	0	73	0	0
T20	0	228	0	0
T21	0	41	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	147	0	0
T47	0	70	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	109	0	0
T148	0	10	0	0
T154	0	39	0	0
T160	0	117	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	60	0	0
T15	22719	1	0	0
T16	26814	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T154	0	1	0	0
T160	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6555687	0	0
T14	26284	25826	0	0
T15	22719	12133	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6558034	0	0
T14	26284	25835	0	0
T15	22719	12165	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	69	0	0
T15	22719	2	0	0
T16	26814	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T21	0	2	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T74	0	1	0	0
T146	0	1	0	0
T154	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	61	0	0
T15	22719	1	0	0
T16	26814	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T154	0	1	0	0
T160	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	60	0	0
T15	22719	1	0	0
T16	26814	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T154	0	1	0	0
T160	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	60	0	0
T15	22719	1	0	0
T16	26814	0	0	0
T19	0	2	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T154	0	1	0	0
T160	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	4503	0	0
T15	22719	10	0	0
T16	26814	0	0	0
T19	0	70	0	0
T20	0	227	0	0
T21	0	40	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	145	0	0
T47	0	69	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	107	0	0
T148	0	9	0	0
T154	0	37	0	0
T160	0	114	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	38	0	0
T15	22719	1	0	0
T16	26814	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T148	0	1	0	0
T149	0	2	0	0
T160	0	1	0	0
T164	0	2	0	0
T169	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T38,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T15,T19,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T15,T19,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T15,T19,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T19,T21
1	0	Covered	T38,T39,T40
1	1	Covered	T15,T19,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T19,T21
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T19,T21
0	1	Covered	T15,T21,T45
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T19,T21
1	-	Covered	T15,T21,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T19,T21
0	1	Covered	T15,T19,T21
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T19,T21
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T19,T21
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T19,T21
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T19,T21
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T15,T19,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T21,T45
StableSt	-	-	-	-	-	-	0	Covered	T15,T19,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	76	0	0
CntIncr_A	7290145	37858	0	0
CntNoWrap_A	7290145	6635953	0	0
DetectStDropOut_A	7290145	0	0	0
DetectedOut_A	7290145	3080	0	0
DetectedPulseOut_A	7290145	37	0	0
DisabledIdleSt_A	7290145	6483733	0	0
DisabledNoDetection_A	7290145	6486081	0	0
EnterDebounceSt_A	7290145	39	0	0
EnterDetectSt_A	7290145	37	0	0
EnterStableSt_A	7290145	37	0	0
PulseIsPulse_A	7290145	37	0	0
StayInStableSt	7290145	3025	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7290145	6279	0	0
gen_low_level_sva.LowLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	76	0	0
T15	22719	6	0	0
T16	26814	0	0	0
T19	0	2	0	0
T21	0	4	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T74	0	1	0	0
T148	0	2	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	37858	0	0
T15	22719	144	0	0
T16	26814	0	0	0
T19	0	47	0	0
T21	0	118	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	97	0	0
T45	0	82	0	0
T46	0	18	0	0
T47	0	39	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T74	0	18	0	0
T148	0	21	0	0
T169	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635953	0	0
T14	26284	25826	0	0
T15	22719	12522	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	3080	0	0
T15	22719	453	0	0
T16	26814	0	0	0
T19	0	40	0	0
T21	0	291	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	163	0	0
T45	0	353	0	0
T46	0	39	0	0
T47	0	80	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T148	0	44	0	0
T169	0	1	0	0
T200	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	37	0	0
T15	22719	3	0	0
T16	26814	0	0	0
T19	0	1	0	0
T21	0	2	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T148	0	1	0	0
T169	0	1	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6483733	0	0
T14	26284	25826	0	0
T15	22719	11758	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6486081	0	0
T14	26284	25835	0	0
T15	22719	11789	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	39	0	0
T15	22719	3	0	0
T16	26814	0	0	0
T19	0	1	0	0
T21	0	2	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T74	0	1	0	0
T148	0	1	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	37	0	0
T15	22719	3	0	0
T16	26814	0	0	0
T19	0	1	0	0
T21	0	2	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T148	0	1	0	0
T169	0	1	0	0
T200	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	37	0	0
T15	22719	3	0	0
T16	26814	0	0	0
T19	0	1	0	0
T21	0	2	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T148	0	1	0	0
T169	0	1	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	37	0	0
T15	22719	3	0	0
T16	26814	0	0	0
T19	0	1	0	0
T21	0	2	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T148	0	1	0	0
T169	0	1	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	3025	0	0
T15	22719	448	0	0
T16	26814	0	0	0
T19	0	38	0	0
T21	0	288	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T44	0	161	0	0
T45	0	352	0	0
T46	0	38	0	0
T47	0	78	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T82	0	120	0	0
T148	0	42	0	0
T200	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6279	0	0
T14	26284	29	0	0
T15	22719	64	0	0
T16	0	12	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	0	6	0	0
T30	0	5	0	0
T38	423	3	0	0
T39	422	3	0	0
T40	502	5	0	0
T78	681	0	0	0
T93	526	5	0	0
T94	502	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	19	0	0
T15	22719	1	0	0
T16	26814	0	0	0
T21	0	1	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T82	0	2	0	0
T169	0	1	0	0
T171	0	2	0	0
T201	0	1	0	0
T202	0	2	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T38,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T19,T21,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T19,T21,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T19,T21,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T21,T41
1	0	Covered	T38,T39,T40
1	1	Covered	T19,T21,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T41
0	1	Covered	T41,T192,T171
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T21,T41
0	1	Covered	T21,T41,T48
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T21,T41
1	-	Covered	T21,T41,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T21,T41
0	1	Covered	T19,T21,T41
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T21,T41
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T21,T41
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T21,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T204,T205
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T21,T41
DetectSt	-	-	-	-	1	-	-	Covered	T41,T192,T171
DetectSt	-	-	-	-	0	1	-	Covered	T19,T21,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T41,T48
StableSt	-	-	-	-	-	-	0	Covered	T19,T21,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	139	0	0
CntIncr_A	7290145	88645	0	0
CntNoWrap_A	7290145	6635890	0	0
DetectStDropOut_A	7290145	4	0	0
DetectedOut_A	7290145	16227	0	0
DetectedPulseOut_A	7290145	63	0	0
DisabledIdleSt_A	7290145	6250550	0	0
DisabledNoDetection_A	7290145	6252885	0	0
EnterDebounceSt_A	7290145	72	0	0
EnterDetectSt_A	7290145	67	0	0
EnterStableSt_A	7290145	63	0	0
PulseIsPulse_A	7290145	63	0	0
StayInStableSt	7290145	16134	0	0
gen_high_level_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	139	0	0
T19	2622	4	0	0
T20	849	0	0	0
T21	3405	4	0	0
T22	38814	0	0	0
T41	74252	4	0	0
T44	0	4	0	0
T45	0	10	0	0
T46	0	6	0	0
T48	32768	4	0	0
T52	0	2	0	0
T74	0	1	0	0
T88	736	0	0	0
T146	0	2	0	0
T206	402	0	0	0
T207	505	0	0	0
T208	517	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	88645	0	0
T19	2622	142	0	0
T20	849	0	0	0
T21	3405	118	0	0
T22	38814	0	0	0
T41	74252	64	0	0
T44	0	189	0	0
T45	0	324	0	0
T46	0	54	0	0
T48	32768	168	0	0
T52	0	49	0	0
T74	0	16	0	0
T88	736	0	0	0
T146	0	55	0	0
T206	402	0	0	0
T207	505	0	0	0
T208	517	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635890	0	0
T14	26284	25826	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	4	0	0
T41	74252	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T171	960	1	0	0
T192	7951	1	0	0
T209	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	16227	0	0
T19	2622	77	0	0
T20	849	0	0	0
T21	3405	276	0	0
T22	38814	0	0	0
T41	74252	104	0	0
T44	0	452	0	0
T45	0	205	0	0
T46	0	88	0	0
T47	0	39	0	0
T48	32768	83	0	0
T52	0	45	0	0
T88	736	0	0	0
T146	0	46	0	0
T206	402	0	0	0
T207	505	0	0	0
T208	517	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	63	0	0
T19	2622	2	0	0
T20	849	0	0	0
T21	3405	2	0	0
T22	38814	0	0	0
T41	74252	1	0	0
T44	0	2	0	0
T45	0	5	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	32768	2	0	0
T52	0	1	0	0
T88	736	0	0	0
T146	0	1	0	0
T206	402	0	0	0
T207	505	0	0	0
T208	517	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6250550	0	0
T14	26284	25826	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6252885	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	72	0	0
T19	2622	2	0	0
T20	849	0	0	0
T21	3405	2	0	0
T22	38814	0	0	0
T41	74252	2	0	0
T44	0	2	0	0
T45	0	5	0	0
T46	0	3	0	0
T48	32768	2	0	0
T52	0	1	0	0
T74	0	1	0	0
T88	736	0	0	0
T146	0	1	0	0
T206	402	0	0	0
T207	505	0	0	0
T208	517	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	67	0	0
T19	2622	2	0	0
T20	849	0	0	0
T21	3405	2	0	0
T22	38814	0	0	0
T41	74252	2	0	0
T44	0	2	0	0
T45	0	5	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	32768	2	0	0
T52	0	1	0	0
T88	736	0	0	0
T146	0	1	0	0
T206	402	0	0	0
T207	505	0	0	0
T208	517	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	63	0	0
T19	2622	2	0	0
T20	849	0	0	0
T21	3405	2	0	0
T22	38814	0	0	0
T41	74252	1	0	0
T44	0	2	0	0
T45	0	5	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	32768	2	0	0
T52	0	1	0	0
T88	736	0	0	0
T146	0	1	0	0
T206	402	0	0	0
T207	505	0	0	0
T208	517	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	63	0	0
T19	2622	2	0	0
T20	849	0	0	0
T21	3405	2	0	0
T22	38814	0	0	0
T41	74252	1	0	0
T44	0	2	0	0
T45	0	5	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	32768	2	0	0
T52	0	1	0	0
T88	736	0	0	0
T146	0	1	0	0
T206	402	0	0	0
T207	505	0	0	0
T208	517	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	16134	0	0
T19	2622	73	0	0
T20	849	0	0	0
T21	3405	273	0	0
T22	38814	0	0	0
T41	74252	103	0	0
T44	0	448	0	0
T45	0	199	0	0
T46	0	84	0	0
T47	0	38	0	0
T48	32768	80	0	0
T52	0	43	0	0
T88	736	0	0	0
T146	0	44	0	0
T206	402	0	0	0
T207	505	0	0	0
T208	517	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	33	0	0
T21	3405	1	0	0
T22	38814	0	0	0
T41	74252	1	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	32768	1	0	0
T59	1424	0	0	0
T60	497	0	0	0
T88	736	0	0	0
T149	0	1	0	0
T160	0	1	0	0
T177	0	1	0	0
T182	0	1	0	0
T206	402	0	0	0
T207	505	0	0	0
T208	517	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T38,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T48,T45,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T48,T45,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T48,T45,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T19,T48
1	0	Covered	T38,T39,T40
1	1	Covered	T48,T45,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T47
0	1	Covered	T48
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T47
0	1	Covered	T46,T153,T178
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T46,T47
1	-	Covered	T46,T153,T178

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T48,T45,T46
0	1	Covered	T48,T45,T46
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T48,T45,T46
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T48,T45,T46
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T48,T45,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T169
DebounceSt	-	0	0	-	-	-	-	Covered	T48,T45,T46
DetectSt	-	-	-	-	1	-	-	Covered	T48
DetectSt	-	-	-	-	0	1	-	Covered	T45,T46,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T46,T153,T178
StableSt	-	-	-	-	-	-	0	Covered	T45,T46,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	79	0	0
CntIncr_A	7290145	86981	0	0
CntNoWrap_A	7290145	6635950	0	0
DetectStDropOut_A	7290145	1	0	0
DetectedOut_A	7290145	2563	0	0
DetectedPulseOut_A	7290145	37	0	0
DisabledIdleSt_A	7290145	6321370	0	0
DisabledNoDetection_A	7290145	6323712	0	0
EnterDebounceSt_A	7290145	41	0	0
EnterDetectSt_A	7290145	38	0	0
EnterStableSt_A	7290145	37	0	0
PulseIsPulse_A	7290145	37	0	0
StayInStableSt	7290145	2502	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7290145	6219	0	0
gen_low_level_sva.LowLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	79	0	0
T45	41261	2	0	0
T46	0	4	0	0
T47	0	2	0	0
T48	32768	2	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T74	0	1	0	0
T91	753	0	0	0
T141	524	0	0	0
T150	0	2	0	0
T169	0	1	0	0
T177	0	2	0	0
T210	0	2	0	0
T211	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	86981	0	0
T45	41261	32	0	0
T46	0	36	0	0
T47	0	39	0	0
T48	32768	84	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T74	0	18	0	0
T91	753	0	0	0
T141	524	0	0	0
T150	0	92	0	0
T169	0	92	0	0
T177	0	88	0	0
T210	0	94	0	0
T211	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635950	0	0
T14	26284	25826	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	1	0	0
T48	32768	1	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	2563	0	0
T45	41261	116	0	0
T46	675	84	0	0
T47	0	80	0	0
T74	6472	0	0	0
T77	36164	0	0	0
T91	753	0	0	0
T141	524	0	0	0
T142	592	0	0	0
T150	0	252	0	0
T153	0	1	0	0
T172	0	43	0	0
T177	0	42	0	0
T178	0	104	0	0
T210	0	40	0	0
T211	0	40	0	0
T212	502	0	0	0
T213	402	0	0	0
T214	266099	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	37	0	0
T45	41261	1	0	0
T46	675	2	0	0
T47	0	1	0	0
T74	6472	0	0	0
T77	36164	0	0	0
T91	753	0	0	0
T141	524	0	0	0
T142	592	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T172	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	502	0	0	0
T213	402	0	0	0
T214	266099	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6321370	0	0
T14	26284	25826	0	0
T15	22719	12133	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6323712	0	0
T14	26284	25835	0	0
T15	22719	12165	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	41	0	0
T45	41261	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	32768	1	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T74	0	1	0	0
T91	753	0	0	0
T141	524	0	0	0
T150	0	1	0	0
T169	0	1	0	0
T177	0	1	0	0
T210	0	1	0	0
T211	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	38	0	0
T45	41261	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	32768	1	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T91	753	0	0	0
T141	524	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T172	0	1	0	0
T177	0	1	0	0
T210	0	1	0	0
T211	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	37	0	0
T45	41261	1	0	0
T46	675	2	0	0
T47	0	1	0	0
T74	6472	0	0	0
T77	36164	0	0	0
T91	753	0	0	0
T141	524	0	0	0
T142	592	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T172	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	502	0	0	0
T213	402	0	0	0
T214	266099	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	37	0	0
T45	41261	1	0	0
T46	675	2	0	0
T47	0	1	0	0
T74	6472	0	0	0
T77	36164	0	0	0
T91	753	0	0	0
T141	524	0	0	0
T142	592	0	0	0
T150	0	1	0	0
T153	0	1	0	0
T172	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	502	0	0	0
T213	402	0	0	0
T214	266099	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	2502	0	0
T45	41261	114	0	0
T46	675	82	0	0
T47	0	78	0	0
T74	6472	0	0	0
T77	36164	0	0	0
T91	753	0	0	0
T141	524	0	0	0
T142	592	0	0	0
T150	0	250	0	0
T172	0	41	0	0
T177	0	40	0	0
T178	0	101	0	0
T210	0	38	0	0
T211	0	38	0	0
T212	502	0	0	0
T213	402	0	0	0
T214	266099	0	0	0
T215	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6219	0	0
T14	26284	26	0	0
T15	22719	80	0	0
T16	0	10	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	0	6	0	0
T30	0	4	0	0
T38	423	3	0	0
T39	422	2	0	0
T40	502	6	0	0
T78	681	0	0	0
T93	526	6	0	0
T94	502	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	13	0	0
T46	675	2	0	0
T74	6472	0	0	0
T77	36164	0	0	0
T145	0	1	0	0
T147	683	0	0	0
T153	0	1	0	0
T178	0	1	0	0
T183	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T203	0	1	0	0
T205	0	2	0	0
T212	502	0	0	0
T213	402	0	0	0
T214	266099	0	0	0
T216	0	1	0	0
T217	422	0	0	0
T218	752	0	0	0
T219	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T38,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T15,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T15,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T15,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T19,T20
1	0	Covered	T38,T39,T40
1	1	Covered	T15,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T19,T20
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T19,T20
0	1	Covered	T15,T20,T41
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T19,T20
1	-	Covered	T15,T20,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T19,T20
0	1	Covered	T15,T19,T20
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T19,T20
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T19,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T150,T200
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T19,T20
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T15,T19,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T20,T41
StableSt	-	-	-	-	-	-	0	Covered	T15,T19,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	128	0	0
CntIncr_A	7290145	91665	0	0
CntNoWrap_A	7290145	6635901	0	0
DetectStDropOut_A	7290145	0	0	0
DetectedOut_A	7290145	184402	0	0
DetectedPulseOut_A	7290145	60	0	0
DisabledIdleSt_A	7290145	6249697	0	0
DisabledNoDetection_A	7290145	6252038	0	0
EnterDebounceSt_A	7290145	69	0	0
EnterDetectSt_A	7290145	60	0	0
EnterStableSt_A	7290145	60	0	0
PulseIsPulse_A	7290145	60	0	0
StayInStableSt	7290145	184313	0	0
gen_high_level_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	128	0	0
T15	22719	4	0	0
T16	26814	0	0	0
T19	0	2	0	0
T20	0	2	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	4	0	0
T44	0	4	0	0
T45	0	4	0	0
T46	0	4	0	0
T52	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	2	0	0
T154	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	91665	0	0
T15	22719	99	0	0
T16	26814	0	0	0
T19	0	47	0	0
T20	0	83	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	64	0	0
T44	0	186	0	0
T45	0	64	0	0
T46	0	36	0	0
T52	0	49	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	55	0	0
T154	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635901	0	0
T14	26284	25826	0	0
T15	22719	12524	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	184402	0	0
T15	22719	240	0	0
T16	26814	0	0	0
T19	0	40	0	0
T20	0	227	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	88	0	0
T44	0	385	0	0
T45	0	141	0	0
T46	0	119	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	108	0	0
T154	0	1	0	0
T168	0	57	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	60	0	0
T15	22719	2	0	0
T16	26814	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	1	0	0
T154	0	1	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6249697	0	0
T14	26284	25826	0	0
T15	22719	11758	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6252038	0	0
T14	26284	25835	0	0
T15	22719	11789	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	69	0	0
T15	22719	2	0	0
T16	26814	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T52	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	1	0	0
T154	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	60	0	0
T15	22719	2	0	0
T16	26814	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	1	0	0
T154	0	1	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	60	0	0
T15	22719	2	0	0
T16	26814	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	1	0	0
T154	0	1	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	60	0	0
T15	22719	2	0	0
T16	26814	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	1	0	0
T154	0	1	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	184313	0	0
T15	22719	237	0	0
T16	26814	0	0	0
T19	0	38	0	0
T20	0	226	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	85	0	0
T44	0	381	0	0
T45	0	138	0	0
T46	0	116	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T146	0	106	0	0
T148	0	16	0	0
T168	0	55	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	31	0	0
T15	22719	1	0	0
T16	26814	0	0	0
T20	0	1	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T148	0	2	0	0
T150	0	1	0	0
T154	0	1	0	0
T170	0	1	0	0
T200	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T38,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T41,T44,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T41,T44,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T41,T44,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T41,T48,T44
1	0	Covered	T38,T39,T40
1	1	Covered	T41,T44,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T41,T44,T45
0	1	Covered	T171
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T44,T45
0	1	Covered	T41,T45,T46
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T41,T44,T45
1	-	Covered	T41,T45,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T41,T44,T45
0	1	Covered	T41,T44,T45
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T41,T44,T45
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T41,T44,T45
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T41,T44,T45
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T41,T44,T45
DetectSt	-	-	-	-	1	-	-	Covered	T171
DetectSt	-	-	-	-	0	1	-	Covered	T41,T44,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T45,T46
StableSt	-	-	-	-	-	-	0	Covered	T41,T44,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	88	0	0
CntIncr_A	7290145	2552	0	0
CntNoWrap_A	7290145	6635941	0	0
DetectStDropOut_A	7290145	1	0	0
DetectedOut_A	7290145	3279	0	0
DetectedPulseOut_A	7290145	42	0	0
DisabledIdleSt_A	7290145	6611414	0	0
DisabledNoDetection_A	7290145	6613753	0	0
EnterDebounceSt_A	7290145	45	0	0
EnterDetectSt_A	7290145	43	0	0
EnterStableSt_A	7290145	42	0	0
PulseIsPulse_A	7290145	42	0	0
StayInStableSt	7290145	3213	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7290145	6983	0	0
gen_low_level_sva.LowLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	88	0	0
T41	74252	2	0	0
T44	19144	2	0	0
T45	0	6	0	0
T46	0	2	0	0
T48	32768	0	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T74	0	1	0	0
T148	0	4	0	0
T150	0	4	0	0
T151	0	2	0	0
T154	0	2	0	0
T163	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	2552	0	0
T41	74252	32	0	0
T44	19144	42	0	0
T45	0	178	0	0
T46	0	18	0	0
T48	32768	0	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T74	0	18	0	0
T148	0	42	0	0
T150	0	184	0	0
T151	0	58	0	0
T154	0	71	0	0
T163	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635941	0	0
T14	26284	25826	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	1	0	0
T171	960	1	0	0
T201	750	0	0	0
T220	495	0	0	0
T221	503	0	0	0
T222	4417	0	0	0
T223	493	0	0	0
T224	497	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	3279	0	0
T41	74252	101	0	0
T44	19144	123	0	0
T45	0	296	0	0
T46	0	90	0	0
T48	32768	0	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T148	0	86	0	0
T150	0	114	0	0
T151	0	245	0	0
T154	0	38	0	0
T163	0	38	0	0
T200	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	42	0	0
T41	74252	1	0	0
T44	19144	1	0	0
T45	0	3	0	0
T46	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T148	0	2	0	0
T150	0	2	0	0
T151	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6611414	0	0
T14	26284	25826	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6613753	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	45	0	0
T41	74252	1	0	0
T44	19144	1	0	0
T45	0	3	0	0
T46	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T74	0	1	0	0
T148	0	2	0	0
T150	0	2	0	0
T151	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	43	0	0
T41	74252	1	0	0
T44	19144	1	0	0
T45	0	3	0	0
T46	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T148	0	2	0	0
T150	0	2	0	0
T151	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0
T200	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	42	0	0
T41	74252	1	0	0
T44	19144	1	0	0
T45	0	3	0	0
T46	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T148	0	2	0	0
T150	0	2	0	0
T151	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	42	0	0
T41	74252	1	0	0
T44	19144	1	0	0
T45	0	3	0	0
T46	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T148	0	2	0	0
T150	0	2	0	0
T151	0	1	0	0
T154	0	1	0	0
T163	0	1	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	3213	0	0
T41	74252	100	0	0
T44	19144	121	0	0
T45	0	292	0	0
T46	0	89	0	0
T48	32768	0	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T73	14163	0	0	0
T148	0	83	0	0
T150	0	111	0	0
T151	0	243	0	0
T154	0	36	0	0
T163	0	36	0	0
T200	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6983	0	0
T14	26284	26	0	0
T15	22719	80	0	0
T27	406	0	0	0
T28	713	3	0	0
T29	0	8	0	0
T38	423	3	0	0
T39	422	1	0	0
T40	502	7	0	0
T78	681	3	0	0
T93	526	2	0	0
T94	502	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	18	0	0
T41	74252	1	0	0
T45	41261	2	0	0
T46	0	1	0	0
T48	32768	0	0	0
T52	504	0	0	0
T59	1424	0	0	0
T60	497	0	0	0
T61	445	0	0	0
T62	12008	0	0	0
T63	452	0	0	0
T86	0	1	0	0
T141	524	0	0	0
T148	0	1	0	0
T150	0	1	0	0
T164	0	1	0	0
T170	0	2	0	0
T201	0	1	0	0
T202	0	1	0	0