Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T17,T49
1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T17,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T17,T49

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T17,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T49
1	0	Covered	T14,T17,T51
1	1	Covered	T14,T17,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T49
0	1	Covered	T49,T51,T62
1	0	Covered	T51,T62,T95

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T50
0	1	Covered	T14,T17,T50
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T17,T50
1	-	Covered	T14,T17,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T17,T49
0	1	Covered	T14,T17,T49
0	0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T49
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T49
IdleSt	0	-	-	-	-	-	-	Covered	T14,T17,T49
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T74,T125,T225
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T49
DetectSt	-	-	-	-	1	-	-	Covered	T49,T51,T62
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T50
DetectSt	-	-	-	-	0	0	-	Covered	T14,T17,T49
StableSt	-	-	-	-	-	-	1	Covered	T14,T17,T50
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T50
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	3163	0	0
CntIncr_A	7290145	120082	0	0
CntNoWrap_A	7290145	6632866	0	0
DetectStDropOut_A	7290145	389	0	0
DetectedOut_A	7290145	87031	0	0
DetectedPulseOut_A	7290145	930	0	0
DisabledIdleSt_A	7290145	6117049	0	0
DisabledNoDetection_A	7290145	6119237	0	0
EnterDebounceSt_A	7290145	1598	0	0
EnterDetectSt_A	7290145	1565	0	0
EnterStableSt_A	7290145	930	0	0
PulseIsPulse_A	7290145	930	0	0
StayInStableSt	7290145	85984	0	0
gen_high_event_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_high_level_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	812	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	3163	0	0
T14	26284	50	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	22	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T49	0	56	0	0
T50	0	62	0	0
T51	0	60	0	0
T62	0	62	0	0
T68	0	20	0	0
T79	0	8	0	0
T95	0	20	0	0
T226	0	56	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	120082	0	0
T14	26284	1900	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	671	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T49	0	1509	0	0
T50	0	2387	0	0
T51	0	2393	0	0
T62	0	1175	0	0
T68	0	540	0	0
T79	0	612	0	0
T95	0	693	0	0
T226	0	1092	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6632866	0	0
T14	26284	25776	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	389	0	0
T23	41035	0	0	0
T49	5332	28	0	0
T50	18041	0	0	0
T51	12288	8	0	0
T62	0	10	0	0
T76	0	5	0	0
T95	0	4	0	0
T96	0	5	0	0
T97	0	3	0	0
T98	0	4	0	0
T99	0	18	0	0
T227	0	6	0	0
T228	488	0	0	0
T229	425	0	0	0
T230	2293	0	0	0
T231	423	0	0	0
T232	402	0	0	0
T233	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	87031	0	0
T14	26284	2774	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	1011	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	3806	0	0
T68	0	938	0	0
T79	0	1896	0	0
T137	0	1834	0	0
T226	0	1789	0	0
T234	0	175	0	0
T235	0	1326	0	0
T236	0	1055	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	930	0	0
T14	26284	25	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	11	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	31	0	0
T68	0	10	0	0
T79	0	4	0	0
T137	0	27	0	0
T226	0	28	0	0
T234	0	3	0	0
T235	0	26	0	0
T236	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6117049	0	0
T14	26284	18444	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6119237	0	0
T14	26284	18445	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	1598	0	0
T14	26284	25	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	11	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T49	0	28	0	0
T50	0	31	0	0
T51	0	30	0	0
T62	0	31	0	0
T68	0	10	0	0
T79	0	4	0	0
T95	0	10	0	0
T226	0	28	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	1565	0	0
T14	26284	25	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	11	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T49	0	28	0	0
T50	0	31	0	0
T51	0	30	0	0
T62	0	31	0	0
T68	0	10	0	0
T79	0	4	0	0
T95	0	10	0	0
T226	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	930	0	0
T14	26284	25	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	11	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	31	0	0
T68	0	10	0	0
T79	0	4	0	0
T137	0	27	0	0
T226	0	28	0	0
T234	0	3	0	0
T235	0	26	0	0
T236	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	930	0	0
T14	26284	25	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	11	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	31	0	0
T68	0	10	0	0
T79	0	4	0	0
T137	0	27	0	0
T226	0	28	0	0
T234	0	3	0	0
T235	0	26	0	0
T236	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	85984	0	0
T14	26284	2742	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	1000	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	3774	0	0
T68	0	923	0	0
T79	0	1892	0	0
T137	0	1807	0	0
T226	0	1760	0	0
T234	0	172	0	0
T235	0	1297	0	0
T236	0	1046	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	812	0	0
T14	26284	18	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	11	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	30	0	0
T68	0	5	0	0
T79	0	4	0	0
T137	0	27	0	0
T226	0	27	0	0
T234	0	3	0	0
T235	0	23	0	0
T236	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T38,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T14,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T15,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T16,T73,T100
1	0	Covered	T74,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T18
0	1	Covered	T14,T15,T18
1	0	Covered	T77,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T15,T18
1	-	Covered	T14,T15,T18

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T15,T16
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T15,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T22,T23
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T15,T16
DetectSt	-	-	-	-	1	-	-	Covered	T16,T73,T100
DetectSt	-	-	-	-	0	1	-	Covered	T14,T15,T18
DetectSt	-	-	-	-	0	0	-	Covered	T14,T15,T16
StableSt	-	-	-	-	-	-	1	Covered	T14,T15,T18
StableSt	-	-	-	-	-	-	0	Covered	T14,T15,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	993	0	0
CntIncr_A	7290145	53535	0	0
CntNoWrap_A	7290145	6635036	0	0
DetectStDropOut_A	7290145	77	0	0
DetectedOut_A	7290145	18206	0	0
DetectedPulseOut_A	7290145	377	0	0
DisabledIdleSt_A	7290145	6211308	0	0
DisabledNoDetection_A	7290145	6212887	0	0
EnterDebounceSt_A	7290145	537	0	0
EnterDetectSt_A	7290145	458	0	0
EnterStableSt_A	7290145	377	0	0
PulseIsPulse_A	7290145	377	0	0
StayInStableSt	7290145	17793	0	0
gen_high_level_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	336	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	993	0	0
T14	26284	8	0	0
T15	22719	5	0	0
T16	26814	2	0	0
T18	0	4	0	0
T21	0	2	0	0
T22	0	16	0	0
T23	0	26	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	7	0	0
T50	0	8	0	0
T89	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	53535	0	0
T14	26284	200	0	0
T15	22719	346	0	0
T16	26814	161	0	0
T18	0	170	0	0
T21	0	25	0	0
T22	0	932	0	0
T23	0	1415	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	138	0	0
T50	0	348	0	0
T89	0	148	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635036	0	0
T14	26284	25818	0	0
T15	22719	12523	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	77	0	0
T16	26814	1	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T73	14163	2	0	0
T100	0	5	0	0
T101	0	2	0	0
T102	0	8	0	0
T103	0	7	0	0
T104	0	4	0	0
T105	0	8	0	0
T106	0	3	0	0
T107	0	1	0	0
T110	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	18206	0	0
T14	26284	318	0	0
T15	22719	9	0	0
T16	26814	0	0	0
T18	0	158	0	0
T21	0	3	0	0
T22	0	62	0	0
T23	0	803	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	74	0	0
T50	0	179	0	0
T79	0	577	0	0
T89	0	60	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	377	0	0
T14	26284	4	0	0
T15	22719	2	0	0
T16	26814	0	0	0
T18	0	2	0	0
T21	0	1	0	0
T22	0	6	0	0
T23	0	11	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	3	0	0
T50	0	4	0	0
T79	0	2	0	0
T89	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6211308	0	0
T14	26284	23059	0	0
T15	22719	11688	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6212887	0	0
T14	26284	23061	0	0
T15	22719	11717	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	537	0	0
T14	26284	4	0	0
T15	22719	3	0	0
T16	26814	1	0	0
T18	0	2	0	0
T21	0	1	0	0
T22	0	10	0	0
T23	0	15	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	4	0	0
T50	0	4	0	0
T89	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	458	0	0
T14	26284	4	0	0
T15	22719	2	0	0
T16	26814	1	0	0
T18	0	2	0	0
T21	0	1	0	0
T22	0	6	0	0
T23	0	11	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	3	0	0
T50	0	4	0	0
T89	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	377	0	0
T14	26284	4	0	0
T15	22719	2	0	0
T16	26814	0	0	0
T18	0	2	0	0
T21	0	1	0	0
T22	0	6	0	0
T23	0	11	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	3	0	0
T50	0	4	0	0
T79	0	2	0	0
T89	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	377	0	0
T14	26284	4	0	0
T15	22719	2	0	0
T16	26814	0	0	0
T18	0	2	0	0
T21	0	1	0	0
T22	0	6	0	0
T23	0	11	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	3	0	0
T50	0	4	0	0
T79	0	2	0	0
T89	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	17793	0	0
T14	26284	314	0	0
T15	22719	7	0	0
T16	26814	0	0	0
T18	0	156	0	0
T21	0	2	0	0
T22	0	56	0	0
T23	0	792	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	71	0	0
T50	0	175	0	0
T79	0	575	0	0
T89	0	59	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	336	0	0
T14	26284	4	0	0
T15	22719	2	0	0
T16	26814	0	0	0
T18	0	2	0	0
T21	0	1	0	0
T22	0	6	0	0
T23	0	11	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	3	0	0
T50	0	4	0	0
T79	0	2	0	0
T89	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T17,T49
1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T17,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T17,T49

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T17,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T49
1	0	Covered	T14,T17,T51
1	1	Covered	T14,T17,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T49
0	1	Covered	T49,T62,T96
1	0	Covered	T62,T226,T95

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T51
0	1	Covered	T14,T17,T51
1	0	Covered	T74,T80,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T17,T51
1	-	Covered	T14,T17,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T17,T49
0	1	Covered	T14,T17,T49
0	0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T49
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T49
IdleSt	0	-	-	-	-	-	-	Covered	T14,T17,T49
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T74,T125,T225
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T49
DetectSt	-	-	-	-	1	-	-	Covered	T49,T62,T226
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T51
DetectSt	-	-	-	-	0	0	-	Covered	T14,T17,T49
StableSt	-	-	-	-	-	-	1	Covered	T14,T17,T51
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T51
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	2811	0	0
CntIncr_A	7290145	98781	0	0
CntNoWrap_A	7290145	6633218	0	0
DetectStDropOut_A	7290145	382	0	0
DetectedOut_A	7290145	67667	0	0
DetectedPulseOut_A	7290145	750	0	0
DisabledIdleSt_A	7290145	6136513	0	0
DisabledNoDetection_A	7290145	6138736	0	0
EnterDebounceSt_A	7290145	1422	0	0
EnterDetectSt_A	7290145	1389	0	0
EnterStableSt_A	7290145	750	0	0
PulseIsPulse_A	7290145	750	0	0
StayInStableSt	7290145	66832	0	0
gen_high_event_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_high_level_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	656	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	2811	0	0
T14	26284	28	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	52	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T49	0	14	0	0
T50	0	50	0	0
T51	0	42	0	0
T62	0	30	0	0
T68	0	24	0	0
T79	0	18	0	0
T95	0	54	0	0
T226	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	98781	0	0
T14	26284	854	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	1534	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T49	0	371	0	0
T50	0	2200	0	0
T51	0	1281	0	0
T62	0	565	0	0
T68	0	492	0	0
T79	0	1575	0	0
T95	0	1890	0	0
T226	0	851	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6633218	0	0
T14	26284	25798	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	382	0	0
T23	41035	0	0	0
T49	5332	7	0	0
T50	18041	0	0	0
T51	12288	0	0	0
T62	0	5	0	0
T74	0	1	0	0
T76	0	12	0	0
T96	0	26	0	0
T98	0	8	0	0
T99	0	30	0	0
T228	488	0	0	0
T229	425	0	0	0
T230	2293	0	0	0
T231	423	0	0	0
T232	402	0	0	0
T233	403	0	0	0
T237	0	6	0	0
T238	0	9	0	0
T239	0	26	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	67667	0	0
T14	26284	1218	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	2456	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	2673	0	0
T51	0	960	0	0
T68	0	478	0	0
T79	0	1933	0	0
T137	0	63	0	0
T234	0	928	0	0
T235	0	1768	0	0
T240	0	292	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	750	0	0
T14	26284	14	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	26	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	25	0	0
T51	0	21	0	0
T68	0	12	0	0
T79	0	9	0	0
T137	0	12	0	0
T234	0	11	0	0
T235	0	26	0	0
T240	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6136513	0	0
T14	26284	19944	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6138736	0	0
T14	26284	19948	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	1422	0	0
T14	26284	14	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	26	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T49	0	7	0	0
T50	0	25	0	0
T51	0	21	0	0
T62	0	15	0	0
T68	0	12	0	0
T79	0	9	0	0
T95	0	27	0	0
T226	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	1389	0	0
T14	26284	14	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	26	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T49	0	7	0	0
T50	0	25	0	0
T51	0	21	0	0
T62	0	15	0	0
T68	0	12	0	0
T79	0	9	0	0
T95	0	27	0	0
T226	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	750	0	0
T14	26284	14	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	26	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	25	0	0
T51	0	21	0	0
T68	0	12	0	0
T79	0	9	0	0
T137	0	12	0	0
T234	0	11	0	0
T235	0	26	0	0
T240	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	750	0	0
T14	26284	14	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	26	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	25	0	0
T51	0	21	0	0
T68	0	12	0	0
T79	0	9	0	0
T137	0	12	0	0
T234	0	11	0	0
T235	0	26	0	0
T240	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	66832	0	0
T14	26284	1200	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	2427	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	2645	0	0
T51	0	939	0	0
T68	0	466	0	0
T79	0	1924	0	0
T137	0	51	0	0
T234	0	916	0	0
T235	0	1739	0	0
T240	0	284	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	656	0	0
T14	26284	10	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	23	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	22	0	0
T51	0	21	0	0
T68	0	12	0	0
T79	0	9	0	0
T137	0	12	0	0
T234	0	10	0	0
T235	0	23	0	0
T240	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T38,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T16,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T14,T16,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T16,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T16,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T17
0	1	Covered	T72,T241,T242
1	0	Covered	T74,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T17
0	1	Covered	T16,T17,T18
1	0	Covered	T74,T75,T243

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T16,T17
1	-	Covered	T16,T17,T18

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T16,T17
0	1	Covered	T14,T16,T17
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T17
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T16,T17
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T16,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T23,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T16,T17
DetectSt	-	-	-	-	1	-	-	Covered	T72,T74,T241
DetectSt	-	-	-	-	0	1	-	Covered	T14,T16,T17
DetectSt	-	-	-	-	0	0	-	Covered	T14,T16,T17
StableSt	-	-	-	-	-	-	1	Covered	T16,T17,T18
StableSt	-	-	-	-	-	-	0	Covered	T14,T16,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	851	0	0
CntIncr_A	7290145	52093	0	0
CntNoWrap_A	7290145	6635178	0	0
DetectStDropOut_A	7290145	28	0	0
DetectedOut_A	7290145	17521	0	0
DetectedPulseOut_A	7290145	371	0	0
DisabledIdleSt_A	7290145	6240663	0	0
DisabledNoDetection_A	7290145	6242338	0	0
EnterDebounceSt_A	7290145	448	0	0
EnterDetectSt_A	7290145	403	0	0
EnterStableSt_A	7290145	371	0	0
PulseIsPulse_A	7290145	371	0	0
StayInStableSt	7290145	17119	0	0
gen_high_level_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	336	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	851	0	0
T14	26284	6	0	0
T15	22719	0	0	0
T16	26814	8	0	0
T17	0	6	0	0
T18	0	8	0	0
T22	0	23	0	0
T23	0	17	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T48	0	17	0	0
T50	0	4	0	0
T79	0	2	0	0
T89	0	15	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	52093	0	0
T14	26284	177	0	0
T15	22719	0	0	0
T16	26814	452	0	0
T17	0	261	0	0
T18	0	372	0	0
T22	0	930	0	0
T23	0	1191	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T48	0	852	0	0
T50	0	118	0	0
T79	0	183	0	0
T89	0	1514	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635178	0	0
T14	26284	25820	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	28	0	0
T42	12699	0	0	0
T43	859	0	0	0
T44	19144	0	0	0
T53	9463	0	0	0
T68	23449	0	0	0
T72	15313	4	0	0
T73	14163	0	0	0
T136	0	6	0	0
T173	29886	0	0	0
T241	0	2	0	0
T242	0	3	0	0
T244	0	7	0	0
T245	0	1	0	0
T246	0	3	0	0
T247	0	2	0	0
T248	407	0	0	0
T249	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	17521	0	0
T14	26284	204	0	0
T15	22719	0	0	0
T16	26814	194	0	0
T17	0	164	0	0
T18	0	287	0	0
T22	0	543	0	0
T23	0	254	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T48	0	125	0	0
T50	0	142	0	0
T79	0	39	0	0
T89	0	34	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	371	0	0
T14	26284	3	0	0
T15	22719	0	0	0
T16	26814	4	0	0
T17	0	3	0	0
T18	0	4	0	0
T22	0	10	0	0
T23	0	8	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T48	0	8	0	0
T50	0	2	0	0
T79	0	1	0	0
T89	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6240663	0	0
T14	26284	24612	0	0
T15	22719	11722	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6242338	0	0
T14	26284	24617	0	0
T15	22719	11752	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	448	0	0
T14	26284	3	0	0
T15	22719	0	0	0
T16	26814	4	0	0
T17	0	3	0	0
T18	0	4	0	0
T22	0	13	0	0
T23	0	9	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T48	0	9	0	0
T50	0	2	0	0
T79	0	1	0	0
T89	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	403	0	0
T14	26284	3	0	0
T15	22719	0	0	0
T16	26814	4	0	0
T17	0	3	0	0
T18	0	4	0	0
T22	0	10	0	0
T23	0	8	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T48	0	8	0	0
T50	0	2	0	0
T79	0	1	0	0
T89	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	371	0	0
T14	26284	3	0	0
T15	22719	0	0	0
T16	26814	4	0	0
T17	0	3	0	0
T18	0	4	0	0
T22	0	10	0	0
T23	0	8	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T48	0	8	0	0
T50	0	2	0	0
T79	0	1	0	0
T89	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	371	0	0
T14	26284	3	0	0
T15	22719	0	0	0
T16	26814	4	0	0
T17	0	3	0	0
T18	0	4	0	0
T22	0	10	0	0
T23	0	8	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T48	0	8	0	0
T50	0	2	0	0
T79	0	1	0	0
T89	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	17119	0	0
T14	26284	198	0	0
T15	22719	0	0	0
T16	26814	190	0	0
T17	0	161	0	0
T18	0	283	0	0
T22	0	533	0	0
T23	0	246	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T48	0	117	0	0
T50	0	138	0	0
T79	0	38	0	0
T89	0	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	336	0	0
T16	26814	4	0	0
T17	18428	3	0	0
T18	0	4	0	0
T22	0	10	0	0
T23	0	8	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T48	0	8	0	0
T56	522	0	0	0
T57	436	0	0	0
T58	426	0	0	0
T73	0	7	0	0
T79	0	1	0	0
T89	0	7	0	0
T110	523	0	0	0
T173	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T17,T49
1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T17,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T17,T49

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T17,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T49
1	0	Covered	T14,T17,T51
1	1	Covered	T14,T17,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T49
0	1	Covered	T49,T79,T96
1	0	Covered	T79,T68,T95

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T51
0	1	Covered	T14,T17,T51
1	0	Covered	T74,T81,T250

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T17,T51
1	-	Covered	T14,T17,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T17,T49
0	1	Covered	T14,T17,T49
0	0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T49
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T49
IdleSt	0	-	-	-	-	-	-	Covered	T14,T17,T49
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T74,T125,T225
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T49
DetectSt	-	-	-	-	1	-	-	Covered	T49,T79,T68
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T51
DetectSt	-	-	-	-	0	0	-	Covered	T14,T17,T49
StableSt	-	-	-	-	-	-	1	Covered	T14,T17,T51
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T51
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	3213	0	0
CntIncr_A	7290145	116803	0	0
CntNoWrap_A	7290145	6632816	0	0
DetectStDropOut_A	7290145	476	0	0
DetectedOut_A	7290145	81620	0	0
DetectedPulseOut_A	7290145	933	0	0
DisabledIdleSt_A	7290145	6126675	0	0
DisabledNoDetection_A	7290145	6128909	0	0
EnterDebounceSt_A	7290145	1624	0	0
EnterDetectSt_A	7290145	1589	0	0
EnterStableSt_A	7290145	933	0	0
PulseIsPulse_A	7290145	933	0	0
StayInStableSt	7290145	80616	0	0
gen_high_event_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_high_level_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	838	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	3213	0	0
T14	26284	54	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	24	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T49	0	28	0	0
T50	0	46	0	0
T51	0	24	0	0
T62	0	58	0	0
T68	0	54	0	0
T79	0	46	0	0
T95	0	22	0	0
T226	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	116803	0	0
T14	26284	1350	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	732	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T49	0	747	0	0
T50	0	2070	0	0
T51	0	732	0	0
T62	0	783	0	0
T68	0	1482	0	0
T79	0	6603	0	0
T95	0	769	0	0
T226	0	152	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6632816	0	0
T14	26284	25772	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	476	0	0
T23	41035	0	0	0
T49	5332	14	0	0
T50	18041	0	0	0
T51	12288	0	0	0
T74	0	1	0	0
T76	0	3	0	0
T79	0	16	0	0
T96	0	26	0	0
T98	0	33	0	0
T99	0	20	0	0
T227	0	1	0	0
T228	488	0	0	0
T229	425	0	0	0
T230	2293	0	0	0
T231	423	0	0	0
T232	402	0	0	0
T233	403	0	0	0
T237	0	18	0	0
T239	0	29	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	81620	0	0
T14	26284	2728	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	1351	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	1832	0	0
T51	0	249	0	0
T62	0	1741	0	0
T137	0	136	0	0
T226	0	193	0	0
T234	0	616	0	0
T235	0	964	0	0
T236	0	1005	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	933	0	0
T14	26284	27	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	12	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	23	0	0
T51	0	12	0	0
T62	0	29	0	0
T137	0	10	0	0
T226	0	4	0	0
T234	0	6	0	0
T235	0	14	0	0
T236	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6126675	0	0
T14	26284	19239	0	0
T15	22719	12528	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6128909	0	0
T14	26284	19241	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	1624	0	0
T14	26284	27	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	12	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T49	0	14	0	0
T50	0	23	0	0
T51	0	12	0	0
T62	0	29	0	0
T68	0	27	0	0
T79	0	23	0	0
T95	0	11	0	0
T226	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	1589	0	0
T14	26284	27	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	12	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T49	0	14	0	0
T50	0	23	0	0
T51	0	12	0	0
T62	0	29	0	0
T68	0	27	0	0
T79	0	23	0	0
T95	0	11	0	0
T226	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	933	0	0
T14	26284	27	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	12	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	23	0	0
T51	0	12	0	0
T62	0	29	0	0
T137	0	10	0	0
T226	0	4	0	0
T234	0	6	0	0
T235	0	14	0	0
T236	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	933	0	0
T14	26284	27	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	12	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	23	0	0
T51	0	12	0	0
T62	0	29	0	0
T137	0	10	0	0
T226	0	4	0	0
T234	0	6	0	0
T235	0	14	0	0
T236	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	80616	0	0
T14	26284	2695	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	1338	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	1808	0	0
T51	0	237	0	0
T62	0	1709	0	0
T137	0	126	0	0
T226	0	189	0	0
T234	0	609	0	0
T235	0	948	0	0
T236	0	992	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	838	0	0
T14	26284	21	0	0
T15	22719	0	0	0
T16	26814	0	0	0
T17	0	11	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T50	0	22	0	0
T51	0	12	0	0
T62	0	26	0	0
T137	0	10	0	0
T226	0	4	0	0
T234	0	5	0	0
T235	0	12	0	0
T236	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T15,T16
1	Covered	T38,T39,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T39,T40	VC_COV_UNR
1	Covered	T14,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T39,T40
1	Covered	T14,T15,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16
1	1	Covered	T14,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T111,T251,T103
1	0	Covered	T74,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T74,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T15,T16
1	-	Covered	T14,T15,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
0	0	Excluded	T38,T39,T40	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T15,T16
IdleSt	0	-	-	-	-	-	-	Covered	T38,T39,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T15,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T23,T62
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T15,T16
DetectSt	-	-	-	-	1	-	-	Covered	T111,T251,T74
DetectSt	-	-	-	-	0	1	-	Covered	T14,T15,T16
DetectSt	-	-	-	-	0	0	-	Covered	T14,T15,T16
StableSt	-	-	-	-	-	-	1	Covered	T14,T15,T16
StableSt	-	-	-	-	-	-	0	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T38,T39,T40

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7290145	881	0	0
CntIncr_A	7290145	52613	0	0
CntNoWrap_A	7290145	6635148	0	0
DetectStDropOut_A	7290145	67	0	0
DetectedOut_A	7290145	15655	0	0
DetectedPulseOut_A	7290145	342	0	0
DisabledIdleSt_A	7290145	6220794	0	0
DisabledNoDetection_A	7290145	6222465	0	0
EnterDebounceSt_A	7290145	468	0	0
EnterDetectSt_A	7290145	413	0	0
EnterStableSt_A	7290145	342	0	0
PulseIsPulse_A	7290145	342	0	0
StayInStableSt	7290145	15293	0	0
gen_high_level_sva.HighLevelEvent_A	7290145	6638427	0	0
gen_not_sticky_sva.StableStDropOut_A	7290145	319	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	881	0	0
T14	26284	4	0	0
T15	22719	4	0	0
T16	26814	20	0	0
T17	0	2	0	0
T18	0	4	0	0
T22	0	28	0	0
T23	0	15	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	4	0	0
T48	0	12	0	0
T50	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	52613	0	0
T14	26284	142	0	0
T15	22719	216	0	0
T16	26814	970	0	0
T17	0	90	0	0
T18	0	188	0	0
T22	0	1114	0	0
T23	0	1214	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	166	0	0
T48	0	456	0	0
T50	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6635148	0	0
T14	26284	25822	0	0
T15	22719	12524	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	67	0	0
T55	3168	0	0	0
T86	0	3	0	0
T92	2246	0	0	0
T103	0	13	0	0
T104	0	1	0	0
T105	0	5	0	0
T111	21167	6	0	0
T112	1807	0	0	0
T113	403	0	0	0
T114	526	0	0	0
T115	522	0	0	0
T116	501	0	0	0
T117	505	0	0	0
T200	0	2	0	0
T251	0	4	0	0
T252	0	6	0	0
T253	0	8	0	0
T254	0	2	0	0
T255	497	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	15655	0	0
T14	26284	115	0	0
T15	22719	120	0	0
T16	26814	652	0	0
T17	0	51	0	0
T18	0	140	0	0
T22	0	710	0	0
T23	0	60	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	103	0	0
T48	0	243	0	0
T50	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	342	0	0
T14	26284	2	0	0
T15	22719	2	0	0
T16	26814	10	0	0
T17	0	1	0	0
T18	0	2	0	0
T22	0	13	0	0
T23	0	7	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	2	0	0
T48	0	6	0	0
T50	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6220794	0	0
T14	26284	23104	0	0
T15	22719	11722	0	0
T27	406	5	0	0
T28	713	312	0	0
T38	423	22	0	0
T39	422	21	0	0
T40	502	101	0	0
T78	681	280	0	0
T93	526	125	0	0
T94	502	101	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6222465	0	0
T14	26284	23107	0	0
T15	22719	11752	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	468	0	0
T14	26284	2	0	0
T15	22719	2	0	0
T16	26814	10	0	0
T17	0	1	0	0
T18	0	2	0	0
T22	0	15	0	0
T23	0	8	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	2	0	0
T48	0	6	0	0
T50	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	413	0	0
T14	26284	2	0	0
T15	22719	2	0	0
T16	26814	10	0	0
T17	0	1	0	0
T18	0	2	0	0
T22	0	13	0	0
T23	0	7	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	2	0	0
T48	0	6	0	0
T50	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	342	0	0
T14	26284	2	0	0
T15	22719	2	0	0
T16	26814	10	0	0
T17	0	1	0	0
T18	0	2	0	0
T22	0	13	0	0
T23	0	7	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	2	0	0
T48	0	6	0	0
T50	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	342	0	0
T14	26284	2	0	0
T15	22719	2	0	0
T16	26814	10	0	0
T17	0	1	0	0
T18	0	2	0	0
T22	0	13	0	0
T23	0	7	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	2	0	0
T48	0	6	0	0
T50	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	15293	0	0
T14	26284	112	0	0
T15	22719	118	0	0
T16	26814	642	0	0
T17	0	49	0	0
T18	0	138	0	0
T22	0	697	0	0
T23	0	53	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	101	0	0
T48	0	237	0	0
T50	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	6638427	0	0
T14	26284	25835	0	0
T15	22719	12561	0	0
T27	406	6	0	0
T28	713	313	0	0
T38	423	23	0	0
T39	422	22	0	0
T40	502	102	0	0
T78	681	281	0	0
T93	526	126	0	0
T94	502	102	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7290145	319	0	0
T14	26284	1	0	0
T15	22719	2	0	0
T16	26814	10	0	0
T18	0	2	0	0
T22	0	13	0	0
T23	0	7	0	0
T27	406	0	0	0
T28	713	0	0	0
T29	494	0	0	0
T30	548	0	0	0
T31	496	0	0	0
T32	869	0	0	0
T33	426	0	0	0
T41	0	2	0	0
T48	0	6	0	0
T50	0	1	0	0
T89	0	4	0	0