Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 43 | 43 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
79 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
| Total | Covered | Percent |
Conditions | 19 | 19 | 100.00 |
Logical | 19 | 19 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T14,T17,T49 |
1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T38,T39,T40 |
1 | Covered | T14,T17,T49 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests |
0 | Covered | T38,T39,T40 |
1 | Covered | T14,T17,T49 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T38,T39,T40 |
1 | Covered | T14,T17,T49 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T17,T49 |
1 | 0 | Covered | T14,T17,T51 |
1 | 1 | Covered | T14,T17,T49 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T14,T17,T49 |
0 | 1 | Covered | T49,T62,T79 |
1 | 0 | Covered | T62,T79,T226 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T14,T17,T51 |
0 | 1 | Covered | T14,T17,T51 |
1 | 0 | Covered | T74,T256 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T14,T17,T51 |
1 | - | Covered | T14,T17,T51 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T7 |
DetectSt |
168 |
Covered |
T7 |
IdleSt |
163 |
Covered |
T7 |
StableSt |
191 |
Covered |
T7 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T7 |
DebounceSt->IdleSt |
163 |
Covered |
T7 |
DetectSt->IdleSt |
186 |
Covered |
T7 |
DetectSt->StableSt |
191 |
Covered |
T7 |
IdleSt->DebounceSt |
148 |
Covered |
T7 |
StableSt->IdleSt |
206 |
Covered |
T7 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
20 |
95.24 |
TERNARY |
92 |
3 |
3 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
12 |
11 |
91.67 |
IF |
219 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T14,T17,T49 |
0 |
1 |
Covered |
T14,T17,T49 |
0 |
0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T14,T17,T49 |
0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T38,T39,T40 |
0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T14,T17,T49 |
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T14,T17,T49 |
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T74,T75 |
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T14,T17,T49 |
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T74,T125,T225 |
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T14,T17,T49 |
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T49,T62,T79 |
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T14,T17,T51 |
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T14,T17,T49 |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T14,T17,T51 |
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T14,T17,T51 |
default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T38,T39,T40 |
0 |
Covered |
T38,T39,T40 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
3369 |
0 |
0 |
T14 |
26284 |
4 |
0 |
0 |
T15 |
22719 |
0 |
0 |
0 |
T16 |
26814 |
0 |
0 |
0 |
T17 |
0 |
18 |
0 |
0 |
T27 |
406 |
0 |
0 |
0 |
T28 |
713 |
0 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T49 |
0 |
50 |
0 |
0 |
T50 |
0 |
46 |
0 |
0 |
T51 |
0 |
50 |
0 |
0 |
T62 |
0 |
44 |
0 |
0 |
T68 |
0 |
54 |
0 |
0 |
T79 |
0 |
30 |
0 |
0 |
T95 |
0 |
54 |
0 |
0 |
T226 |
0 |
56 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
134852 |
0 |
0 |
T14 |
26284 |
104 |
0 |
0 |
T15 |
22719 |
0 |
0 |
0 |
T16 |
26814 |
0 |
0 |
0 |
T17 |
0 |
801 |
0 |
0 |
T27 |
406 |
0 |
0 |
0 |
T28 |
713 |
0 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T49 |
0 |
1351 |
0 |
0 |
T50 |
0 |
1748 |
0 |
0 |
T51 |
0 |
1675 |
0 |
0 |
T62 |
0 |
827 |
0 |
0 |
T68 |
0 |
999 |
0 |
0 |
T79 |
0 |
4315 |
0 |
0 |
T95 |
0 |
1809 |
0 |
0 |
T226 |
0 |
1594 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
6632660 |
0 |
0 |
T14 |
26284 |
25822 |
0 |
0 |
T15 |
22719 |
12528 |
0 |
0 |
T27 |
406 |
5 |
0 |
0 |
T28 |
713 |
312 |
0 |
0 |
T38 |
423 |
22 |
0 |
0 |
T39 |
422 |
21 |
0 |
0 |
T40 |
502 |
101 |
0 |
0 |
T78 |
681 |
280 |
0 |
0 |
T93 |
526 |
125 |
0 |
0 |
T94 |
502 |
101 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
412 |
0 |
0 |
T23 |
41035 |
0 |
0 |
0 |
T49 |
5332 |
25 |
0 |
0 |
T50 |
18041 |
0 |
0 |
0 |
T51 |
12288 |
0 |
0 |
0 |
T62 |
0 |
9 |
0 |
0 |
T77 |
0 |
12 |
0 |
0 |
T79 |
0 |
9 |
0 |
0 |
T96 |
0 |
17 |
0 |
0 |
T98 |
0 |
3 |
0 |
0 |
T99 |
0 |
27 |
0 |
0 |
T137 |
0 |
5 |
0 |
0 |
T143 |
0 |
7 |
0 |
0 |
T227 |
0 |
1 |
0 |
0 |
T228 |
488 |
0 |
0 |
0 |
T229 |
425 |
0 |
0 |
0 |
T230 |
2293 |
0 |
0 |
0 |
T231 |
423 |
0 |
0 |
0 |
T232 |
402 |
0 |
0 |
0 |
T233 |
403 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
102521 |
0 |
0 |
T14 |
26284 |
98 |
0 |
0 |
T15 |
22719 |
0 |
0 |
0 |
T16 |
26814 |
0 |
0 |
0 |
T17 |
0 |
1230 |
0 |
0 |
T27 |
406 |
0 |
0 |
0 |
T28 |
713 |
0 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T50 |
0 |
2154 |
0 |
0 |
T51 |
0 |
1397 |
0 |
0 |
T68 |
0 |
2058 |
0 |
0 |
T95 |
0 |
1790 |
0 |
0 |
T97 |
0 |
1687 |
0 |
0 |
T234 |
0 |
5757 |
0 |
0 |
T235 |
0 |
2837 |
0 |
0 |
T240 |
0 |
2683 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
1031 |
0 |
0 |
T14 |
26284 |
2 |
0 |
0 |
T15 |
22719 |
0 |
0 |
0 |
T16 |
26814 |
0 |
0 |
0 |
T17 |
0 |
9 |
0 |
0 |
T27 |
406 |
0 |
0 |
0 |
T28 |
713 |
0 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T50 |
0 |
23 |
0 |
0 |
T51 |
0 |
25 |
0 |
0 |
T68 |
0 |
27 |
0 |
0 |
T95 |
0 |
27 |
0 |
0 |
T97 |
0 |
17 |
0 |
0 |
T234 |
0 |
29 |
0 |
0 |
T235 |
0 |
29 |
0 |
0 |
T240 |
0 |
24 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
6109484 |
0 |
0 |
T14 |
26284 |
20630 |
0 |
0 |
T15 |
22719 |
12528 |
0 |
0 |
T27 |
406 |
5 |
0 |
0 |
T28 |
713 |
312 |
0 |
0 |
T38 |
423 |
22 |
0 |
0 |
T39 |
422 |
21 |
0 |
0 |
T40 |
502 |
101 |
0 |
0 |
T78 |
681 |
280 |
0 |
0 |
T93 |
526 |
125 |
0 |
0 |
T94 |
502 |
101 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
6111673 |
0 |
0 |
T14 |
26284 |
20638 |
0 |
0 |
T15 |
22719 |
12561 |
0 |
0 |
T27 |
406 |
6 |
0 |
0 |
T28 |
713 |
313 |
0 |
0 |
T38 |
423 |
23 |
0 |
0 |
T39 |
422 |
22 |
0 |
0 |
T40 |
502 |
102 |
0 |
0 |
T78 |
681 |
281 |
0 |
0 |
T93 |
526 |
126 |
0 |
0 |
T94 |
502 |
102 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
1699 |
0 |
0 |
T14 |
26284 |
2 |
0 |
0 |
T15 |
22719 |
0 |
0 |
0 |
T16 |
26814 |
0 |
0 |
0 |
T17 |
0 |
9 |
0 |
0 |
T27 |
406 |
0 |
0 |
0 |
T28 |
713 |
0 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T49 |
0 |
25 |
0 |
0 |
T50 |
0 |
23 |
0 |
0 |
T51 |
0 |
25 |
0 |
0 |
T62 |
0 |
22 |
0 |
0 |
T68 |
0 |
27 |
0 |
0 |
T79 |
0 |
15 |
0 |
0 |
T95 |
0 |
27 |
0 |
0 |
T226 |
0 |
28 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
1672 |
0 |
0 |
T14 |
26284 |
2 |
0 |
0 |
T15 |
22719 |
0 |
0 |
0 |
T16 |
26814 |
0 |
0 |
0 |
T17 |
0 |
9 |
0 |
0 |
T27 |
406 |
0 |
0 |
0 |
T28 |
713 |
0 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T49 |
0 |
25 |
0 |
0 |
T50 |
0 |
23 |
0 |
0 |
T51 |
0 |
25 |
0 |
0 |
T62 |
0 |
22 |
0 |
0 |
T68 |
0 |
27 |
0 |
0 |
T79 |
0 |
15 |
0 |
0 |
T95 |
0 |
27 |
0 |
0 |
T226 |
0 |
28 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
1031 |
0 |
0 |
T14 |
26284 |
2 |
0 |
0 |
T15 |
22719 |
0 |
0 |
0 |
T16 |
26814 |
0 |
0 |
0 |
T17 |
0 |
9 |
0 |
0 |
T27 |
406 |
0 |
0 |
0 |
T28 |
713 |
0 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T50 |
0 |
23 |
0 |
0 |
T51 |
0 |
25 |
0 |
0 |
T68 |
0 |
27 |
0 |
0 |
T95 |
0 |
27 |
0 |
0 |
T97 |
0 |
17 |
0 |
0 |
T234 |
0 |
29 |
0 |
0 |
T235 |
0 |
29 |
0 |
0 |
T240 |
0 |
24 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
1031 |
0 |
0 |
T14 |
26284 |
2 |
0 |
0 |
T15 |
22719 |
0 |
0 |
0 |
T16 |
26814 |
0 |
0 |
0 |
T17 |
0 |
9 |
0 |
0 |
T27 |
406 |
0 |
0 |
0 |
T28 |
713 |
0 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T50 |
0 |
23 |
0 |
0 |
T51 |
0 |
25 |
0 |
0 |
T68 |
0 |
27 |
0 |
0 |
T95 |
0 |
27 |
0 |
0 |
T97 |
0 |
17 |
0 |
0 |
T234 |
0 |
29 |
0 |
0 |
T235 |
0 |
29 |
0 |
0 |
T240 |
0 |
24 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
101373 |
0 |
0 |
T14 |
26284 |
96 |
0 |
0 |
T15 |
22719 |
0 |
0 |
0 |
T16 |
26814 |
0 |
0 |
0 |
T17 |
0 |
1221 |
0 |
0 |
T27 |
406 |
0 |
0 |
0 |
T28 |
713 |
0 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T50 |
0 |
2130 |
0 |
0 |
T51 |
0 |
1370 |
0 |
0 |
T68 |
0 |
2023 |
0 |
0 |
T95 |
0 |
1761 |
0 |
0 |
T97 |
0 |
1670 |
0 |
0 |
T234 |
0 |
5721 |
0 |
0 |
T235 |
0 |
2802 |
0 |
0 |
T240 |
0 |
2659 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
6638427 |
0 |
0 |
T14 |
26284 |
25835 |
0 |
0 |
T15 |
22719 |
12561 |
0 |
0 |
T27 |
406 |
6 |
0 |
0 |
T28 |
713 |
313 |
0 |
0 |
T38 |
423 |
23 |
0 |
0 |
T39 |
422 |
22 |
0 |
0 |
T40 |
502 |
102 |
0 |
0 |
T78 |
681 |
281 |
0 |
0 |
T93 |
526 |
126 |
0 |
0 |
T94 |
502 |
102 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
6638427 |
0 |
0 |
T14 |
26284 |
25835 |
0 |
0 |
T15 |
22719 |
12561 |
0 |
0 |
T27 |
406 |
6 |
0 |
0 |
T28 |
713 |
313 |
0 |
0 |
T38 |
423 |
23 |
0 |
0 |
T39 |
422 |
22 |
0 |
0 |
T40 |
502 |
102 |
0 |
0 |
T78 |
681 |
281 |
0 |
0 |
T93 |
526 |
126 |
0 |
0 |
T94 |
502 |
102 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
906 |
0 |
0 |
T14 |
26284 |
2 |
0 |
0 |
T15 |
22719 |
0 |
0 |
0 |
T16 |
26814 |
0 |
0 |
0 |
T17 |
0 |
9 |
0 |
0 |
T27 |
406 |
0 |
0 |
0 |
T28 |
713 |
0 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T50 |
0 |
22 |
0 |
0 |
T51 |
0 |
23 |
0 |
0 |
T68 |
0 |
19 |
0 |
0 |
T95 |
0 |
25 |
0 |
0 |
T97 |
0 |
17 |
0 |
0 |
T234 |
0 |
22 |
0 |
0 |
T235 |
0 |
23 |
0 |
0 |
T240 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 46 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
| Total | Covered | Percent |
Conditions | 21 | 21 | 100.00 |
Logical | 21 | 21 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T14,T15,T16 |
1 | Covered | T38,T39,T40 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T38,T39,T40 |
1 | 1 | Covered | T38,T39,T40 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T38,T39,T40 |
1 | Covered | T15,T16,T17 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T38,T39,T40 |
VC_COV_UNR |
1 | Covered | T15,T16,T17 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T38,T39,T40 |
1 | Covered | T15,T16,T17 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T15,T16 |
1 | 0 | Covered | T14,T15,T16 |
1 | 1 | Covered | T15,T16,T17 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T15,T16,T17 |
0 | 1 | Covered | T22,T23,T48 |
1 | 0 | Covered | T74,T75 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T15,T16,T17 |
0 | 1 | Covered | T15,T16,T17 |
1 | 0 | Covered | T76,T74,T237 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T15,T16,T17 |
1 | - | Covered | T15,T16,T17 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T7 |
DetectSt |
168 |
Covered |
T7 |
IdleSt |
163 |
Covered |
T7 |
StableSt |
191 |
Covered |
T7 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T7 |
DebounceSt->IdleSt |
163 |
Covered |
T7 |
DetectSt->IdleSt |
186 |
Covered |
T7 |
DetectSt->StableSt |
191 |
Covered |
T7 |
IdleSt->DebounceSt |
148 |
Covered |
T7 |
StableSt->IdleSt |
206 |
Covered |
T7 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
21 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
11 |
11 |
100.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T15,T16,T17 |
|
0 |
1 |
Covered |
T15,T16,T17 |
|
0 |
0 |
Excluded |
T38,T39,T40 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T15,T16,T17 |
0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T38,T39,T40 |
0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T15,T16,T17 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T38,T39,T40 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T74,T75 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T15,T16,T17 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T51,T173,T95 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T15,T16,T17 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T22,T23,T48 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T15,T16,T17 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T15,T16,T17 |
|
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T15,T16,T17 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T15,T16,T17 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T38,T39,T40 |
0 |
Covered |
T38,T39,T40 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T38,T39,T40 |
0 |
Covered |
T38,T39,T40 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
962 |
0 |
0 |
T15 |
22719 |
6 |
0 |
0 |
T16 |
26814 |
6 |
0 |
0 |
T17 |
0 |
4 |
0 |
0 |
T18 |
0 |
8 |
0 |
0 |
T22 |
0 |
4 |
0 |
0 |
T23 |
0 |
4 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T41 |
0 |
2 |
0 |
0 |
T48 |
0 |
12 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
7 |
0 |
0 |
T56 |
522 |
0 |
0 |
0 |
T57 |
436 |
0 |
0 |
0 |
T58 |
426 |
0 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
54137 |
0 |
0 |
T15 |
22719 |
375 |
0 |
0 |
T16 |
26814 |
462 |
0 |
0 |
T17 |
0 |
128 |
0 |
0 |
T18 |
0 |
632 |
0 |
0 |
T22 |
0 |
262 |
0 |
0 |
T23 |
0 |
338 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T41 |
0 |
72 |
0 |
0 |
T48 |
0 |
699 |
0 |
0 |
T50 |
0 |
61 |
0 |
0 |
T51 |
0 |
307 |
0 |
0 |
T56 |
522 |
0 |
0 |
0 |
T57 |
436 |
0 |
0 |
0 |
T58 |
426 |
0 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
6635067 |
0 |
0 |
T14 |
26284 |
25826 |
0 |
0 |
T15 |
22719 |
12522 |
0 |
0 |
T27 |
406 |
5 |
0 |
0 |
T28 |
713 |
312 |
0 |
0 |
T38 |
423 |
22 |
0 |
0 |
T39 |
422 |
21 |
0 |
0 |
T40 |
502 |
101 |
0 |
0 |
T78 |
681 |
280 |
0 |
0 |
T93 |
526 |
125 |
0 |
0 |
T94 |
502 |
101 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
102 |
0 |
0 |
T22 |
38814 |
2 |
0 |
0 |
T23 |
41035 |
2 |
0 |
0 |
T41 |
74252 |
0 |
0 |
0 |
T48 |
32768 |
6 |
0 |
0 |
T50 |
18041 |
0 |
0 |
0 |
T54 |
0 |
5 |
0 |
0 |
T88 |
736 |
0 |
0 |
0 |
T107 |
0 |
8 |
0 |
0 |
T208 |
517 |
0 |
0 |
0 |
T232 |
402 |
0 |
0 |
0 |
T233 |
403 |
0 |
0 |
0 |
T241 |
0 |
3 |
0 |
0 |
T242 |
0 |
4 |
0 |
0 |
T254 |
0 |
8 |
0 |
0 |
T257 |
0 |
5 |
0 |
0 |
T258 |
0 |
5 |
0 |
0 |
T259 |
427 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
15551 |
0 |
0 |
T15 |
22719 |
130 |
0 |
0 |
T16 |
26814 |
22 |
0 |
0 |
T17 |
0 |
155 |
0 |
0 |
T18 |
0 |
26 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T41 |
0 |
63 |
0 |
0 |
T50 |
0 |
70 |
0 |
0 |
T51 |
0 |
78 |
0 |
0 |
T56 |
522 |
0 |
0 |
0 |
T57 |
436 |
0 |
0 |
0 |
T58 |
426 |
0 |
0 |
0 |
T68 |
0 |
287 |
0 |
0 |
T72 |
0 |
34 |
0 |
0 |
T89 |
0 |
95 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
350 |
0 |
0 |
T15 |
22719 |
3 |
0 |
0 |
T16 |
26814 |
3 |
0 |
0 |
T17 |
0 |
2 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T50 |
0 |
1 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T56 |
522 |
0 |
0 |
0 |
T57 |
436 |
0 |
0 |
0 |
T58 |
426 |
0 |
0 |
0 |
T68 |
0 |
6 |
0 |
0 |
T72 |
0 |
2 |
0 |
0 |
T89 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
6214977 |
0 |
0 |
T14 |
26284 |
25728 |
0 |
0 |
T15 |
22719 |
11722 |
0 |
0 |
T27 |
406 |
5 |
0 |
0 |
T28 |
713 |
312 |
0 |
0 |
T38 |
423 |
22 |
0 |
0 |
T39 |
422 |
21 |
0 |
0 |
T40 |
502 |
101 |
0 |
0 |
T78 |
681 |
280 |
0 |
0 |
T93 |
526 |
125 |
0 |
0 |
T94 |
502 |
101 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
6216632 |
0 |
0 |
T14 |
26284 |
25737 |
0 |
0 |
T15 |
22719 |
11752 |
0 |
0 |
T27 |
406 |
6 |
0 |
0 |
T28 |
713 |
313 |
0 |
0 |
T38 |
423 |
23 |
0 |
0 |
T39 |
422 |
22 |
0 |
0 |
T40 |
502 |
102 |
0 |
0 |
T78 |
681 |
281 |
0 |
0 |
T93 |
526 |
126 |
0 |
0 |
T94 |
502 |
102 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
507 |
0 |
0 |
T15 |
22719 |
3 |
0 |
0 |
T16 |
26814 |
3 |
0 |
0 |
T17 |
0 |
2 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T48 |
0 |
6 |
0 |
0 |
T50 |
0 |
1 |
0 |
0 |
T51 |
0 |
5 |
0 |
0 |
T56 |
522 |
0 |
0 |
0 |
T57 |
436 |
0 |
0 |
0 |
T58 |
426 |
0 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
456 |
0 |
0 |
T15 |
22719 |
3 |
0 |
0 |
T16 |
26814 |
3 |
0 |
0 |
T17 |
0 |
2 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T22 |
0 |
2 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T48 |
0 |
6 |
0 |
0 |
T50 |
0 |
1 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T56 |
522 |
0 |
0 |
0 |
T57 |
436 |
0 |
0 |
0 |
T58 |
426 |
0 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
350 |
0 |
0 |
T15 |
22719 |
3 |
0 |
0 |
T16 |
26814 |
3 |
0 |
0 |
T17 |
0 |
2 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T50 |
0 |
1 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T56 |
522 |
0 |
0 |
0 |
T57 |
436 |
0 |
0 |
0 |
T58 |
426 |
0 |
0 |
0 |
T68 |
0 |
6 |
0 |
0 |
T72 |
0 |
2 |
0 |
0 |
T89 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
350 |
0 |
0 |
T15 |
22719 |
3 |
0 |
0 |
T16 |
26814 |
3 |
0 |
0 |
T17 |
0 |
2 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T50 |
0 |
1 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T56 |
522 |
0 |
0 |
0 |
T57 |
436 |
0 |
0 |
0 |
T58 |
426 |
0 |
0 |
0 |
T68 |
0 |
6 |
0 |
0 |
T72 |
0 |
2 |
0 |
0 |
T89 |
0 |
1 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
15178 |
0 |
0 |
T15 |
22719 |
127 |
0 |
0 |
T16 |
26814 |
19 |
0 |
0 |
T17 |
0 |
153 |
0 |
0 |
T18 |
0 |
22 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T41 |
0 |
62 |
0 |
0 |
T50 |
0 |
69 |
0 |
0 |
T51 |
0 |
74 |
0 |
0 |
T56 |
522 |
0 |
0 |
0 |
T57 |
436 |
0 |
0 |
0 |
T58 |
426 |
0 |
0 |
0 |
T68 |
0 |
281 |
0 |
0 |
T72 |
0 |
32 |
0 |
0 |
T89 |
0 |
94 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
6638427 |
0 |
0 |
T14 |
26284 |
25835 |
0 |
0 |
T15 |
22719 |
12561 |
0 |
0 |
T27 |
406 |
6 |
0 |
0 |
T28 |
713 |
313 |
0 |
0 |
T38 |
423 |
23 |
0 |
0 |
T39 |
422 |
22 |
0 |
0 |
T40 |
502 |
102 |
0 |
0 |
T78 |
681 |
281 |
0 |
0 |
T93 |
526 |
126 |
0 |
0 |
T94 |
502 |
102 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7290145 |
322 |
0 |
0 |
T15 |
22719 |
3 |
0 |
0 |
T16 |
26814 |
3 |
0 |
0 |
T17 |
0 |
1 |
0 |
0 |
T18 |
0 |
4 |
0 |
0 |
T29 |
494 |
0 |
0 |
0 |
T30 |
548 |
0 |
0 |
0 |
T31 |
496 |
0 |
0 |
0 |
T32 |
869 |
0 |
0 |
0 |
T33 |
426 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T50 |
0 |
1 |
0 |
0 |
T56 |
522 |
0 |
0 |
0 |
T57 |
436 |
0 |
0 |
0 |
T58 |
426 |
0 |
0 |
0 |
T68 |
0 |
6 |
0 |
0 |
T72 |
0 |
2 |
0 |
0 |
T89 |
0 |
1 |
0 |
0 |
T173 |
0 |
1 |
0 |
0 |