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Module Instance : tb.dut.u_reg.u_key_intr_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.76 100.00 88.73 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.62 100.00 94.46 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

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Module Instances:
tb.dut.u_reg.u_key_intr_status_cdc
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT7,T1,T2
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT7,T1,T2
10CoveredT1,T3,T6
11CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT7,T1,T2
01CoveredT15,T19,T20
10CoveredT1,T3,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T3,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT7,T1,T2
10Not Covered
11CoveredT15,T19,T20

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T1,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T3,T6
0 0 0 Covered T7,T1,T2


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T7,T1,T2
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T3,T6
0 0 0 Covered T7,T1,T2


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1193150571 725091 0 0
DstReqKnown_A 7489538 6679653 0 0
SrcAckBusyChk_A 1193150571 665 0 0
SrcBusyKnown_A 1193150571 1191416122 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1193150571 725091 0 0
T1 210898 16125 0 0
T2 147866 218 0 0
T3 528040 6488 0 0
T4 304024 3352 0 0
T5 316359 3492 0 0
T6 597125 1900 0 0
T8 406937 32789 0 0
T9 0 826 0 0
T10 0 8465 0 0
T11 0 341 0 0
T24 384886 0 0 0
T25 197288 0 0 0
T26 191311 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7489538 6679653 0 0
T1 4439 39 0 0
T2 422 6 0 0
T3 1056 656 0 0
T4 633 233 0 0
T5 632 232 0 0
T6 1206 6 0 0
T7 403 3 0 0
T8 8478 78 0 0
T24 7697 7297 0 0
T25 402 2 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1193150571 665 0 0
T1 210898 10 0 0
T2 147866 0 0 0
T3 528040 3 0 0
T4 304024 2 0 0
T5 316359 2 0 0
T6 597125 1 0 0
T8 406937 20 0 0
T9 0 2 0 0
T10 0 16 0 0
T11 0 1 0 0
T12 0 1 0 0
T24 384886 0 0 0
T25 197288 0 0 0
T26 191311 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1193150571 1191416122 0 0
T1 210898 210812 0 0
T2 147866 142198 0 0
T3 528040 527968 0 0
T4 304024 303926 0 0
T5 316359 316288 0 0
T6 597125 596902 0 0
T7 201440 201377 0 0
T8 406937 406784 0 0
T24 384886 384881 0 0
T25 197288 197217 0 0

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