Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T85,T75
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T85,T75
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T41,T22,T96

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T41,T22,T96

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T41,T22,T96

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T41,T22,T96
1	0	Covered	T41,T43,T85
1	1	Covered	T41,T22,T96

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T41,T22,T96
0	1	Covered	T99,T106,T114
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T22,T96
0	1	Covered	T41,T22,T96
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T41,T22,T96
1	-	Covered	T41,T22,T96

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T41,T22,T96
0	1	Covered	T41,T22,T96
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T41,T22,T96
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T41,T22,T96
IdleSt	0	-	-	-	-	-	-	Covered	T41,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T80
DebounceSt	-	0	1	1	-	-	-	Covered	T41,T22,T96
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T94,T99
DebounceSt	-	0	0	-	-	-	-	Covered	T41,T22,T96
DetectSt	-	-	-	-	1	-	-	Covered	T99,T106,T114
DetectSt	-	-	-	-	0	1	-	Covered	T41,T22,T96
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T22,T96
StableSt	-	-	-	-	-	-	0	Covered	T41,T22,T96
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	332	0	0
CntIncr_A	10054024	279661	0	0
CntNoWrap_A	10054024	9352385	0	0
DetectStDropOut_A	10054024	3	0	0
DetectedOut_A	10054024	1030	0	0
DetectedPulseOut_A	10054024	150	0	0
DisabledIdleSt_A	10054024	9065354	0	0
DisabledNoDetection_A	10054024	9067845	0	0
EnterDebounceSt_A	10054024	182	0	0
EnterDetectSt_A	10054024	153	0	0
EnterStableSt_A	10054024	150	0	0
PulseIsPulse_A	10054024	150	0	0
StayInStableSt	10054024	880	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10054024	7139	0	0
gen_low_level_sva.LowLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	149	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	332	0	0
T13	31225	0	0	0
T14	1549	0	0	0
T22	0	5	0	0
T25	490	0	0	0
T41	690	4	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T53	25658	0	0	0
T58	0	2	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	4	0	0
T96	0	6	0	0
T97	0	4	0	0
T98	0	2	0	0
T99	0	3	0	0
T100	0	2	0	0
T101	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	279661	0	0
T13	31225	0	0	0
T14	1549	0	0	0
T22	0	183	0	0
T25	490	0	0	0
T41	690	83	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T53	25658	0	0	0
T58	0	10	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	149	0	0
T96	0	143	0	0
T97	0	145	0	0
T98	0	16	0	0
T99	0	79	0	0
T100	0	37	0	0
T101	0	39561	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9352385	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	285	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	3	0	0
T99	680	1	0	0
T106	16182	1	0	0
T114	0	1	0	0
T117	427	0	0	0
T118	491	0	0	0
T123	431	0	0	0
T124	1780	0	0	0
T125	432	0	0	0
T126	683	0	0	0
T127	748	0	0	0
T128	21214	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1030	0	0
T13	31225	0	0	0
T14	1549	0	0	0
T22	0	10	0	0
T25	490	0	0	0
T41	690	18	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T53	25658	0	0	0
T58	0	2	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	9	0	0
T96	0	18	0	0
T97	0	11	0	0
T98	0	2	0	0
T100	0	2	0	0
T101	0	18	0	0
T129	0	15	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	150	0	0
T13	31225	0	0	0
T14	1549	0	0	0
T22	0	2	0	0
T25	490	0	0	0
T41	690	2	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T53	25658	0	0	0
T58	0	1	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	1	0	0
T96	0	3	0	0
T97	0	2	0	0
T98	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T129	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9065354	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	131	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9067845	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	132	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	182	0	0
T13	31225	0	0	0
T14	1549	0	0	0
T22	0	3	0	0
T25	490	0	0	0
T41	690	2	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T53	25658	0	0	0
T58	0	1	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	3	0	0
T96	0	3	0	0
T97	0	2	0	0
T98	0	1	0	0
T99	0	2	0	0
T100	0	1	0	0
T101	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	153	0	0
T13	31225	0	0	0
T14	1549	0	0	0
T22	0	2	0	0
T25	490	0	0	0
T41	690	2	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T53	25658	0	0	0
T58	0	1	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	1	0	0
T96	0	3	0	0
T97	0	2	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	150	0	0
T13	31225	0	0	0
T14	1549	0	0	0
T22	0	2	0	0
T25	490	0	0	0
T41	690	2	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T53	25658	0	0	0
T58	0	1	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	1	0	0
T96	0	3	0	0
T97	0	2	0	0
T98	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T129	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	150	0	0
T13	31225	0	0	0
T14	1549	0	0	0
T22	0	2	0	0
T25	490	0	0	0
T41	690	2	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T53	25658	0	0	0
T58	0	1	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	1	0	0
T96	0	3	0	0
T97	0	2	0	0
T98	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T129	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	880	0	0
T13	31225	0	0	0
T14	1549	0	0	0
T22	0	8	0	0
T25	490	0	0	0
T41	690	16	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T53	25658	0	0	0
T58	0	1	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	8	0	0
T96	0	15	0	0
T97	0	9	0	0
T98	0	1	0	0
T100	0	1	0	0
T101	0	16	0	0
T129	0	13	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	7139	0	0
T13	31225	12	0	0
T14	1549	6	0	0
T25	490	7	0	0
T26	0	7	0	0
T27	0	30	0	0
T41	690	3	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T53	25658	23	0	0
T75	496	7	0	0
T85	522	4	0	0
T86	518	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	149	0	0
T13	31225	0	0	0
T14	1549	0	0	0
T22	0	2	0	0
T25	490	0	0	0
T41	690	2	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T53	25658	0	0	0
T58	0	1	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	1	0	0
T96	0	3	0	0
T97	0	2	0	0
T98	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T129	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T85,T75
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T85,T75
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T14,T17,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T14,T17,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T44,T63,T69

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T44
1	0	Covered	T41,T43,T85
1	1	Covered	T14,T17,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T44,T63,T69
0	1	Covered	T71,T93,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T63,T69
0	1	Unreachable
1	0	Covered	T44,T63,T69

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T17,T44
0	1	Covered	T14,T17,T44
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T44,T63,T69
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T44
IdleSt	0	-	-	-	-	-	-	Covered	T41,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T44,T63,T69
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T17,T71
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T44
DetectSt	-	-	-	-	1	-	-	Covered	T71,T93,T88
DetectSt	-	-	-	-	0	1	-	Covered	T44,T63,T69
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T63,T69
StableSt	-	-	-	-	-	-	0	Covered	T44,T63,T69
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	166	0	0
CntIncr_A	10054024	272907	0	0
CntNoWrap_A	10054024	9352551	0	0
DetectStDropOut_A	10054024	10	0	0
DetectedOut_A	10054024	369310	0	0
DetectedPulseOut_A	10054024	47	0	0
DisabledIdleSt_A	10054024	6636962	0	0
DisabledNoDetection_A	10054024	6639515	0	0
EnterDebounceSt_A	10054024	111	0	0
EnterDetectSt_A	10054024	57	0	0
EnterStableSt_A	10054024	47	0	0
PulseIsPulse_A	10054024	47	0	0
StayInStableSt	10054024	369263	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10054024	7139	0	0
gen_low_level_sva.LowLevelEvent_A	10054024	9355272	0	0
gen_sticky_sva.StableStDropOut_A	10054024	1728738	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	166	0	0
T14	1549	6	0	0
T15	20268	0	0	0
T17	0	4	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	2	0	0
T63	0	2	0	0
T69	0	4	0	0
T70	0	2	0	0
T71	0	5	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	272907	0	0
T14	1549	396	0	0
T15	20268	0	0	0
T17	0	148	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	39	0	0
T63	0	51	0	0
T69	0	48	0	0
T70	0	12	0	0
T71	0	174933	0	0
T72	0	130	0	0
T73	0	28429	0	0
T74	0	16	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9352551	0	0
T13	31225	30748	0	0
T14	1549	1142	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	10	0	0
T47	14330	0	0	0
T71	267238	2	0	0
T72	19131	0	0	0
T88	0	1	0	0
T91	1084	0	0	0
T93	0	1	0	0
T139	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	2	0	0
T143	12394	0	0	0
T144	402	0	0	0
T145	21406	0	0	0
T146	108768	0	0	0
T147	1401	0	0	0
T148	737	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	369310	0	0
T44	104222	187	0	0
T63	1254	310	0	0
T69	0	99	0	0
T70	0	19	0	0
T73	0	51661	0	0
T74	0	57	0	0
T87	0	441	0	0
T99	680	0	0	0
T115	423	0	0	0
T116	409	0	0	0
T117	427	0	0	0
T131	0	17	0	0
T133	0	75	0	0
T134	0	52	0	0
T135	607	0	0	0
T136	405	0	0	0
T137	495	0	0	0
T138	448	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	47	0	0
T44	104222	1	0	0
T63	1254	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T87	0	1	0	0
T99	680	0	0	0
T115	423	0	0	0
T116	409	0	0	0
T117	427	0	0	0
T131	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	607	0	0	0
T136	405	0	0	0
T137	495	0	0	0
T138	448	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	6636962	0	0
T13	31225	30748	0	0
T14	1549	52	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	6639515	0	0
T13	31225	30761	0	0
T14	1549	53	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	111	0	0
T14	1549	6	0	0
T15	20268	0	0	0
T17	0	4	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	1	0	0
T63	0	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	3	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	57	0	0
T44	104222	1	0	0
T63	1254	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T87	0	1	0	0
T99	680	0	0	0
T115	423	0	0	0
T116	409	0	0	0
T117	427	0	0	0
T131	0	1	0	0
T133	0	1	0	0
T135	607	0	0	0
T136	405	0	0	0
T137	495	0	0	0
T138	448	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	47	0	0
T44	104222	1	0	0
T63	1254	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T87	0	1	0	0
T99	680	0	0	0
T115	423	0	0	0
T116	409	0	0	0
T117	427	0	0	0
T131	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	607	0	0	0
T136	405	0	0	0
T137	495	0	0	0
T138	448	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	47	0	0
T44	104222	1	0	0
T63	1254	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T87	0	1	0	0
T99	680	0	0	0
T115	423	0	0	0
T116	409	0	0	0
T117	427	0	0	0
T131	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	607	0	0	0
T136	405	0	0	0
T137	495	0	0	0
T138	448	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	369263	0	0
T44	104222	186	0	0
T63	1254	309	0	0
T69	0	97	0	0
T70	0	18	0	0
T73	0	51660	0	0
T74	0	56	0	0
T87	0	440	0	0
T99	680	0	0	0
T115	423	0	0	0
T116	409	0	0	0
T117	427	0	0	0
T131	0	16	0	0
T133	0	74	0	0
T134	0	51	0	0
T135	607	0	0	0
T136	405	0	0	0
T137	495	0	0	0
T138	448	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	7139	0	0
T13	31225	12	0	0
T14	1549	6	0	0
T25	490	7	0	0
T26	0	7	0	0
T27	0	30	0	0
T41	690	3	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T53	25658	23	0	0
T75	496	7	0	0
T85	522	4	0	0
T86	518	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1728738	0	0
T44	104222	87283	0	0
T63	1254	319	0	0
T69	0	351	0	0
T70	0	208	0	0
T73	0	126	0	0
T74	0	281	0	0
T87	0	77	0	0
T99	680	0	0	0
T115	423	0	0	0
T116	409	0	0	0
T117	427	0	0	0
T131	0	171	0	0
T133	0	217	0	0
T134	0	137	0	0
T135	607	0	0	0
T136	405	0	0	0
T137	495	0	0	0
T138	448	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T85,T75,T86

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T85,T75,T86
1	1	Covered	T85,T75,T86

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T14,T17,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T14,T17,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T14,T17,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T44
1	0	Covered	T85,T75,T86
1	1	Covered	T14,T17,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T44
0	1	Covered	T69,T74,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T44
0	1	Unreachable
1	0	Covered	T14,T17,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T17,T44
0	1	Covered	T14,T17,T44
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T44
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T44
IdleSt	0	-	-	-	-	-	-	Covered	T85,T75,T86
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T69,T74,T105
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T44
DetectSt	-	-	-	-	1	-	-	Covered	T69,T74,T88
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T17,T44
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	162	0	0
CntIncr_A	10054024	739491	0	0
CntNoWrap_A	10054024	9352555	0	0
DetectStDropOut_A	10054024	9	0	0
DetectedOut_A	10054024	198081	0	0
DetectedPulseOut_A	10054024	47	0	0
DisabledIdleSt_A	10054024	6636962	0	0
DisabledNoDetection_A	10054024	6639515	0	0
EnterDebounceSt_A	10054024	108	0	0
EnterDetectSt_A	10054024	56	0	0
EnterStableSt_A	10054024	47	0	0
PulseIsPulse_A	10054024	47	0	0
StayInStableSt	10054024	198034	0	0
gen_high_level_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_sticky_sva.StableStDropOut_A	10054024	1773064	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	162	0	0
T14	1549	4	0	0
T15	20268	0	0	0
T17	0	2	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	2	0	0
T63	0	2	0	0
T69	0	6	0	0
T70	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	739491	0	0
T14	1549	174	0	0
T15	20268	0	0	0
T17	0	24	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	23325	0	0
T63	0	55	0	0
T69	0	364	0	0
T70	0	79	0	0
T71	0	34	0	0
T72	0	84	0	0
T73	0	65	0	0
T74	0	285	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9352555	0	0
T13	31225	30748	0	0
T14	1549	1144	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9	0	0
T69	993	1	0	0
T70	899	0	0	0
T74	0	2	0	0
T88	0	1	0	0
T103	5215	0	0	0
T139	0	1	0	0
T142	0	4	0	0
T149	524	0	0	0
T150	898	0	0	0
T151	534	0	0	0
T152	533	0	0	0
T153	491	0	0	0
T154	461	0	0	0
T155	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	198081	0	0
T14	1549	593	0	0
T15	20268	0	0	0
T17	0	109	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	64132	0	0
T63	0	242	0	0
T69	0	1	0	0
T70	0	97	0	0
T71	0	100	0	0
T72	0	174	0	0
T73	0	102	0	0
T131	0	51	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	47	0	0
T14	1549	2	0	0
T15	20268	0	0	0
T17	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	1	0	0
T63	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T131	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	6636962	0	0
T13	31225	30748	0	0
T14	1549	52	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	6639515	0	0
T13	31225	30761	0	0
T14	1549	53	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	108	0	0
T14	1549	2	0	0
T15	20268	0	0	0
T17	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	1	0	0
T63	0	1	0	0
T69	0	4	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	56	0	0
T14	1549	2	0	0
T15	20268	0	0	0
T17	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	1	0	0
T63	0	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	47	0	0
T14	1549	2	0	0
T15	20268	0	0	0
T17	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	1	0	0
T63	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T131	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	47	0	0
T14	1549	2	0	0
T15	20268	0	0	0
T17	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	1	0	0
T63	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T131	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	198034	0	0
T14	1549	591	0	0
T15	20268	0	0	0
T17	0	108	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	64131	0	0
T63	0	241	0	0
T70	0	96	0	0
T71	0	99	0	0
T72	0	173	0	0
T73	0	101	0	0
T87	0	253	0	0
T131	0	50	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1773064	0	0
T14	1549	296	0	0
T15	20268	0	0	0
T17	0	116	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	51	0	0
T63	0	370	0	0
T69	0	33	0	0
T70	0	57	0	0
T71	0	259760	0	0
T72	0	81	0	0
T73	0	80058	0	0
T131	0	63	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T85,T75,T86

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T14,T17,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T14,T17,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T14,T17,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T44
1	0	Covered	T85,T75,T86
1	1	Covered	T14,T17,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T44
0	1	Covered	T87,T88,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T44
0	1	Unreachable
1	0	Covered	T14,T17,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T17,T44
0	1	Covered	T14,T17,T44
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T44
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T44
IdleSt	0	-	-	-	-	-	-	Covered	T85,T75,T86
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T63,T70,T72
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T44
DetectSt	-	-	-	-	1	-	-	Covered	T87,T88,T89
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T17,T44
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	165	0	0
CntIncr_A	10054024	183572	0	0
CntNoWrap_A	10054024	9352552	0	0
DetectStDropOut_A	10054024	4	0	0
DetectedOut_A	10054024	1142920	0	0
DetectedPulseOut_A	10054024	54	0	0
DisabledIdleSt_A	10054024	6636962	0	0
DisabledNoDetection_A	10054024	6639515	0	0
EnterDebounceSt_A	10054024	109	0	0
EnterDetectSt_A	10054024	58	0	0
EnterStableSt_A	10054024	54	0	0
PulseIsPulse_A	10054024	54	0	0
StayInStableSt	10054024	1142866	0	0
gen_high_event_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_high_level_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_sticky_sva.StableStDropOut_A	10054024	1304122	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	165	0	0
T14	1549	4	0	0
T15	20268	0	0	0
T17	0	2	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	2	0	0
T63	0	5	0	0
T69	0	4	0	0
T70	0	3	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	183572	0	0
T14	1549	32	0	0
T15	20268	0	0	0
T17	0	11	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	89	0	0
T63	0	230	0	0
T69	0	146	0	0
T70	0	44	0	0
T71	0	47125	0	0
T72	0	60	0	0
T73	0	96	0	0
T74	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9352552	0	0
T13	31225	30748	0	0
T14	1549	1144	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	4	0	0
T87	1027	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T107	35087	0	0	0
T156	0	1	0	0
T157	448	0	0	0
T158	34342	0	0	0
T159	11280	0	0	0
T160	718	0	0	0
T161	1149	0	0	0
T162	93716	0	0	0
T163	15078	0	0	0
T164	743	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1142920	0	0
T14	1549	128	0	0
T15	20268	0	0	0
T17	0	69	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	300	0	0
T69	0	306	0	0
T70	0	1	0	0
T71	0	212731	0	0
T74	0	210	0	0
T87	0	123	0	0
T105	0	5	0	0
T132	0	145	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	54	0	0
T14	1549	2	0	0
T15	20268	0	0	0
T17	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T74	0	1	0	0
T87	0	1	0	0
T105	0	1	0	0
T132	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	6636962	0	0
T13	31225	30748	0	0
T14	1549	52	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	6639515	0	0
T13	31225	30761	0	0
T14	1549	53	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	109	0	0
T14	1549	2	0	0
T15	20268	0	0	0
T17	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	1	0	0
T63	0	5	0	0
T69	0	2	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	58	0	0
T14	1549	2	0	0
T15	20268	0	0	0
T17	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T74	0	1	0	0
T87	0	2	0	0
T105	0	1	0	0
T132	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	54	0	0
T14	1549	2	0	0
T15	20268	0	0	0
T17	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T74	0	1	0	0
T87	0	1	0	0
T105	0	1	0	0
T132	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	54	0	0
T14	1549	2	0	0
T15	20268	0	0	0
T17	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	1	0	0
T69	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T74	0	1	0	0
T87	0	1	0	0
T105	0	1	0	0
T132	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1142866	0	0
T14	1549	126	0	0
T15	20268	0	0	0
T17	0	68	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	299	0	0
T69	0	304	0	0
T71	0	212730	0	0
T74	0	209	0	0
T87	0	122	0	0
T105	0	4	0	0
T132	0	144	0	0
T165	0	264	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1304122	0	0
T14	1549	921	0	0
T15	20268	0	0	0
T17	0	188	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T44	0	87122	0	0
T69	0	74	0	0
T70	0	115	0	0
T71	0	47	0	0
T74	0	112	0	0
T87	0	267	0	0
T105	0	56	0	0
T132	0	68	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T18,T20,T52

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T18,T20,T52

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T20,T52,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T41,T42,T43
1	1	Covered	T18,T20,T52

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T52,T44
0	1	Covered	T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T52,T44
0	1	Covered	T52,T167,T90
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T52,T44
1	-	Covered	T52,T167,T90

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T20,T52
0	1	Covered	T18,T20,T52
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T52,T44
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T20,T52
IdleSt	0	-	-	-	-	-	-	Covered	T41,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T52,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T105,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T20,T52
DetectSt	-	-	-	-	1	-	-	Covered	T166
DetectSt	-	-	-	-	0	1	-	Covered	T20,T52,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T52,T167,T90
StableSt	-	-	-	-	-	-	0	Covered	T20,T52,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	81	0	0
CntIncr_A	10054024	13827	0	0
CntNoWrap_A	10054024	9352636	0	0
DetectStDropOut_A	10054024	1	0	0
DetectedOut_A	10054024	2748	0	0
DetectedPulseOut_A	10054024	36	0	0
DisabledIdleSt_A	10054024	9097091	0	0
DisabledNoDetection_A	10054024	9099586	0	0
EnterDebounceSt_A	10054024	44	0	0
EnterDetectSt_A	10054024	37	0	0
EnterStableSt_A	10054024	36	0	0
PulseIsPulse_A	10054024	36	0	0
StayInStableSt	10054024	2690	0	0
gen_high_level_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	81	0	0
T18	591	2	0	0
T19	98453	0	0	0
T20	3082	2	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	2	0	0
T51	0	2	0	0
T52	0	2	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T90	0	2	0	0
T91	0	2	0	0
T96	692	0	0	0
T146	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	13827	0	0
T18	591	20	0	0
T19	98453	0	0	0
T20	3082	66	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	40	0	0
T51	0	34	0	0
T52	0	11728	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T90	0	14	0	0
T91	0	73	0	0
T96	692	0	0	0
T146	0	27	0	0
T167	0	20	0	0
T168	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9352636	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1	0	0
T166	836	1	0	0
T169	404	0	0	0
T170	25777	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	2748	0	0
T20	3082	38	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	26	0	0
T51	0	108	0	0
T52	54799	40	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	50	0	0
T90	0	113	0	0
T91	0	33	0	0
T94	1556	0	0	0
T96	692	0	0	0
T146	0	50	0	0
T167	0	10	0	0
T168	0	41	0	0
T171	451	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	36	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	1	0	0
T51	0	1	0	0
T52	54799	1	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	2	0	0
T90	0	1	0	0
T91	0	1	0	0
T94	1556	0	0	0
T96	692	0	0	0
T146	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T171	451	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9097091	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9099586	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	44	0	0
T18	591	2	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T90	0	1	0	0
T91	0	1	0	0
T96	692	0	0	0
T146	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	37	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	1	0	0
T51	0	1	0	0
T52	54799	1	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	2	0	0
T90	0	1	0	0
T91	0	1	0	0
T94	1556	0	0	0
T96	692	0	0	0
T146	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T171	451	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	36	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	1	0	0
T51	0	1	0	0
T52	54799	1	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	2	0	0
T90	0	1	0	0
T91	0	1	0	0
T94	1556	0	0	0
T96	692	0	0	0
T146	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T171	451	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	36	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	1	0	0
T51	0	1	0	0
T52	54799	1	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	2	0	0
T90	0	1	0	0
T91	0	1	0	0
T94	1556	0	0	0
T96	692	0	0	0
T146	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T171	451	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	2690	0	0
T20	3082	36	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	24	0	0
T51	0	106	0	0
T52	54799	39	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	48	0	0
T90	0	112	0	0
T91	0	32	0	0
T94	1556	0	0	0
T96	692	0	0	0
T146	0	48	0	0
T167	0	9	0	0
T168	0	39	0	0
T171	451	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	14	0	0
T44	104222	0	0	0
T52	54799	1	0	0
T74	0	2	0	0
T90	632	1	0	0
T91	0	1	0	0
T94	1556	0	0	0
T110	0	1	0	0
T115	423	0	0	0
T116	409	0	0	0
T167	693	1	0	0
T171	451	0	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	537	0	0	0
T177	424	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T18,T20,T58

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T18,T20,T58

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T18,T20,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T58
1	0	Covered	T43,T85,T75
1	1	Covered	T18,T20,T58

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T49
0	1	Covered	T58
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T49
0	1	Covered	T18,T20,T49
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T20,T49
1	-	Covered	T18,T20,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T20,T58
0	1	Covered	T18,T20,T58
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T58
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T20,T58
IdleSt	0	-	-	-	-	-	-	Covered	T41,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T20,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T178,T179,T174
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T20,T58
DetectSt	-	-	-	-	1	-	-	Covered	T58
DetectSt	-	-	-	-	0	1	-	Covered	T18,T20,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T20,T49
StableSt	-	-	-	-	-	-	0	Covered	T18,T20,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	128	0	0
CntIncr_A	10054024	34767	0	0
CntNoWrap_A	10054024	9352589	0	0
DetectStDropOut_A	10054024	1	0	0
DetectedOut_A	10054024	5256	0	0
DetectedPulseOut_A	10054024	60	0	0
DisabledIdleSt_A	10054024	9132506	0	0
DisabledNoDetection_A	10054024	9135000	0	0
EnterDebounceSt_A	10054024	67	0	0
EnterDetectSt_A	10054024	61	0	0
EnterStableSt_A	10054024	60	0	0
PulseIsPulse_A	10054024	60	0	0
StayInStableSt	10054024	5169	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10054024	2855	0	0
gen_low_level_sva.LowLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	128	0	0
T18	591	6	0	0
T19	98453	0	0	0
T20	3082	2	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T49	0	2	0	0
T51	0	2	0	0
T58	0	2	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T72	0	4	0	0
T82	0	2	0	0
T90	0	4	0	0
T96	692	0	0	0
T168	0	2	0	0
T180	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	34767	0	0
T18	591	30	0	0
T19	98453	0	0	0
T20	3082	66	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T49	0	99	0	0
T51	0	34	0	0
T58	0	32	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T72	0	52	0	0
T82	0	25	0	0
T90	0	28	0	0
T96	692	0	0	0
T168	0	66	0	0
T180	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9352589	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1	0	0
T45	8816	0	0	0
T46	33711	0	0	0
T49	1140	0	0	0
T54	27456	0	0	0
T58	12114	1	0	0
T59	696	0	0	0
T130	643	0	0	0
T181	494	0	0	0
T182	522	0	0	0
T183	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	5256	0	0
T18	591	123	0	0
T19	98453	0	0	0
T20	3082	214	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T49	0	492	0	0
T51	0	43	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T72	0	193	0	0
T74	0	43	0	0
T82	0	169	0	0
T90	0	65	0	0
T96	692	0	0	0
T168	0	109	0	0
T180	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	60	0	0
T18	591	3	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T49	0	1	0	0
T51	0	1	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T72	0	2	0	0
T74	0	1	0	0
T82	0	1	0	0
T90	0	2	0	0
T96	692	0	0	0
T168	0	1	0	0
T180	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9132506	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9135000	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	67	0	0
T18	591	3	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T49	0	1	0	0
T51	0	1	0	0
T58	0	1	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T72	0	2	0	0
T82	0	1	0	0
T90	0	2	0	0
T96	692	0	0	0
T168	0	1	0	0
T180	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	61	0	0
T18	591	3	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T49	0	1	0	0
T51	0	1	0	0
T58	0	1	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T72	0	2	0	0
T82	0	1	0	0
T90	0	2	0	0
T96	692	0	0	0
T168	0	1	0	0
T180	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	60	0	0
T18	591	3	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T49	0	1	0	0
T51	0	1	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T72	0	2	0	0
T74	0	1	0	0
T82	0	1	0	0
T90	0	2	0	0
T96	692	0	0	0
T168	0	1	0	0
T180	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	60	0	0
T18	591	3	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T49	0	1	0	0
T51	0	1	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T72	0	2	0	0
T74	0	1	0	0
T82	0	1	0	0
T90	0	2	0	0
T96	692	0	0	0
T168	0	1	0	0
T180	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	5169	0	0
T18	591	119	0	0
T19	98453	0	0	0
T20	3082	213	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T49	0	491	0	0
T51	0	42	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T72	0	190	0	0
T74	0	41	0	0
T82	0	167	0	0
T90	0	62	0	0
T96	692	0	0	0
T168	0	108	0	0
T180	0	35	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	2855	0	0
T13	31225	0	0	0
T14	1549	0	0	0
T16	0	31	0	0
T25	490	5	0	0
T26	448	3	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	0	5	0	0
T30	0	5	0	0
T31	0	7	0	0
T53	25658	12	0	0
T75	496	8	0	0
T85	522	3	0	0
T86	518	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	33	0	0
T18	591	2	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T49	0	1	0	0
T51	0	1	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T72	0	1	0	0
T90	0	1	0	0
T96	692	0	0	0
T110	0	3	0	0
T168	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0