Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.22	100.00	95.66		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	90.61	95.65	85.71		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	90.61	95.65	85.71		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	90.69	95.65	85.71		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	90.69	95.65	85.71		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	90.69	95.65	85.71		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	90.69	95.65	85.71		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.69	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.69	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.69	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.69	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
90.61	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
90.61	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T53,T13,T27
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T53,T13,T27
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T53,T13,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T53,T13,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T53,T13,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T53,T13,T28
1	0	Covered	T43,T53,T13
1	1	Covered	T53,T13,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T53,T13,T15
0	1	Covered	T13,T21,T22
1	0	Covered	T79,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T53,T13,T15
0	1	Covered	T53,T13,T15
1	0	Covered	T79,T81,T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T53,T13,T15
1	-	Covered	T53,T13,T15

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.69	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.69	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.69	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.69	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T41,T18,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T41,T18,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T41,T18,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T41,T18,T19
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T18,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T41,T18,T19
0	1	Covered	T58,T49,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T18,T19
0	1	Covered	T41,T18,T19
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T41,T18,T19
1	-	Covered	T41,T18,T19

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T28,T15
1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T15
1	0	Covered	T28,T15,T46
1	1	Covered	T27,T28,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T15
0	1	Covered	T27,T28,T15
1	0	Covered	T28,T15,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T15,T46
0	1	Covered	T28,T15,T46
1	0	Covered	T60,T83,T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T15,T46
1	-	Covered	T28,T15,T46

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T85,T75,T86

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T14,T17,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T14,T17,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T14,T17,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T44
1	0	Covered	T85,T75,T86
1	1	Covered	T14,T17,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T44
0	1	Covered	T87,T88,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T44
0	1	Unreachable
1	0	Covered	T14,T17,T44

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
90.61	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
90.61	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T16,T18,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T16,T18,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T16,T18,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T41,T42,T43
1	1	Covered	T16,T18,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T90,T91,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T16,T18,T19
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T18,T19
1	-	Covered	T16,T18,T19

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T85,T75,T86

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T85,T75,T86
1	1	Covered	T85,T75,T86

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T14,T17,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T14,T17,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T14,T17,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T44
1	0	Covered	T85,T75,T86
1	1	Covered	T14,T17,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T44
0	1	Covered	T69,T74,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T44
0	1	Unreachable
1	0	Covered	T14,T17,T44

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T85,T75
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T85,T75
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T14,T17,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T14,T17,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T44,T63,T69

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T44
1	0	Covered	T41,T43,T85
1	1	Covered	T14,T17,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T44,T63,T69
0	1	Covered	T71,T93,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T63,T69
0	1	Unreachable
1	0	Covered	T44,T63,T69

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.69	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.69	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.69	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.69	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
90.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
90.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T41,T18,T19
0	1	Covered	T41,T18,T19
0	0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T41,T18,T19
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T41,T18,T19
IdleSt	0	-	-	-	-	-	-	Covered	T41,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T41,T18,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T94,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T41,T18,T19
DetectSt	-	-	-	-	1	-	-	Covered	T58,T49,T82
DetectSt	-	-	-	-	0	1	-	Covered	T41,T18,T19
DetectSt	-	-	-	-	0	0	-	Covered	T53,T13,T15
StableSt	-	-	-	-	-	-	1	Covered	T41,T18,T19
StableSt	-	-	-	-	-	-	0	Covered	T41,T18,T19
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T27,T28
0	1	Covered	T14,T27,T28
0	0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T27,T28
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T85,T75,T86
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T95,T63,T70
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T27,T28,T15
DetectSt	-	-	-	-	0	1	-	Covered	T14,T15,T17
DetectSt	-	-	-	-	0	0	-	Covered	T27,T28,T15
StableSt	-	-	-	-	-	-	1	Covered	T14,T15,T17
StableSt	-	-	-	-	-	-	0	Covered	T14,T15,T17
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	261404624	17883	0	0
CntIncr_A	261404624	2903741	0	0
CntNoWrap_A	261404624	243152759	0	0
DetectStDropOut_A	261404624	1830	0	0
DetectedOut_A	261404624	2320836	0	0
DetectedPulseOut_A	261404624	6033	0	0
DisabledIdleSt_A	261404624	227494494	0	0
DisabledNoDetection_A	261404624	227556052	0	0
EnterDebounceSt_A	261404624	9310	0	0
EnterDetectSt_A	261404624	8601	0	0
EnterStableSt_A	261404624	6032	0	0
PulseIsPulse_A	261404624	6032	0	0
StayInStableSt	261404624	2313894	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	90486216	53401	0	0
gen_high_event_sva.HighLevelEvent_A	50270120	46776360	0	0
gen_high_level_sva.HighLevelEvent_A	170918408	159039624	0	0
gen_low_level_sva.LowLevelEvent_A	90486216	84197448	0	0
gen_not_sticky_sva.StableStDropOut_A	231242552	4909	0	0
gen_sticky_sva.StableStDropOut_A	30162072	4805924	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261404624	17883	0	0
T13	62450	20	0	0
T14	3098	0	0	0
T15	20268	14	0	0
T16	8040	0	0	0
T21	0	31	0	0
T22	0	18	0	0
T25	980	0	0	0
T26	448	0	0	0
T27	10430	34	0	0
T28	14604	20	0	0
T29	1012	0	0	0
T30	846	0	0	0
T31	1044	0	0	0
T32	1495	0	0	0
T41	690	4	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T44	0	2	0	0
T45	0	22	0	0
T46	33711	70	0	0
T53	51316	4	0	0
T54	0	54	0	0
T58	0	8	0	0
T60	0	44	0	0
T64	496	0	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	4	0	0
T96	0	6	0	0
T97	0	4	0	0
T98	0	2	0	0
T99	0	3	0	0
T100	0	2	0	0
T101	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261404624	2903741	0	0
T13	62450	1360	0	0
T14	3098	0	0	0
T15	20268	496	0	0
T16	8040	0	0	0
T21	0	1556	0	0
T22	0	868	0	0
T25	980	0	0	0
T26	448	0	0	0
T27	10430	873	0	0
T28	14604	618	0	0
T29	1012	0	0	0
T30	846	0	0	0
T31	1044	0	0	0
T32	1495	0	0	0
T41	690	83	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T44	0	129	0	0
T45	0	558	0	0
T46	33711	2331	0	0
T53	51316	212	0	0
T54	0	1984	0	0
T58	0	400	0	0
T60	0	1505	0	0
T64	496	0	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	149	0	0
T96	0	143	0	0
T97	0	145	0	0
T98	0	16	0	0
T99	0	79	0	0
T100	0	37	0	0
T101	0	39561	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261404624	243152759	0	0
T13	811850	799366	0	0
T14	40274	29834	0	0
T25	12740	2314	0	0
T41	17940	7510	0	0
T42	3851666	3841240	0	0
T43	219206	338	0	0
T53	667108	603123	0	0
T75	12896	2470	0	0
T85	13572	3146	0	0
T86	13468	3042	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261404624	1830	0	0
T27	5215	17	0	0
T28	0	5	0	0
T44	104222	1	0	0
T48	29879	1	0	0
T54	0	15	0	0
T73	80670	0	0	0
T79	0	1	0	0
T95	0	6	0	0
T99	680	1	0	0
T102	0	3	0	0
T103	0	7	0	0
T104	0	13	0	0
T105	26294	1	0	0
T106	16182	1	0	0
T107	0	7	0	0
T108	0	11	0	0
T109	0	13	0	0
T110	0	2	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	4	0	0
T114	0	1	0	0
T115	423	0	0	0
T116	409	0	0	0
T117	427	0	0	0
T118	491	0	0	0
T119	559	0	0	0
T120	865	0	0	0
T121	506	0	0	0
T122	720	0	0	0
T123	431	0	0	0
T124	1780	0	0	0
T125	432	0	0	0
T126	683	0	0	0
T127	748	0	0	0
T128	21214	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261404624	2320836	0	0
T13	62450	287	0	0
T14	3098	0	0	0
T15	20268	547	0	0
T16	8040	0	0	0
T21	0	439	0	0
T22	0	32	0	0
T25	980	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T41	690	18	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T45	0	258	0	0
T46	33711	3846	0	0
T53	51316	138	0	0
T55	0	1247	0	0
T56	0	1508	0	0
T58	0	213	0	0
T60	0	1768	0	0
T61	0	81	0	0
T62	0	81	0	0
T64	496	0	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	9	0	0
T96	0	18	0	0
T97	0	11	0	0
T98	0	2	0	0
T100	0	2	0	0
T101	0	18	0	0
T129	0	15	0	0
T130	643	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261404624	6033	0	0
T13	62450	8	0	0
T14	3098	0	0	0
T15	20268	7	0	0
T16	8040	0	0	0
T21	0	15	0	0
T22	0	7	0	0
T25	980	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T41	690	2	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T45	0	11	0	0
T46	33711	35	0	0
T53	51316	2	0	0
T55	0	26	0	0
T56	0	15	0	0
T58	0	4	0	0
T60	0	22	0	0
T61	0	2	0	0
T62	0	1	0	0
T64	496	0	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	1	0	0
T96	0	3	0	0
T97	0	2	0	0
T98	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T129	0	2	0	0
T130	643	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261404624	227494494	0	0
T13	811850	781216	0	0
T14	40274	26560	0	0
T25	12740	2314	0	0
T41	17940	7356	0	0
T42	3851666	3841240	0	0
T43	219206	338	0	0
T53	667108	584844	0	0
T75	12896	2470	0	0
T85	13572	3146	0	0
T86	13468	3042	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261404624	227556052	0	0
T13	811850	781502	0	0
T14	40274	26586	0	0
T25	12740	2340	0	0
T41	17940	7382	0	0
T42	3851666	3841266	0	0
T43	219206	806	0	0
T53	667108	585146	0	0
T75	12896	2496	0	0
T85	13572	3172	0	0
T86	13468	3068	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261404624	9310	0	0
T13	62450	12	0	0
T14	3098	0	0	0
T15	20268	7	0	0
T16	8040	0	0	0
T21	0	16	0	0
T22	0	11	0	0
T25	980	0	0	0
T26	448	0	0	0
T27	10430	17	0	0
T28	14604	10	0	0
T29	1012	0	0	0
T30	846	0	0	0
T31	1044	0	0	0
T32	1495	0	0	0
T41	690	2	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T44	0	1	0	0
T45	0	11	0	0
T46	33711	35	0	0
T53	51316	2	0	0
T54	0	27	0	0
T58	0	4	0	0
T60	0	22	0	0
T64	496	0	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	3	0	0
T96	0	3	0	0
T97	0	2	0	0
T98	0	1	0	0
T99	0	2	0	0
T100	0	1	0	0
T101	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261404624	8601	0	0
T13	62450	8	0	0
T14	3098	0	0	0
T15	20268	7	0	0
T16	8040	0	0	0
T21	0	15	0	0
T22	0	7	0	0
T25	980	0	0	0
T26	448	0	0	0
T27	10430	17	0	0
T28	14604	10	0	0
T29	1012	0	0	0
T30	846	0	0	0
T31	1044	0	0	0
T32	1495	0	0	0
T41	690	2	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T44	0	1	0	0
T45	0	11	0	0
T46	33711	35	0	0
T53	51316	2	0	0
T54	0	27	0	0
T58	0	4	0	0
T60	0	22	0	0
T64	496	0	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	1	0	0
T96	0	3	0	0
T97	0	2	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261404624	6032	0	0
T13	62450	8	0	0
T14	3098	0	0	0
T15	20268	7	0	0
T16	8040	0	0	0
T21	0	15	0	0
T22	0	7	0	0
T25	980	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T41	690	2	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T45	0	11	0	0
T46	33711	35	0	0
T53	51316	2	0	0
T55	0	26	0	0
T56	0	15	0	0
T58	0	4	0	0
T60	0	22	0	0
T61	0	2	0	0
T62	0	1	0	0
T64	496	0	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	1	0	0
T96	0	3	0	0
T97	0	2	0	0
T98	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T129	0	2	0	0
T130	643	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	261404624	6032	0	0
T13	62450	8	0	0
T14	3098	0	0	0
T15	20268	7	0	0
T16	8040	0	0	0
T21	0	15	0	0
T22	0	7	0	0
T25	980	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T41	690	2	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T45	0	11	0	0
T46	33711	35	0	0
T53	51316	2	0	0
T55	0	26	0	0
T56	0	15	0	0
T58	0	4	0	0
T60	0	22	0	0
T61	0	2	0	0
T62	0	1	0	0
T64	496	0	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	1	0	0
T96	0	3	0	0
T97	0	2	0	0
T98	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T129	0	2	0	0
T130	643	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	261404624	2313894	0	0
T13	62450	279	0	0
T14	3098	0	0	0
T15	20268	535	0	0
T16	8040	0	0	0
T21	0	424	0	0
T22	0	25	0	0
T25	980	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T41	690	16	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T45	0	246	0	0
T46	33711	3798	0	0
T53	51316	136	0	0
T55	0	1220	0	0
T56	0	1489	0	0
T58	0	209	0	0
T60	0	1746	0	0
T61	0	78	0	0
T62	0	79	0	0
T64	496	0	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	8	0	0
T96	0	15	0	0
T97	0	9	0	0
T98	0	1	0	0
T100	0	1	0	0
T101	0	16	0	0
T129	0	13	0	0
T130	643	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90486216	53401	0	0
T13	281025	86	0	0
T14	13941	24	0	0
T16	0	31	0	0
T25	4410	54	0	0
T26	2688	55	0	0
T27	26075	192	0	0
T28	36510	121	0	0
T29	0	25	0	0
T30	0	8	0	0
T31	0	12	0	0
T41	2070	9	0	0
T42	592564	2	0	0
T43	33724	0	0	0
T53	230922	192	0	0
T75	4464	63	0	0
T85	4698	39	0	0
T86	4662	40	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50270120	46776360	0	0
T13	156125	153805	0	0
T14	7745	5745	0	0
T25	2450	450	0	0
T41	3450	1450	0	0
T42	740705	738705	0	0
T43	42155	155	0	0
T53	128290	116055	0	0
T75	2480	480	0	0
T85	2610	610	0	0
T86	2590	590	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170918408	159039624	0	0
T13	530825	522937	0	0
T14	26333	19533	0	0
T25	8330	1530	0	0
T41	11730	4930	0	0
T42	2518397	2511597	0	0
T43	143327	527	0	0
T53	436186	394587	0	0
T75	8432	1632	0	0
T85	8874	2074	0	0
T86	8806	2006	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90486216	84197448	0	0
T13	281025	276849	0	0
T14	13941	10341	0	0
T25	4410	810	0	0
T41	6210	2610	0	0
T42	1333269	1329669	0	0
T43	75879	279	0	0
T53	230922	208899	0	0
T75	4464	864	0	0
T85	4698	1098	0	0
T86	4662	1062	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231242552	4909	0	0
T13	62450	8	0	0
T14	3098	0	0	0
T15	20268	2	0	0
T16	8040	0	0	0
T21	0	15	0	0
T22	0	7	0	0
T25	980	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T41	690	2	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T45	0	10	0	0
T46	33711	22	0	0
T53	51316	2	0	0
T55	0	25	0	0
T56	0	11	0	0
T58	0	4	0	0
T60	0	22	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	496	0	0	0
T75	496	0	0	0
T85	522	0	0	0
T86	518	0	0	0
T94	0	1	0	0
T96	0	3	0	0
T97	0	2	0	0
T98	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T129	0	2	0	0
T130	643	0	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30162072	4805924	0	0
T14	3098	1217	0	0
T15	40536	0	0	0
T17	0	304	0	0
T25	980	0	0	0
T26	896	0	0	0
T27	10430	0	0	0
T28	14604	0	0	0
T29	1012	0	0	0
T30	846	0	0	0
T31	1044	0	0	0
T32	2990	0	0	0
T44	104222	174456	0	0
T63	1254	689	0	0
T69	0	458	0	0
T70	0	380	0	0
T71	0	259807	0	0
T72	0	81	0	0
T73	0	80184	0	0
T74	0	393	0	0
T87	0	344	0	0
T99	680	0	0	0
T105	0	56	0	0
T115	423	0	0	0
T116	409	0	0	0
T117	427	0	0	0
T131	0	234	0	0
T132	0	68	0	0
T133	0	217	0	0
T134	0	137	0	0
T135	607	0	0	0
T136	405	0	0	0
T137	495	0	0	0
T138	448	0	0	0