Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T85,T75,T86

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T85,T75,T86
1	1	Covered	T85,T75,T86

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T16,T19,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T16,T19,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T19,T22,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T19,T22
1	0	Covered	T85,T75,T86
1	1	Covered	T16,T19,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T22,T44
0	1	Covered	T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T22,T44
0	1	Covered	T19,T22,T49
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T22,T44
1	-	Covered	T19,T22,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T19,T22
0	1	Covered	T16,T19,T22
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T22,T44
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T19,T22
IdleSt	0	-	-	-	-	-	-	Covered	T85,T75,T86
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T22,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T50,T120
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T19,T22
DetectSt	-	-	-	-	1	-	-	Covered	T90
DetectSt	-	-	-	-	0	1	-	Covered	T19,T22,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T22,T49
StableSt	-	-	-	-	-	-	0	Covered	T19,T22,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	160	0	0
CntIncr_A	10054024	87762	0	0
CntNoWrap_A	10054024	9352557	0	0
DetectStDropOut_A	10054024	1	0	0
DetectedOut_A	10054024	16944	0	0
DetectedPulseOut_A	10054024	74	0	0
DisabledIdleSt_A	10054024	9065997	0	0
DisabledNoDetection_A	10054024	9068483	0	0
EnterDebounceSt_A	10054024	86	0	0
EnterDetectSt_A	10054024	75	0	0
EnterStableSt_A	10054024	74	0	0
PulseIsPulse_A	10054024	74	0	0
StayInStableSt	10054024	16840	0	0
gen_high_level_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	44	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	160	0	0
T16	8040	1	0	0
T19	98453	2	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	6	0	0
T44	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T64	496	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	4	0	0
T90	0	4	0	0
T96	692	0	0	0
T167	0	2	0	0
T202	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	87762	0	0
T16	8040	28	0	0
T19	98453	18486	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	24942	0	0
T44	0	91	0	0
T49	0	99	0	0
T50	0	19	0	0
T64	496	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	50	0	0
T90	0	28	0	0
T96	692	0	0	0
T167	0	20	0	0
T202	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9352557	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1	0	0
T90	632	1	0	0
T101	40166	0	0	0
T176	537	0	0	0
T177	424	0	0	0
T210	409	0	0	0
T211	408	0	0	0
T212	4419	0	0	0
T213	620	0	0	0
T214	405	0	0	0
T215	13499	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	16944	0	0
T19	98453	9612	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	166	0	0
T44	0	40	0	0
T49	0	1	0	0
T52	54799	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	110	0	0
T90	0	64	0	0
T94	1556	0	0	0
T96	692	0	0	0
T167	0	101	0	0
T202	0	7	0	0
T213	0	52	0	0
T216	0	134	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	74	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	3	0	0
T44	0	1	0	0
T49	0	1	0	0
T52	54799	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	2	0	0
T90	0	1	0	0
T94	1556	0	0	0
T96	692	0	0	0
T167	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0
T216	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9065997	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9068483	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	86	0	0
T16	8040	1	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	4	0	0
T44	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T64	496	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	2	0	0
T90	0	2	0	0
T96	692	0	0	0
T167	0	1	0	0
T202	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	75	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	3	0	0
T44	0	1	0	0
T49	0	1	0	0
T52	54799	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	2	0	0
T90	0	2	0	0
T94	1556	0	0	0
T96	692	0	0	0
T167	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0
T216	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	74	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	3	0	0
T44	0	1	0	0
T49	0	1	0	0
T52	54799	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	2	0	0
T90	0	1	0	0
T94	1556	0	0	0
T96	692	0	0	0
T167	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0
T216	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	74	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	3	0	0
T44	0	1	0	0
T49	0	1	0	0
T52	54799	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	2	0	0
T90	0	1	0	0
T94	1556	0	0	0
T96	692	0	0	0
T167	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0
T216	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	16840	0	0
T19	98453	9611	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	162	0	0
T44	0	38	0	0
T52	54799	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	108	0	0
T90	0	62	0	0
T91	0	153	0	0
T94	1556	0	0	0
T96	692	0	0	0
T167	0	100	0	0
T202	0	6	0	0
T213	0	51	0	0
T216	0	132	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	44	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	2	0	0
T49	0	1	0	0
T52	54799	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T72	0	2	0	0
T82	0	2	0	0
T91	0	2	0	0
T94	1556	0	0	0
T96	692	0	0	0
T167	0	1	0	0
T199	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T85,T75,T86
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T85,T75,T86
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T16,T18,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T16,T18,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T16,T18,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T43,T85,T75
1	1	Covered	T16,T18,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T19
0	1	Covered	T18,T22,T58
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T18,T19
1	-	Covered	T18,T22,T58

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T18,T19
0	1	Covered	T16,T18,T19
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T19
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T19
IdleSt	0	-	-	-	-	-	-	Covered	T41,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T22,T105
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T19
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T16,T18,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T22,T58
StableSt	-	-	-	-	-	-	0	Covered	T16,T18,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	105	0	0
CntIncr_A	10054024	21161	0	0
CntNoWrap_A	10054024	9352612	0	0
DetectStDropOut_A	10054024	0	0	0
DetectedOut_A	10054024	3663	0	0
DetectedPulseOut_A	10054024	49	0	0
DisabledIdleSt_A	10054024	8997954	0	0
DisabledNoDetection_A	10054024	9000441	0	0
EnterDebounceSt_A	10054024	56	0	0
EnterDetectSt_A	10054024	49	0	0
EnterStableSt_A	10054024	49	0	0
PulseIsPulse_A	10054024	49	0	0
StayInStableSt	10054024	3586	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10054024	6339	0	0
gen_low_level_sva.LowLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	105	0	0
T16	8040	2	0	0
T18	591	2	0	0
T19	98453	2	0	0
T20	3082	2	0	0
T21	36975	0	0	0
T22	0	3	0	0
T50	0	2	0	0
T58	0	4	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T199	0	2	0	0
T202	0	2	0	0
T213	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	21161	0	0
T16	8040	28	0	0
T18	591	10	0	0
T19	98453	18486	0	0
T20	3082	132	0	0
T21	36975	0	0	0
T22	0	50	0	0
T50	0	19	0	0
T58	0	64	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T199	0	28	0	0
T202	0	21	0	0
T213	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9352612	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	3663	0	0
T16	8040	119	0	0
T18	591	48	0	0
T19	98453	41	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	0	14	0	0
T50	0	46	0	0
T58	0	138	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T168	0	111	0	0
T199	0	44	0	0
T202	0	43	0	0
T213	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	49	0	0
T16	8040	1	0	0
T18	591	1	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	0	1	0	0
T50	0	1	0	0
T58	0	2	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T168	0	1	0	0
T199	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8997954	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9000441	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	56	0	0
T16	8040	1	0	0
T18	591	1	0	0
T19	98453	1	0	0
T20	3082	2	0	0
T21	36975	0	0	0
T22	0	2	0	0
T50	0	1	0	0
T58	0	2	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T199	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	49	0	0
T16	8040	1	0	0
T18	591	1	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	0	1	0	0
T50	0	1	0	0
T58	0	2	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T168	0	1	0	0
T199	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	49	0	0
T16	8040	1	0	0
T18	591	1	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	0	1	0	0
T50	0	1	0	0
T58	0	2	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T168	0	1	0	0
T199	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	49	0	0
T16	8040	1	0	0
T18	591	1	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	0	1	0	0
T50	0	1	0	0
T58	0	2	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T168	0	1	0	0
T199	0	1	0	0
T202	0	1	0	0
T213	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	3586	0	0
T16	8040	117	0	0
T18	591	47	0	0
T19	98453	39	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	0	13	0	0
T50	0	44	0	0
T58	0	135	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T168	0	110	0	0
T199	0	42	0	0
T202	0	41	0	0
T213	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	6339	0	0
T13	31225	13	0	0
T14	1549	0	0	0
T25	490	6	0	0
T26	448	7	0	0
T27	5215	32	0	0
T28	7302	31	0	0
T29	0	5	0	0
T53	25658	25	0	0
T75	496	6	0	0
T85	522	4	0	0
T86	518	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	21	0	0
T18	591	1	0	0
T19	98453	0	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	1	0	0
T58	0	1	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T96	692	0	0	0
T166	0	1	0	0
T168	0	1	0	0
T178	0	1	0	0
T187	0	1	0	0
T205	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T85,T75,T86

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T85,T75,T86
1	1	Covered	T85,T75,T86

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T16,T18,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T16,T18,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T16,T18,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T20
1	0	Covered	T85,T75,T86
1	1	Covered	T16,T18,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T20
0	1	Covered	T173
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T20
0	1	Covered	T16,T44,T82
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T18,T20
1	-	Covered	T16,T44,T82

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T18,T20
0	1	Covered	T16,T18,T20
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T20
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T20
IdleSt	0	-	-	-	-	-	-	Covered	T85,T75,T86
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T22,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T20
DetectSt	-	-	-	-	1	-	-	Covered	T173
DetectSt	-	-	-	-	0	1	-	Covered	T16,T18,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T44,T82
StableSt	-	-	-	-	-	-	0	Covered	T16,T18,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	140	0	0
CntIncr_A	10054024	9748	0	0
CntNoWrap_A	10054024	9352577	0	0
DetectStDropOut_A	10054024	1	0	0
DetectedOut_A	10054024	4767	0	0
DetectedPulseOut_A	10054024	63	0	0
DisabledIdleSt_A	10054024	9327159	0	0
DisabledNoDetection_A	10054024	9329654	0	0
EnterDebounceSt_A	10054024	78	0	0
EnterDetectSt_A	10054024	64	0	0
EnterStableSt_A	10054024	63	0	0
PulseIsPulse_A	10054024	63	0	0
StayInStableSt	10054024	4680	0	0
gen_high_level_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	140	0	0
T16	8040	5	0	0
T18	591	2	0	0
T19	98453	0	0	0
T20	3082	2	0	0
T21	36975	0	0	0
T22	0	4	0	0
T44	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T58	0	3	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	2	0	0
T202	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9748	0	0
T16	8040	80	0	0
T18	591	10	0	0
T19	98453	0	0	0
T20	3082	66	0	0
T21	36975	0	0	0
T22	0	75	0	0
T44	0	91	0	0
T50	0	19	0	0
T51	0	34	0	0
T58	0	64	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	25	0	0
T202	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9352577	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1	0	0
T173	196745	1	0	0
T209	4698	0	0	0
T219	19498	0	0	0
T220	33842	0	0	0
T221	522	0	0	0
T222	409285	0	0	0
T223	6017	0	0	0
T224	504	0	0	0
T225	8749	0	0	0
T226	613	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	4767	0	0
T16	8040	78	0	0
T18	591	45	0	0
T19	98453	0	0	0
T20	3082	38	0	0
T21	36975	0	0	0
T22	0	99	0	0
T44	0	45	0	0
T50	0	46	0	0
T51	0	108	0	0
T58	0	172	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	104	0	0
T202	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	63	0	0
T16	8040	2	0	0
T18	591	1	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	0	1	0	0
T44	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T58	0	1	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	1	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9327159	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9329654	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	78	0	0
T16	8040	3	0	0
T18	591	1	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	0	3	0	0
T44	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T58	0	2	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	1	0	0
T202	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	64	0	0
T16	8040	2	0	0
T18	591	1	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	0	1	0	0
T44	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T58	0	1	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	1	0	0
T202	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	63	0	0
T16	8040	2	0	0
T18	591	1	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	0	1	0	0
T44	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T58	0	1	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	1	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	63	0	0
T16	8040	2	0	0
T18	591	1	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	0	1	0	0
T44	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T58	0	1	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	1	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	4680	0	0
T16	8040	75	0	0
T18	591	43	0	0
T19	98453	0	0	0
T20	3082	36	0	0
T21	36975	0	0	0
T22	0	97	0	0
T44	0	44	0	0
T50	0	44	0	0
T51	0	106	0	0
T58	0	170	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	103	0	0
T202	0	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	39	0	0
T16	8040	1	0	0
T44	104222	1	0	0
T55	10596	0	0	0
T56	23692	0	0	0
T64	496	0	0	0
T74	0	1	0	0
T82	701	1	0	0
T91	0	1	0	0
T115	423	0	0	0
T116	409	0	0	0
T120	0	2	0	0
T172	0	2	0	0
T186	0	1	0	0
T196	1983	0	0	0
T197	427	0	0	0
T202	0	1	0	0
T207	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T85,T75,T86
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T85,T75,T86
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T16,T19,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T16,T19,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T16,T19,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T19
1	0	Covered	T43,T85,T75
1	1	Covered	T16,T19,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T44
0	1	Covered	T227,T228
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T44
0	1	Covered	T58,T198,T172
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T19,T44
1	-	Covered	T58,T198,T172

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T19,T44
0	1	Covered	T16,T19,T44
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T19,T44
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T19,T44
IdleSt	0	-	-	-	-	-	-	Covered	T41,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T19,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T207,T178
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T19,T44
DetectSt	-	-	-	-	1	-	-	Covered	T227,T228
DetectSt	-	-	-	-	0	1	-	Covered	T16,T19,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T58,T198,T172
StableSt	-	-	-	-	-	-	0	Covered	T16,T19,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	93	0	0
CntIncr_A	10054024	20867	0	0
CntNoWrap_A	10054024	9352624	0	0
DetectStDropOut_A	10054024	2	0	0
DetectedOut_A	10054024	2785	0	0
DetectedPulseOut_A	10054024	42	0	0
DisabledIdleSt_A	10054024	8944664	0	0
DisabledNoDetection_A	10054024	8947152	0	0
EnterDebounceSt_A	10054024	49	0	0
EnterDetectSt_A	10054024	44	0	0
EnterStableSt_A	10054024	42	0	0
PulseIsPulse_A	10054024	42	0	0
StayInStableSt	10054024	2714	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10054024	6400	0	0
gen_low_level_sva.LowLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	93	0	0
T16	8040	3	0	0
T19	98453	2	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	2	0	0
T58	0	2	0	0
T64	496	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	4	0	0
T79	0	1	0	0
T82	0	2	0	0
T91	0	2	0	0
T96	692	0	0	0
T105	0	2	0	0
T198	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	20867	0	0
T16	8040	54	0	0
T19	98453	18486	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	91	0	0
T58	0	32	0	0
T64	496	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	100	0	0
T79	0	30	0	0
T82	0	25	0	0
T91	0	73	0	0
T96	692	0	0	0
T105	0	16	0	0
T198	0	116	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9352624	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	2	0	0
T227	3090	1	0	0
T228	680	1	0	0
T229	527	0	0	0
T230	934	0	0	0
T231	420	0	0	0
T232	163881	0	0	0
T233	503	0	0	0
T234	647	0	0	0
T235	26635	0	0	0
T236	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	2785	0	0
T16	8040	120	0	0
T19	98453	42	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	41	0	0
T58	0	40	0	0
T64	496	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	117	0	0
T82	0	40	0	0
T91	0	117	0	0
T96	692	0	0	0
T105	0	45	0	0
T110	0	42	0	0
T198	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	42	0	0
T16	8040	1	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	1	0	0
T58	0	1	0	0
T64	496	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	2	0	0
T82	0	1	0	0
T91	0	1	0	0
T96	692	0	0	0
T105	0	1	0	0
T110	0	1	0	0
T198	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8944664	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8947152	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	49	0	0
T16	8040	2	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	1	0	0
T58	0	1	0	0
T64	496	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	2	0	0
T79	0	1	0	0
T82	0	1	0	0
T91	0	1	0	0
T96	692	0	0	0
T105	0	1	0	0
T198	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	44	0	0
T16	8040	1	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	1	0	0
T58	0	1	0	0
T64	496	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	2	0	0
T82	0	1	0	0
T91	0	1	0	0
T96	692	0	0	0
T105	0	1	0	0
T110	0	1	0	0
T198	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	42	0	0
T16	8040	1	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	1	0	0
T58	0	1	0	0
T64	496	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	2	0	0
T82	0	1	0	0
T91	0	1	0	0
T96	692	0	0	0
T105	0	1	0	0
T110	0	1	0	0
T198	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	42	0	0
T16	8040	1	0	0
T19	98453	1	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	1	0	0
T58	0	1	0	0
T64	496	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	2	0	0
T82	0	1	0	0
T91	0	1	0	0
T96	692	0	0	0
T105	0	1	0	0
T110	0	1	0	0
T198	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	2714	0	0
T16	8040	118	0	0
T19	98453	40	0	0
T20	3082	0	0	0
T21	36975	0	0	0
T22	54529	0	0	0
T44	0	39	0	0
T58	0	39	0	0
T64	496	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T74	0	113	0	0
T82	0	38	0	0
T91	0	115	0	0
T96	692	0	0	0
T105	0	43	0	0
T110	0	40	0	0
T198	0	76	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	6400	0	0
T13	31225	9	0	0
T14	1549	0	0	0
T25	490	6	0	0
T26	448	5	0	0
T27	5215	29	0	0
T28	7302	22	0	0
T29	0	5	0	0
T53	25658	27	0	0
T75	496	5	0	0
T85	522	4	0	0
T86	518	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	13	0	0
T45	8816	0	0	0
T46	33711	0	0	0
T49	1140	0	0	0
T54	27456	0	0	0
T58	12114	1	0	0
T59	696	0	0	0
T130	643	0	0	0
T166	0	1	0	0
T172	0	1	0	0
T178	0	1	0	0
T181	494	0	0	0
T182	522	0	0	0
T183	402	0	0	0
T198	0	1	0	0
T205	0	1	0	0
T217	0	1	0	0
T237	0	1	0	0
T238	0	1	0	0
T239	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T41,T85,T75

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T42,T43
1	0	Covered	T41,T85,T75
1	1	Covered	T41,T85,T75

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T16,T18,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T16,T18,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T18,T20,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T20
1	0	Covered	T41,T85,T75
1	1	Covered	T16,T18,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T22
0	1	Covered	T90,T92,T173
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T22
0	1	Covered	T18,T20,T22
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T20,T22
1	-	Covered	T18,T20,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T18,T20
0	1	Covered	T16,T18,T20
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T22
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T20
IdleSt	0	-	-	-	-	-	-	Covered	T41,T85,T75
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T20,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T20,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T20
DetectSt	-	-	-	-	1	-	-	Covered	T90,T92,T173
DetectSt	-	-	-	-	0	1	-	Covered	T18,T20,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T20,T22
StableSt	-	-	-	-	-	-	0	Covered	T18,T20,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	170	0	0
CntIncr_A	10054024	97762	0	0
CntNoWrap_A	10054024	9352547	0	0
DetectStDropOut_A	10054024	4	0	0
DetectedOut_A	10054024	4871	0	0
DetectedPulseOut_A	10054024	77	0	0
DisabledIdleSt_A	10054024	9130071	0	0
DisabledNoDetection_A	10054024	9132560	0	0
EnterDebounceSt_A	10054024	89	0	0
EnterDetectSt_A	10054024	81	0	0
EnterStableSt_A	10054024	77	0	0
PulseIsPulse_A	10054024	77	0	0
StayInStableSt	10054024	4763	0	0
gen_high_level_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	46	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	170	0	0
T16	8040	1	0	0
T18	591	6	0	0
T19	98453	0	0	0
T20	3082	3	0	0
T21	36975	0	0	0
T22	0	6	0	0
T44	0	4	0	0
T49	0	4	0	0
T51	0	2	0	0
T58	0	6	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	4	0	0
T90	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	97762	0	0
T16	8040	28	0	0
T18	591	30	0	0
T19	98453	0	0	0
T20	3082	132	0	0
T21	36975	0	0	0
T22	0	75	0	0
T44	0	131	0	0
T49	0	198	0	0
T51	0	34	0	0
T58	0	96	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	50	0	0
T90	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9352547	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	4	0	0
T90	632	1	0	0
T92	0	1	0	0
T101	40166	0	0	0
T173	0	1	0	0
T176	537	0	0	0
T177	424	0	0	0
T210	409	0	0	0
T211	408	0	0	0
T212	4419	0	0	0
T213	620	0	0	0
T214	405	0	0	0
T215	13499	0	0	0
T241	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	4871	0	0
T18	591	123	0	0
T19	98453	0	0	0
T20	3082	5	0	0
T21	36975	0	0	0
T22	54529	169	0	0
T44	0	70	0	0
T49	0	80	0	0
T51	0	78	0	0
T58	0	129	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	68	0	0
T90	0	43	0	0
T96	692	0	0	0
T213	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	77	0	0
T18	591	3	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	3	0	0
T44	0	2	0	0
T49	0	2	0	0
T51	0	1	0	0
T58	0	3	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	2	0	0
T90	0	1	0	0
T96	692	0	0	0
T213	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9130071	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9132560	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	89	0	0
T16	8040	1	0	0
T18	591	3	0	0
T19	98453	0	0	0
T20	3082	2	0	0
T21	36975	0	0	0
T22	0	3	0	0
T44	0	2	0	0
T49	0	2	0	0
T51	0	1	0	0
T58	0	3	0	0
T64	496	0	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	2	0	0
T90	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	81	0	0
T18	591	3	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	3	0	0
T44	0	2	0	0
T49	0	2	0	0
T51	0	1	0	0
T58	0	3	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	2	0	0
T90	0	2	0	0
T96	692	0	0	0
T213	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	77	0	0
T18	591	3	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	3	0	0
T44	0	2	0	0
T49	0	2	0	0
T51	0	1	0	0
T58	0	3	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	2	0	0
T90	0	1	0	0
T96	692	0	0	0
T213	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	77	0	0
T18	591	3	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	3	0	0
T44	0	2	0	0
T49	0	2	0	0
T51	0	1	0	0
T58	0	3	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	2	0	0
T90	0	1	0	0
T96	692	0	0	0
T213	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	4763	0	0
T18	591	119	0	0
T19	98453	0	0	0
T20	3082	4	0	0
T21	36975	0	0	0
T22	54529	165	0	0
T44	0	67	0	0
T49	0	77	0	0
T51	0	77	0	0
T58	0	125	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	66	0	0
T90	0	41	0	0
T96	692	0	0	0
T213	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	46	0	0
T18	591	2	0	0
T19	98453	0	0	0
T20	3082	1	0	0
T21	36975	0	0	0
T22	54529	2	0	0
T44	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T58	0	2	0	0
T65	492	0	0	0
T66	498	0	0	0
T67	523	0	0	0
T68	524	0	0	0
T82	0	2	0	0
T91	0	1	0	0
T96	692	0	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T85,T75
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T85,T75
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T49,T50,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T49,T50,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T49,T50,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T19,T44
1	0	Covered	T41,T43,T85
1	1	Covered	T49,T50,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T49,T50,T51
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T50,T51
0	1	Covered	T49,T167,T82
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T49,T50,T51
1	-	Covered	T49,T167,T82

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T49,T50,T51
0	1	Covered	T49,T50,T51
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T49,T50,T51
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T49,T50,T51
IdleSt	0	-	-	-	-	-	-	Covered	T41,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T49,T50,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T207
DebounceSt	-	0	0	-	-	-	-	Covered	T49,T50,T51
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T49,T50,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T49,T167,T82
StableSt	-	-	-	-	-	-	0	Covered	T49,T50,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	95	0	0
CntIncr_A	10054024	2774	0	0
CntNoWrap_A	10054024	9352622	0	0
DetectStDropOut_A	10054024	0	0	0
DetectedOut_A	10054024	3490	0	0
DetectedPulseOut_A	10054024	46	0	0
DisabledIdleSt_A	10054024	9033092	0	0
DisabledNoDetection_A	10054024	9035583	0	0
EnterDebounceSt_A	10054024	49	0	0
EnterDetectSt_A	10054024	46	0	0
EnterStableSt_A	10054024	46	0	0
PulseIsPulse_A	10054024	46	0	0
StayInStableSt	10054024	3420	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10054024	7139	0	0
gen_low_level_sva.LowLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	95	0	0
T49	1140	2	0	0
T50	478	2	0	0
T51	0	2	0	0
T61	502	0	0	0
T79	0	1	0	0
T82	0	4	0	0
T97	721	0	0	0
T120	0	2	0	0
T167	0	4	0	0
T184	0	2	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T194	874	0	0	0
T195	402	0	0	0
T202	0	2	0	0
T242	0	2	0	0
T243	868	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	2774	0	0
T49	1140	99	0	0
T50	478	19	0	0
T51	0	34	0	0
T61	502	0	0	0
T79	0	31	0	0
T82	0	50	0	0
T97	721	0	0	0
T120	0	50	0	0
T167	0	40	0	0
T184	0	25	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T194	874	0	0	0
T195	402	0	0	0
T202	0	21	0	0
T242	0	91	0	0
T243	868	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9352622	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	3490	0	0
T49	1140	250	0	0
T50	478	46	0	0
T51	0	107	0	0
T61	502	0	0	0
T82	0	121	0	0
T97	721	0	0	0
T120	0	111	0	0
T167	0	112	0	0
T184	0	46	0	0
T185	0	1	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T194	874	0	0	0
T195	402	0	0	0
T202	0	43	0	0
T242	0	43	0	0
T243	868	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	46	0	0
T49	1140	1	0	0
T50	478	1	0	0
T51	0	1	0	0
T61	502	0	0	0
T82	0	2	0	0
T97	721	0	0	0
T120	0	1	0	0
T167	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T194	874	0	0	0
T195	402	0	0	0
T202	0	1	0	0
T242	0	1	0	0
T243	868	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9033092	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9035583	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	49	0	0
T49	1140	1	0	0
T50	478	1	0	0
T51	0	1	0	0
T61	502	0	0	0
T79	0	1	0	0
T82	0	2	0	0
T97	721	0	0	0
T120	0	1	0	0
T167	0	2	0	0
T184	0	1	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T194	874	0	0	0
T195	402	0	0	0
T202	0	1	0	0
T242	0	1	0	0
T243	868	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	46	0	0
T49	1140	1	0	0
T50	478	1	0	0
T51	0	1	0	0
T61	502	0	0	0
T82	0	2	0	0
T97	721	0	0	0
T120	0	1	0	0
T167	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T194	874	0	0	0
T195	402	0	0	0
T202	0	1	0	0
T242	0	1	0	0
T243	868	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	46	0	0
T49	1140	1	0	0
T50	478	1	0	0
T51	0	1	0	0
T61	502	0	0	0
T82	0	2	0	0
T97	721	0	0	0
T120	0	1	0	0
T167	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T194	874	0	0	0
T195	402	0	0	0
T202	0	1	0	0
T242	0	1	0	0
T243	868	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	46	0	0
T49	1140	1	0	0
T50	478	1	0	0
T51	0	1	0	0
T61	502	0	0	0
T82	0	2	0	0
T97	721	0	0	0
T120	0	1	0	0
T167	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T194	874	0	0	0
T195	402	0	0	0
T202	0	1	0	0
T242	0	1	0	0
T243	868	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	3420	0	0
T49	1140	249	0	0
T50	478	44	0	0
T51	0	105	0	0
T61	502	0	0	0
T82	0	118	0	0
T97	721	0	0	0
T120	0	110	0	0
T167	0	109	0	0
T184	0	44	0	0
T186	0	162	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T194	874	0	0	0
T195	402	0	0	0
T202	0	41	0	0
T242	0	41	0	0
T243	868	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	7139	0	0
T13	31225	12	0	0
T14	1549	6	0	0
T25	490	7	0	0
T26	0	7	0	0
T27	0	30	0	0
T41	690	3	0	0
T42	148141	0	0	0
T43	8431	0	0	0
T53	25658	23	0	0
T75	496	7	0	0
T85	522	4	0	0
T86	518	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	22	0	0
T49	1140	1	0	0
T82	701	1	0	0
T97	721	0	0	0
T110	0	1	0	0
T120	0	1	0	0
T167	693	1	0	0
T185	0	1	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T194	874	0	0	0
T195	402	0	0	0
T196	1983	0	0	0
T200	0	1	0	0
T205	0	1	0	0
T207	0	1	0	0
T218	0	1	0	0