Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T28,T15
1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T15
1	0	Covered	T28,T15,T46
1	1	Covered	T27,T28,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T15
0	1	Covered	T27,T28,T54
1	0	Covered	T28,T54,T102

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T46,T45
0	1	Covered	T15,T46,T45
1	0	Covered	T83,T84,T244

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T46,T45
1	-	Covered	T15,T46,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T28,T15
0	1	Covered	T27,T28,T15
0	0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T15
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T28,T15
IdleSt	0	-	-	-	-	-	-	Covered	T27,T28,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T28,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T95,T79,T245
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T28,T15
DetectSt	-	-	-	-	1	-	-	Covered	T27,T28,T54
DetectSt	-	-	-	-	0	1	-	Covered	T15,T46,T45
DetectSt	-	-	-	-	0	0	-	Covered	T27,T28,T15
StableSt	-	-	-	-	-	-	1	Covered	T15,T46,T45
StableSt	-	-	-	-	-	-	0	Covered	T15,T46,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	2764	0	0
CntIncr_A	10054024	100928	0	0
CntNoWrap_A	10054024	9349953	0	0
DetectStDropOut_A	10054024	330	0	0
DetectedOut_A	10054024	77631	0	0
DetectedPulseOut_A	10054024	860	0	0
DisabledIdleSt_A	10054024	8875191	0	0
DisabledNoDetection_A	10054024	8877520	0	0
EnterDebounceSt_A	10054024	1398	0	0
EnterDetectSt_A	10054024	1366	0	0
EnterStableSt_A	10054024	860	0	0
PulseIsPulse_A	10054024	860	0	0
StayInStableSt	10054024	76634	0	0
gen_high_event_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_high_level_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	695	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	2764	0	0
T15	20268	8	0	0
T16	8040	0	0	0
T27	5215	34	0	0
T28	7302	20	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	20	0	0
T46	33711	58	0	0
T54	0	54	0	0
T60	0	38	0	0
T61	0	2	0	0
T62	0	2	0	0
T64	496	0	0	0
T102	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	100928	0	0
T15	20268	232	0	0
T16	8040	0	0	0
T27	5215	873	0	0
T28	7302	618	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	520	0	0
T46	33711	2001	0	0
T54	0	1984	0	0
T60	0	1235	0	0
T61	0	21	0	0
T62	0	21	0	0
T64	496	0	0	0
T102	0	199	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9349953	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	330	0	0
T15	20268	0	0	0
T16	8040	0	0	0
T27	5215	17	0	0
T28	7302	5	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T54	27456	15	0	0
T64	496	0	0	0
T79	0	1	0	0
T95	0	6	0	0
T102	0	3	0	0
T103	0	7	0	0
T104	0	13	0	0
T246	0	7	0	0
T247	0	12	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	77631	0	0
T15	20268	436	0	0
T16	8040	0	0	0
T45	8816	190	0	0
T46	33711	3379	0	0
T49	1140	0	0	0
T54	27456	0	0	0
T55	0	1247	0	0
T56	0	1508	0	0
T60	0	1637	0	0
T61	0	77	0	0
T62	0	81	0	0
T64	496	0	0	0
T130	643	0	0	0
T143	0	619	0	0
T154	0	35	0	0
T182	522	0	0	0
T183	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	860	0	0
T15	20268	4	0	0
T16	8040	0	0	0
T45	8816	10	0	0
T46	33711	29	0	0
T49	1140	0	0	0
T54	27456	0	0	0
T55	0	26	0	0
T56	0	15	0	0
T60	0	19	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	496	0	0	0
T130	643	0	0	0
T143	0	10	0	0
T154	0	1	0	0
T182	522	0	0	0
T183	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8875191	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8877520	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1398	0	0
T15	20268	4	0	0
T16	8040	0	0	0
T27	5215	17	0	0
T28	7302	10	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	10	0	0
T46	33711	29	0	0
T54	0	27	0	0
T60	0	19	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	496	0	0	0
T102	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1366	0	0
T15	20268	4	0	0
T16	8040	0	0	0
T27	5215	17	0	0
T28	7302	10	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	10	0	0
T46	33711	29	0	0
T54	0	27	0	0
T60	0	19	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	496	0	0	0
T102	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	860	0	0
T15	20268	4	0	0
T16	8040	0	0	0
T45	8816	10	0	0
T46	33711	29	0	0
T49	1140	0	0	0
T54	27456	0	0	0
T55	0	26	0	0
T56	0	15	0	0
T60	0	19	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	496	0	0	0
T130	643	0	0	0
T143	0	10	0	0
T154	0	1	0	0
T182	522	0	0	0
T183	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	860	0	0
T15	20268	4	0	0
T16	8040	0	0	0
T45	8816	10	0	0
T46	33711	29	0	0
T49	1140	0	0	0
T54	27456	0	0	0
T55	0	26	0	0
T56	0	15	0	0
T60	0	19	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	496	0	0	0
T130	643	0	0	0
T143	0	10	0	0
T154	0	1	0	0
T182	522	0	0	0
T183	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	76634	0	0
T15	20268	429	0	0
T16	8040	0	0	0
T45	8816	179	0	0
T46	33711	3343	0	0
T49	1140	0	0	0
T54	27456	0	0	0
T55	0	1220	0	0
T56	0	1489	0	0
T60	0	1618	0	0
T61	0	75	0	0
T62	0	79	0	0
T64	496	0	0	0
T130	643	0	0	0
T143	0	608	0	0
T154	0	33	0	0
T182	522	0	0	0
T183	402	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	695	0	0
T15	20268	1	0	0
T16	8040	0	0	0
T45	8816	9	0	0
T46	33711	22	0	0
T47	0	6	0	0
T49	1140	0	0	0
T54	27456	0	0	0
T55	0	25	0	0
T56	0	11	0	0
T60	0	19	0	0
T64	496	0	0	0
T79	0	5	0	0
T130	643	0	0	0
T143	0	9	0	0
T182	522	0	0	0
T183	402	0	0	0
T248	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T53,T13,T27
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T53,T13,T27
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T53,T13,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T53,T13,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T53,T13,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T53,T13,T15
1	0	Covered	T43,T53,T13
1	1	Covered	T53,T13,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T53,T13,T15
0	1	Covered	T44,T48,T105
1	0	Covered	T79,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T53,T13,T15
0	1	Covered	T53,T13,T15
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T53,T13,T15
1	-	Covered	T53,T13,T15

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T53,T13,T15
0	1	Covered	T53,T13,T15
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T53,T13,T15
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T53,T13,T15
IdleSt	0	-	-	-	-	-	-	Covered	T41,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T53,T13,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T21,T22
DebounceSt	-	0	0	-	-	-	-	Covered	T53,T13,T15
DetectSt	-	-	-	-	1	-	-	Covered	T44,T48,T105
DetectSt	-	-	-	-	0	1	-	Covered	T53,T13,T15
DetectSt	-	-	-	-	0	0	-	Covered	T53,T13,T15
StableSt	-	-	-	-	-	-	1	Covered	T53,T13,T15
StableSt	-	-	-	-	-	-	0	Covered	T53,T13,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	1110	0	0
CntIncr_A	10054024	56536	0	0
CntNoWrap_A	10054024	9351607	0	0
DetectStDropOut_A	10054024	78	0	0
DetectedOut_A	10054024	16188	0	0
DetectedPulseOut_A	10054024	426	0	0
DisabledIdleSt_A	10054024	8953756	0	0
DisabledNoDetection_A	10054024	8955449	0	0
EnterDebounceSt_A	10054024	604	0	0
EnterDetectSt_A	10054024	508	0	0
EnterStableSt_A	10054024	426	0	0
PulseIsPulse_A	10054024	426	0	0
StayInStableSt	10054024	15725	0	0
gen_high_level_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	388	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1110	0	0
T13	31225	20	0	0
T14	1549	0	0	0
T15	0	6	0	0
T21	0	31	0	0
T22	0	13	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	12	0	0
T53	25658	4	0	0
T58	0	6	0	0
T60	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	56536	0	0
T13	31225	1360	0	0
T14	1549	0	0	0
T15	0	264	0	0
T21	0	1556	0	0
T22	0	685	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T44	0	129	0	0
T45	0	38	0	0
T46	0	330	0	0
T53	25658	212	0	0
T58	0	390	0	0
T60	0	270	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9351607	0	0
T13	31225	30728	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23194	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	78	0	0
T44	104222	1	0	0
T48	29879	1	0	0
T73	80670	0	0	0
T105	26294	1	0	0
T107	0	7	0	0
T108	0	11	0	0
T109	0	13	0	0
T110	0	2	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	4	0	0
T115	423	0	0	0
T116	409	0	0	0
T119	559	0	0	0
T120	865	0	0	0
T121	506	0	0	0
T122	720	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	16188	0	0
T13	31225	287	0	0
T14	1549	0	0	0
T15	0	111	0	0
T21	0	439	0	0
T22	0	22	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T45	0	68	0	0
T46	0	467	0	0
T53	25658	138	0	0
T58	0	211	0	0
T60	0	131	0	0
T61	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	426	0	0
T13	31225	8	0	0
T14	1549	0	0	0
T15	0	3	0	0
T21	0	15	0	0
T22	0	5	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T45	0	1	0	0
T46	0	6	0	0
T53	25658	2	0	0
T58	0	3	0	0
T60	0	3	0	0
T61	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8953756	0	0
T13	31225	26190	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	18622	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8955449	0	0
T13	31225	26190	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	18626	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	604	0	0
T13	31225	12	0	0
T14	1549	0	0	0
T15	0	3	0	0
T21	0	16	0	0
T22	0	8	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	6	0	0
T53	25658	2	0	0
T58	0	3	0	0
T60	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	508	0	0
T13	31225	8	0	0
T14	1549	0	0	0
T15	0	3	0	0
T21	0	15	0	0
T22	0	5	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	6	0	0
T53	25658	2	0	0
T58	0	3	0	0
T60	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	426	0	0
T13	31225	8	0	0
T14	1549	0	0	0
T15	0	3	0	0
T21	0	15	0	0
T22	0	5	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T45	0	1	0	0
T46	0	6	0	0
T53	25658	2	0	0
T58	0	3	0	0
T60	0	3	0	0
T61	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	426	0	0
T13	31225	8	0	0
T14	1549	0	0	0
T15	0	3	0	0
T21	0	15	0	0
T22	0	5	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T45	0	1	0	0
T46	0	6	0	0
T53	25658	2	0	0
T58	0	3	0	0
T60	0	3	0	0
T61	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	15725	0	0
T13	31225	279	0	0
T14	1549	0	0	0
T15	0	106	0	0
T21	0	424	0	0
T22	0	17	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T45	0	67	0	0
T46	0	455	0	0
T53	25658	136	0	0
T58	0	208	0	0
T60	0	128	0	0
T61	0	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	388	0	0
T13	31225	8	0	0
T14	1549	0	0	0
T15	0	1	0	0
T21	0	15	0	0
T22	0	5	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T45	0	1	0	0
T53	25658	2	0	0
T58	0	3	0	0
T60	0	3	0	0
T61	0	1	0	0
T62	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T28,T15
1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T15
1	0	Covered	T28,T15,T46
1	1	Covered	T27,T28,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T15
0	1	Covered	T27,T28,T55
1	0	Covered	T28,T102,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T46,T54
0	1	Covered	T15,T46,T54
1	0	Covered	T60,T249

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T46,T54
1	-	Covered	T15,T46,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T28,T15
0	1	Covered	T27,T28,T15
0	0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T15
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T28,T15
IdleSt	0	-	-	-	-	-	-	Covered	T27,T28,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T28,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T95,T79,T245
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T28,T15
DetectSt	-	-	-	-	1	-	-	Covered	T27,T28,T102
DetectSt	-	-	-	-	0	1	-	Covered	T15,T46,T54
DetectSt	-	-	-	-	0	0	-	Covered	T27,T28,T15
StableSt	-	-	-	-	-	-	1	Covered	T15,T46,T54
StableSt	-	-	-	-	-	-	0	Covered	T15,T46,T54
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	2829	0	0
CntIncr_A	10054024	116288	0	0
CntNoWrap_A	10054024	9349888	0	0
DetectStDropOut_A	10054024	382	0	0
DetectedOut_A	10054024	62827	0	0
DetectedPulseOut_A	10054024	785	0	0
DisabledIdleSt_A	10054024	8885389	0	0
DisabledNoDetection_A	10054024	8887767	0	0
EnterDebounceSt_A	10054024	1443	0	0
EnterDetectSt_A	10054024	1387	0	0
EnterStableSt_A	10054024	785	0	0
PulseIsPulse_A	10054024	785	0	0
StayInStableSt	10054024	61953	0	0
gen_high_event_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_high_level_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	672	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	2829	0	0
T15	20268	8	0	0
T16	8040	0	0	0
T27	5215	22	0	0
T28	7302	54	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	52	0	0
T46	33711	30	0	0
T54	0	58	0	0
T55	0	42	0	0
T56	0	14	0	0
T60	0	38	0	0
T64	496	0	0	0
T102	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	116288	0	0
T15	20268	240	0	0
T16	8040	0	0	0
T27	5215	565	0	0
T28	7302	1685	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	1144	0	0
T46	33711	1215	0	0
T54	0	1885	0	0
T55	0	1125	0	0
T56	0	623	0	0
T60	0	988	0	0
T64	496	0	0	0
T102	0	251	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9349888	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	382	0	0
T15	20268	0	0	0
T16	8040	0	0	0
T27	5215	11	0	0
T28	7302	18	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T55	10596	7	0	0
T64	496	0	0	0
T79	0	1	0	0
T103	0	22	0	0
T104	0	11	0	0
T246	0	8	0	0
T247	0	14	0	0
T250	0	10	0	0
T251	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	62827	0	0
T15	20268	428	0	0
T16	8040	0	0	0
T45	8816	1637	0	0
T46	33711	1675	0	0
T47	0	1275	0	0
T49	1140	0	0	0
T54	27456	3190	0	0
T56	0	461	0	0
T60	0	440	0	0
T64	496	0	0	0
T95	0	14	0	0
T130	643	0	0	0
T143	0	510	0	0
T182	522	0	0	0
T183	402	0	0	0
T248	0	456	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	785	0	0
T15	20268	4	0	0
T16	8040	0	0	0
T45	8816	26	0	0
T46	33711	15	0	0
T47	0	25	0	0
T49	1140	0	0	0
T54	27456	29	0	0
T56	0	7	0	0
T60	0	19	0	0
T64	496	0	0	0
T95	0	1	0	0
T130	643	0	0	0
T143	0	7	0	0
T182	522	0	0	0
T183	402	0	0	0
T248	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8885389	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8887767	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1443	0	0
T15	20268	4	0	0
T16	8040	0	0	0
T27	5215	11	0	0
T28	7302	27	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	26	0	0
T46	33711	15	0	0
T54	0	29	0	0
T55	0	21	0	0
T56	0	7	0	0
T60	0	19	0	0
T64	496	0	0	0
T102	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1387	0	0
T15	20268	4	0	0
T16	8040	0	0	0
T27	5215	11	0	0
T28	7302	27	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	26	0	0
T46	33711	15	0	0
T54	0	29	0	0
T55	0	21	0	0
T56	0	7	0	0
T60	0	19	0	0
T64	496	0	0	0
T102	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	785	0	0
T15	20268	4	0	0
T16	8040	0	0	0
T45	8816	26	0	0
T46	33711	15	0	0
T47	0	25	0	0
T49	1140	0	0	0
T54	27456	29	0	0
T56	0	7	0	0
T60	0	19	0	0
T64	496	0	0	0
T95	0	1	0	0
T130	643	0	0	0
T143	0	7	0	0
T182	522	0	0	0
T183	402	0	0	0
T248	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	785	0	0
T15	20268	4	0	0
T16	8040	0	0	0
T45	8816	26	0	0
T46	33711	15	0	0
T47	0	25	0	0
T49	1140	0	0	0
T54	27456	29	0	0
T56	0	7	0	0
T60	0	19	0	0
T64	496	0	0	0
T95	0	1	0	0
T130	643	0	0	0
T143	0	7	0	0
T182	522	0	0	0
T183	402	0	0	0
T248	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	61953	0	0
T15	20268	421	0	0
T16	8040	0	0	0
T45	8816	1610	0	0
T46	33711	1655	0	0
T47	0	1248	0	0
T49	1140	0	0	0
T54	27456	3152	0	0
T56	0	453	0	0
T60	0	421	0	0
T64	496	0	0	0
T95	0	13	0	0
T130	643	0	0	0
T143	0	502	0	0
T182	522	0	0	0
T183	402	0	0	0
T248	0	451	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	672	0	0
T15	20268	1	0	0
T16	8040	0	0	0
T45	8816	25	0	0
T46	33711	10	0	0
T47	0	23	0	0
T49	1140	0	0	0
T54	27456	20	0	0
T56	0	6	0	0
T60	0	9	0	0
T64	496	0	0	0
T95	0	1	0	0
T130	643	0	0	0
T143	0	6	0	0
T182	522	0	0	0
T183	402	0	0	0
T248	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T53,T13,T27
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T53,T13,T27
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T13,T15,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T13,T15,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T13,T15,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T53,T13,T15
1	0	Covered	T43,T53,T13
1	1	Covered	T13,T15,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T21
0	1	Covered	T13,T21,T252
1	0	Covered	T79,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T22,T46
0	1	Covered	T15,T22,T46
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T22,T46
1	-	Covered	T15,T22,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T15,T21
0	1	Covered	T13,T15,T21
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T21
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T15,T21
IdleSt	0	-	-	-	-	-	-	Covered	T41,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T15,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T21,T45
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T15,T21
DetectSt	-	-	-	-	1	-	-	Covered	T13,T21,T252
DetectSt	-	-	-	-	0	1	-	Covered	T15,T22,T46
DetectSt	-	-	-	-	0	0	-	Covered	T13,T15,T21
StableSt	-	-	-	-	-	-	1	Covered	T15,T22,T46
StableSt	-	-	-	-	-	-	0	Covered	T15,T22,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	870	0	0
CntIncr_A	10054024	47965	0	0
CntNoWrap_A	10054024	9351847	0	0
DetectStDropOut_A	10054024	73	0	0
DetectedOut_A	10054024	14278	0	0
DetectedPulseOut_A	10054024	335	0	0
DisabledIdleSt_A	10054024	8963916	0	0
DisabledNoDetection_A	10054024	8965715	0	0
EnterDebounceSt_A	10054024	458	0	0
EnterDetectSt_A	10054024	412	0	0
EnterStableSt_A	10054024	335	0	0
PulseIsPulse_A	10054024	335	0	0
StayInStableSt	10054024	13918	0	0
gen_high_level_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	308	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	870	0	0
T13	31225	28	0	0
T14	1549	0	0	0
T15	0	2	0	0
T21	0	15	0	0
T22	0	4	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	5	0	0
T46	0	4	0	0
T54	0	18	0	0
T143	0	2	0	0
T215	0	1	0	0
T253	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	47965	0	0
T13	31225	2314	0	0
T14	1549	0	0	0
T15	0	63	0	0
T21	0	958	0	0
T22	0	196	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	161	0	0
T46	0	168	0	0
T54	0	792	0	0
T143	0	59	0	0
T215	0	91	0	0
T253	0	228	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9351847	0	0
T13	31225	30720	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	73	0	0
T13	31225	12	0	0
T14	1549	0	0	0
T21	0	7	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T113	0	3	0	0
T174	0	6	0	0
T179	0	4	0	0
T201	0	1	0	0
T252	0	6	0	0
T254	0	15	0	0
T255	0	6	0	0
T256	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	14278	0	0
T15	20268	63	0	0
T16	8040	0	0	0
T22	54529	113	0	0
T44	104222	0	0	0
T45	0	77	0	0
T46	0	98	0	0
T47	0	51	0	0
T48	0	91	0	0
T52	54799	0	0	0
T54	0	546	0	0
T64	496	0	0	0
T94	1556	0	0	0
T96	692	0	0	0
T115	423	0	0	0
T143	0	92	0	0
T145	0	232	0	0
T171	451	0	0	0
T253	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	335	0	0
T15	20268	1	0	0
T16	8040	0	0	0
T22	54529	2	0	0
T44	104222	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T52	54799	0	0	0
T54	0	9	0	0
T64	496	0	0	0
T94	1556	0	0	0
T96	692	0	0	0
T115	423	0	0	0
T143	0	1	0	0
T145	0	5	0	0
T171	451	0	0	0
T253	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8963916	0	0
T13	31225	26190	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	18622	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8965715	0	0
T13	31225	26190	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	18626	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	458	0	0
T13	31225	16	0	0
T14	1549	0	0	0
T15	0	1	0	0
T21	0	8	0	0
T22	0	2	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	3	0	0
T46	0	2	0	0
T54	0	9	0	0
T143	0	1	0	0
T215	0	1	0	0
T253	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	412	0	0
T13	31225	12	0	0
T14	1549	0	0	0
T15	0	1	0	0
T21	0	7	0	0
T22	0	2	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T54	0	9	0	0
T143	0	1	0	0
T253	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	335	0	0
T15	20268	1	0	0
T16	8040	0	0	0
T22	54529	2	0	0
T44	104222	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T52	54799	0	0	0
T54	0	9	0	0
T64	496	0	0	0
T94	1556	0	0	0
T96	692	0	0	0
T115	423	0	0	0
T143	0	1	0	0
T145	0	5	0	0
T171	451	0	0	0
T253	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	335	0	0
T15	20268	1	0	0
T16	8040	0	0	0
T22	54529	2	0	0
T44	104222	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T52	54799	0	0	0
T54	0	9	0	0
T64	496	0	0	0
T94	1556	0	0	0
T96	692	0	0	0
T115	423	0	0	0
T143	0	1	0	0
T145	0	5	0	0
T171	451	0	0	0
T253	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	13918	0	0
T15	20268	62	0	0
T16	8040	0	0	0
T22	54529	111	0	0
T44	104222	0	0	0
T45	0	75	0	0
T46	0	96	0	0
T47	0	50	0	0
T48	0	90	0	0
T52	54799	0	0	0
T54	0	528	0	0
T64	496	0	0	0
T94	1556	0	0	0
T96	692	0	0	0
T115	423	0	0	0
T143	0	91	0	0
T145	0	227	0	0
T171	451	0	0	0
T253	0	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	308	0	0
T15	20268	1	0	0
T16	8040	0	0	0
T22	54529	2	0	0
T44	104222	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T52	54799	0	0	0
T64	496	0	0	0
T94	1556	0	0	0
T96	692	0	0	0
T115	423	0	0	0
T143	0	1	0	0
T145	0	5	0	0
T171	451	0	0	0
T253	0	2	0	0
T257	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T28,T15
1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T15
1	0	Covered	T28,T15,T46
1	1	Covered	T27,T28,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T15
0	1	Covered	T27,T28,T15
1	0	Covered	T28,T15,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T46,T55,T56
0	1	Covered	T46,T55,T56
1	0	Covered	T84,T258

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T46,T55,T56
1	-	Covered	T46,T55,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T28,T15
0	1	Covered	T27,T28,T15
0	0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T15
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T28,T15
IdleSt	0	-	-	-	-	-	-	Covered	T27,T28,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T28,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T95,T79,T245
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T28,T15
DetectSt	-	-	-	-	1	-	-	Covered	T27,T28,T15
DetectSt	-	-	-	-	0	1	-	Covered	T46,T55,T56
DetectSt	-	-	-	-	0	0	-	Covered	T27,T28,T15
StableSt	-	-	-	-	-	-	1	Covered	T46,T55,T56
StableSt	-	-	-	-	-	-	0	Covered	T46,T55,T56
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	2892	0	0
CntIncr_A	10054024	104468	0	0
CntNoWrap_A	10054024	9349825	0	0
DetectStDropOut_A	10054024	360	0	0
DetectedOut_A	10054024	80436	0	0
DetectedPulseOut_A	10054024	857	0	0
DisabledIdleSt_A	10054024	8874246	0	0
DisabledNoDetection_A	10054024	8876614	0	0
EnterDebounceSt_A	10054024	1471	0	0
EnterDetectSt_A	10054024	1423	0	0
EnterStableSt_A	10054024	857	0	0
PulseIsPulse_A	10054024	857	0	0
StayInStableSt	10054024	79480	0	0
gen_high_event_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_high_level_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	754	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	2892	0	0
T15	20268	24	0	0
T16	8040	0	0	0
T27	5215	22	0	0
T28	7302	36	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	48	0	0
T46	33711	58	0	0
T54	0	16	0	0
T55	0	28	0	0
T56	0	10	0	0
T60	0	38	0	0
T64	496	0	0	0
T102	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	104468	0	0
T15	20268	815	0	0
T16	8040	0	0	0
T27	5215	565	0	0
T28	7302	1115	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	1385	0	0
T46	33711	2059	0	0
T54	0	583	0	0
T55	0	672	0	0
T56	0	440	0	0
T60	0	1428	0	0
T64	496	0	0	0
T102	0	1161	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9349825	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	360	0	0
T15	20268	8	0	0
T16	8040	0	0	0
T27	5215	11	0	0
T28	7302	11	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	7	0	0
T54	27456	5	0	0
T60	0	9	0	0
T64	496	0	0	0
T79	0	1	0	0
T102	0	12	0	0
T103	0	9	0	0
T104	0	21	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	80436	0	0
T45	8816	0	0	0
T46	33711	3321	0	0
T47	0	2234	0	0
T49	1140	0	0	0
T54	27456	0	0	0
T55	0	784	0	0
T56	0	517	0	0
T79	0	400	0	0
T130	643	0	0	0
T143	0	159	0	0
T182	522	0	0	0
T183	402	0	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T246	0	1941	0	0
T248	0	960	0	0
T259	0	1288	0	0
T260	0	2128	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	857	0	0
T45	8816	0	0	0
T46	33711	29	0	0
T47	0	25	0	0
T49	1140	0	0	0
T54	27456	0	0	0
T55	0	14	0	0
T56	0	5	0	0
T79	0	5	0	0
T130	643	0	0	0
T143	0	4	0	0
T182	522	0	0	0
T183	402	0	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T246	0	15	0	0
T248	0	20	0	0
T259	0	13	0	0
T260	0	30	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8874246	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8876614	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1471	0	0
T15	20268	12	0	0
T16	8040	0	0	0
T27	5215	11	0	0
T28	7302	18	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	24	0	0
T46	33711	29	0	0
T54	0	8	0	0
T55	0	14	0	0
T56	0	5	0	0
T60	0	19	0	0
T64	496	0	0	0
T102	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1423	0	0
T15	20268	12	0	0
T16	8040	0	0	0
T27	5215	11	0	0
T28	7302	18	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	24	0	0
T46	33711	29	0	0
T54	0	8	0	0
T55	0	14	0	0
T56	0	5	0	0
T60	0	19	0	0
T64	496	0	0	0
T102	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	857	0	0
T45	8816	0	0	0
T46	33711	29	0	0
T47	0	25	0	0
T49	1140	0	0	0
T54	27456	0	0	0
T55	0	14	0	0
T56	0	5	0	0
T79	0	5	0	0
T130	643	0	0	0
T143	0	4	0	0
T182	522	0	0	0
T183	402	0	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T246	0	15	0	0
T248	0	20	0	0
T259	0	13	0	0
T260	0	30	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	857	0	0
T45	8816	0	0	0
T46	33711	29	0	0
T47	0	25	0	0
T49	1140	0	0	0
T54	27456	0	0	0
T55	0	14	0	0
T56	0	5	0	0
T79	0	5	0	0
T130	643	0	0	0
T143	0	4	0	0
T182	522	0	0	0
T183	402	0	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T246	0	15	0	0
T248	0	20	0	0
T259	0	13	0	0
T260	0	30	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	79480	0	0
T45	8816	0	0	0
T46	33711	3285	0	0
T47	0	2208	0	0
T49	1140	0	0	0
T54	27456	0	0	0
T55	0	769	0	0
T56	0	510	0	0
T79	0	395	0	0
T130	643	0	0	0
T143	0	155	0	0
T182	522	0	0	0
T183	402	0	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T246	0	1926	0	0
T248	0	939	0	0
T259	0	1272	0	0
T260	0	2090	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	754	0	0
T45	8816	0	0	0
T46	33711	22	0	0
T47	0	24	0	0
T49	1140	0	0	0
T54	27456	0	0	0
T55	0	13	0	0
T56	0	3	0	0
T79	0	5	0	0
T130	643	0	0	0
T143	0	4	0	0
T182	522	0	0	0
T183	402	0	0	0
T191	1106	0	0	0
T192	502	0	0	0
T193	403	0	0	0
T246	0	15	0	0
T248	0	19	0	0
T259	0	10	0	0
T260	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T53,T13,T27
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T53,T13,T27
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T53,T13,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T53,T13,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T53,T13,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T53,T13,T21
1	0	Covered	T43,T53,T13
1	1	Covered	T53,T13,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T53,T13,T21
0	1	Covered	T22,T253,T252
1	0	Covered	T79,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T53,T13,T21
0	1	Covered	T53,T13,T21
1	0	Covered	T79,T81

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T53,T13,T21
1	-	Covered	T53,T13,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T53,T13,T21
0	1	Covered	T53,T13,T21
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T53,T13,T21
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T53,T13,T21
IdleSt	0	-	-	-	-	-	-	Covered	T41,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T53,T13,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T46,T257
DebounceSt	-	0	0	-	-	-	-	Covered	T53,T13,T21
DetectSt	-	-	-	-	1	-	-	Covered	T22,T253,T252
DetectSt	-	-	-	-	0	1	-	Covered	T53,T13,T21
DetectSt	-	-	-	-	0	0	-	Covered	T53,T13,T21
StableSt	-	-	-	-	-	-	1	Covered	T53,T13,T21
StableSt	-	-	-	-	-	-	0	Covered	T53,T13,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	865	0	0
CntIncr_A	10054024	47675	0	0
CntNoWrap_A	10054024	9351852	0	0
DetectStDropOut_A	10054024	91	0	0
DetectedOut_A	10054024	14534	0	0
DetectedPulseOut_A	10054024	309	0	0
DisabledIdleSt_A	10054024	8951459	0	0
DisabledNoDetection_A	10054024	8953250	0	0
EnterDebounceSt_A	10054024	463	0	0
EnterDetectSt_A	10054024	404	0	0
EnterStableSt_A	10054024	308	0	0
PulseIsPulse_A	10054024	308	0	0
StayInStableSt	10054024	14199	0	0
gen_high_level_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	278	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	865	0	0
T13	31225	6	0	0
T14	1549	0	0	0
T21	0	15	0	0
T22	0	24	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T46	0	6	0	0
T48	0	2	0	0
T53	25658	4	0	0
T55	0	2	0	0
T56	0	4	0	0
T145	0	8	0	0
T253	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	47675	0	0
T13	31225	288	0	0
T14	1549	0	0	0
T21	0	924	0	0
T22	0	1864	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T46	0	162	0	0
T48	0	199	0	0
T53	25658	320	0	0
T55	0	30	0	0
T56	0	190	0	0
T145	0	392	0	0
T253	0	236	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9351852	0	0
T13	31225	30742	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23194	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	91	0	0
T22	54529	12	0	0
T44	104222	0	0	0
T52	54799	0	0	0
T74	0	3	0	0
T88	0	3	0	0
T94	1556	0	0	0
T96	692	0	0	0
T110	0	11	0	0
T115	423	0	0	0
T116	409	0	0	0
T171	451	0	0	0
T252	0	1	0	0
T253	12189	2	0	0
T254	0	3	0	0
T261	0	2	0	0
T262	0	4	0	0
T263	0	4	0	0
T264	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	14534	0	0
T13	31225	206	0	0
T14	1549	0	0	0
T21	0	34	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T46	0	170	0	0
T48	0	5	0	0
T53	25658	30	0	0
T55	0	64	0	0
T56	0	93	0	0
T145	0	346	0	0
T248	0	65	0	0
T257	0	50	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	309	0	0
T13	31225	3	0	0
T14	1549	0	0	0
T21	0	7	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T46	0	2	0	0
T48	0	1	0	0
T53	25658	2	0	0
T55	0	1	0	0
T56	0	2	0	0
T145	0	4	0	0
T248	0	1	0	0
T257	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8951459	0	0
T13	31225	26190	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	18622	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8953250	0	0
T13	31225	26190	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	18626	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	463	0	0
T13	31225	3	0	0
T14	1549	0	0	0
T21	0	8	0	0
T22	0	12	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T46	0	4	0	0
T48	0	1	0	0
T53	25658	2	0	0
T55	0	1	0	0
T56	0	2	0	0
T145	0	4	0	0
T253	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	404	0	0
T13	31225	3	0	0
T14	1549	0	0	0
T21	0	7	0	0
T22	0	12	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T46	0	2	0	0
T48	0	1	0	0
T53	25658	2	0	0
T55	0	1	0	0
T56	0	2	0	0
T145	0	4	0	0
T253	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	308	0	0
T13	31225	3	0	0
T14	1549	0	0	0
T21	0	7	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T46	0	2	0	0
T48	0	1	0	0
T53	25658	2	0	0
T55	0	1	0	0
T56	0	2	0	0
T145	0	4	0	0
T248	0	1	0	0
T257	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	308	0	0
T13	31225	3	0	0
T14	1549	0	0	0
T21	0	7	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T46	0	2	0	0
T48	0	1	0	0
T53	25658	2	0	0
T55	0	1	0	0
T56	0	2	0	0
T145	0	4	0	0
T248	0	1	0	0
T257	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	14199	0	0
T13	31225	203	0	0
T14	1549	0	0	0
T21	0	27	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T46	0	166	0	0
T48	0	4	0	0
T53	25658	28	0	0
T55	0	62	0	0
T56	0	90	0	0
T145	0	342	0	0
T248	0	64	0	0
T257	0	49	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	278	0	0
T13	31225	3	0	0
T14	1549	0	0	0
T21	0	7	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T48	0	1	0	0
T53	25658	2	0	0
T56	0	1	0	0
T74	0	2	0	0
T145	0	4	0	0
T248	0	1	0	0
T257	0	1	0	0
T265	0	5	0	0