Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T27,T28,T15
1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T27,T28,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T28,T15
1	0	Covered	T15,T46,T54
1	1	Covered	T27,T28,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T15
0	1	Covered	T27,T60,T103
1	0	Covered	T54,T60,T47

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T15,T46
0	1	Covered	T28,T15,T46
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T15,T46
1	-	Covered	T28,T15,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T28,T15
0	1	Covered	T27,T28,T15
0	0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T15
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T27,T28,T15
IdleSt	0	-	-	-	-	-	-	Covered	T27,T28,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T28,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T95,T79,T245
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T28,T15
DetectSt	-	-	-	-	1	-	-	Covered	T27,T54,T60
DetectSt	-	-	-	-	0	1	-	Covered	T28,T15,T46
DetectSt	-	-	-	-	0	0	-	Covered	T27,T28,T15
StableSt	-	-	-	-	-	-	1	Covered	T28,T15,T46
StableSt	-	-	-	-	-	-	0	Covered	T28,T15,T46
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	3072	0	0
CntIncr_A	10054024	111270	0	0
CntNoWrap_A	10054024	9349645	0	0
DetectStDropOut_A	10054024	393	0	0
DetectedOut_A	10054024	100738	0	0
DetectedPulseOut_A	10054024	1011	0	0
DisabledIdleSt_A	10054024	8861706	0	0
DisabledNoDetection_A	10054024	8864074	0	0
EnterDebounceSt_A	10054024	1550	0	0
EnterDetectSt_A	10054024	1523	0	0
EnterStableSt_A	10054024	1011	0	0
PulseIsPulse_A	10054024	1011	0	0
StayInStableSt	10054024	99628	0	0
gen_high_event_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_high_level_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	912	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	3072	0	0
T15	20268	18	0	0
T16	8040	0	0	0
T27	5215	18	0	0
T28	7302	44	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	14	0	0
T46	33711	46	0	0
T54	0	24	0	0
T55	0	20	0	0
T56	0	36	0	0
T60	0	16	0	0
T64	496	0	0	0
T102	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	111270	0	0
T15	20268	450	0	0
T16	8040	0	0	0
T27	5215	461	0	0
T28	7302	1122	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	399	0	0
T46	33711	1426	0	0
T54	0	887	0	0
T55	0	360	0	0
T56	0	1278	0	0
T60	0	599	0	0
T64	496	0	0	0
T102	0	864	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9349645	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	393	0	0
T15	20268	0	0	0
T16	8040	0	0	0
T27	5215	9	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T60	7822	5	0	0
T64	496	0	0	0
T79	0	1	0	0
T103	0	12	0	0
T104	0	25	0	0
T246	0	7	0	0
T247	0	13	0	0
T266	0	16	0	0
T267	0	23	0	0
T268	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	100738	0	0
T15	20268	2260	0	0
T16	8040	0	0	0
T28	7302	1819	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	130	0	0
T46	33711	2561	0	0
T55	0	294	0	0
T56	0	3020	0	0
T64	496	0	0	0
T95	0	37	0	0
T102	0	1629	0	0
T130	643	0	0	0
T143	0	2952	0	0
T248	0	1338	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1011	0	0
T15	20268	9	0	0
T16	8040	0	0	0
T28	7302	22	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	7	0	0
T46	33711	23	0	0
T55	0	10	0	0
T56	0	18	0	0
T64	496	0	0	0
T95	0	3	0	0
T102	0	24	0	0
T130	643	0	0	0
T143	0	21	0	0
T248	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8861706	0	0
T13	31225	30748	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23198	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8864074	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1550	0	0
T15	20268	9	0	0
T16	8040	0	0	0
T27	5215	9	0	0
T28	7302	22	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	7	0	0
T46	33711	23	0	0
T54	0	12	0	0
T55	0	10	0	0
T56	0	18	0	0
T60	0	8	0	0
T64	496	0	0	0
T102	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1523	0	0
T15	20268	9	0	0
T16	8040	0	0	0
T27	5215	9	0	0
T28	7302	22	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	7	0	0
T46	33711	23	0	0
T54	0	12	0	0
T55	0	10	0	0
T56	0	18	0	0
T60	0	8	0	0
T64	496	0	0	0
T102	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1011	0	0
T15	20268	9	0	0
T16	8040	0	0	0
T28	7302	22	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	7	0	0
T46	33711	23	0	0
T55	0	10	0	0
T56	0	18	0	0
T64	496	0	0	0
T95	0	3	0	0
T102	0	24	0	0
T130	643	0	0	0
T143	0	21	0	0
T248	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1011	0	0
T15	20268	9	0	0
T16	8040	0	0	0
T28	7302	22	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	7	0	0
T46	33711	23	0	0
T55	0	10	0	0
T56	0	18	0	0
T64	496	0	0	0
T95	0	3	0	0
T102	0	24	0	0
T130	643	0	0	0
T143	0	21	0	0
T248	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	99628	0	0
T15	20268	2245	0	0
T16	8040	0	0	0
T28	7302	1797	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	122	0	0
T46	33711	2532	0	0
T55	0	284	0	0
T56	0	2999	0	0
T64	496	0	0	0
T95	0	34	0	0
T102	0	1605	0	0
T130	643	0	0	0
T143	0	2930	0	0
T248	0	1326	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	912	0	0
T15	20268	3	0	0
T16	8040	0	0	0
T28	7302	22	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T32	1495	0	0	0
T45	0	6	0	0
T46	33711	17	0	0
T55	0	10	0	0
T56	0	15	0	0
T64	496	0	0	0
T95	0	3	0	0
T102	0	24	0	0
T130	643	0	0	0
T143	0	20	0	0
T248	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T53,T13,T27
1	Covered	T41,T42,T43

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T53,T13,T27
1	0	Covered	T41,T42,T43
1	1	Covered	T41,T42,T43

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T53,T13,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T42,T43	VC_COV_UNR
1	Covered	T53,T13,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T42,T43
1	Covered	T53,T13,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T53,T13,T28
1	0	Covered	T43,T53,T13
1	1	Covered	T53,T13,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T53,T13,T15
0	1	Covered	T21,T72,T257
1	0	Covered	T79,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T53,T13,T15
0	1	Covered	T53,T13,T15
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T53,T13,T15
1	-	Covered	T53,T13,T15

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T53,T13,T15
0	1	Covered	T53,T13,T15
0	0	Excluded	T41,T42,T43	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T53,T13,T15
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T53,T13,T15
IdleSt	0	-	-	-	-	-	-	Covered	T41,T42,T43
DebounceSt	-	1	-	-	-	-	-	Covered	T79,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T53,T13,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T13,T102
DebounceSt	-	0	0	-	-	-	-	Covered	T53,T13,T15
DetectSt	-	-	-	-	1	-	-	Covered	T21,T72,T257
DetectSt	-	-	-	-	0	1	-	Covered	T53,T13,T15
DetectSt	-	-	-	-	0	0	-	Covered	T53,T13,T15
StableSt	-	-	-	-	-	-	1	Covered	T53,T13,T15
StableSt	-	-	-	-	-	-	0	Covered	T53,T13,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T41,T42,T43

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10054024	1010	0	0
CntIncr_A	10054024	58334	0	0
CntNoWrap_A	10054024	9351707	0	0
DetectStDropOut_A	10054024	78	0	0
DetectedOut_A	10054024	19220	0	0
DetectedPulseOut_A	10054024	393	0	0
DisabledIdleSt_A	10054024	8932089	0	0
DisabledNoDetection_A	10054024	8933883	0	0
EnterDebounceSt_A	10054024	537	0	0
EnterDetectSt_A	10054024	476	0	0
EnterStableSt_A	10054024	393	0	0
PulseIsPulse_A	10054024	393	0	0
StayInStableSt	10054024	18810	0	0
gen_high_level_sva.HighLevelEvent_A	10054024	9355272	0	0
gen_not_sticky_sva.StableStDropOut_A	10054024	374	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	1010	0	0
T13	31225	28	0	0
T14	1549	0	0	0
T15	0	8	0	0
T21	0	10	0	0
T22	0	2	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	8	0	0
T53	25658	17	0	0
T58	0	4	0	0
T102	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	58334	0	0
T13	31225	2224	0	0
T14	1549	0	0	0
T15	0	252	0	0
T21	0	643	0	0
T22	0	87	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T44	0	122	0	0
T45	0	60	0	0
T46	0	224	0	0
T53	25658	1288	0	0
T58	0	390	0	0
T102	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9351707	0	0
T13	31225	30720	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	23181	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	78	0	0
T21	36975	5	0	0
T22	54529	0	0	0
T44	104222	0	0	0
T52	54799	0	0	0
T72	19131	4	0	0
T79	0	1	0	0
T94	1556	0	0	0
T96	692	0	0	0
T105	0	11	0	0
T107	0	3	0	0
T115	423	0	0	0
T116	409	0	0	0
T171	451	0	0	0
T254	0	4	0	0
T257	0	2	0	0
T262	0	2	0	0
T269	0	3	0	0
T270	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	19220	0	0
T13	31225	90	0	0
T14	1549	0	0	0
T15	0	250	0	0
T22	0	67	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T44	0	7	0	0
T45	0	46	0	0
T46	0	308	0	0
T53	25658	219	0	0
T58	0	10	0	0
T102	0	51	0	0
T253	0	105	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	393	0	0
T13	31225	12	0	0
T14	1549	0	0	0
T15	0	4	0	0
T22	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	4	0	0
T53	25658	8	0	0
T58	0	2	0	0
T102	0	1	0	0
T253	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8932089	0	0
T13	31225	26190	0	0
T14	1549	1148	0	0
T25	490	89	0	0
T41	690	289	0	0
T42	148141	147740	0	0
T43	8431	13	0	0
T53	25658	18622	0	0
T75	496	95	0	0
T85	522	121	0	0
T86	518	117	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	8933883	0	0
T13	31225	26190	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	18626	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	537	0	0
T13	31225	16	0	0
T14	1549	0	0	0
T15	0	4	0	0
T21	0	5	0	0
T22	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	4	0	0
T53	25658	9	0	0
T58	0	2	0	0
T102	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	476	0	0
T13	31225	12	0	0
T14	1549	0	0	0
T15	0	4	0	0
T21	0	5	0	0
T22	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	4	0	0
T53	25658	8	0	0
T58	0	2	0	0
T102	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	393	0	0
T13	31225	12	0	0
T14	1549	0	0	0
T15	0	4	0	0
T22	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	4	0	0
T53	25658	8	0	0
T58	0	2	0	0
T102	0	1	0	0
T253	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	393	0	0
T13	31225	12	0	0
T14	1549	0	0	0
T15	0	4	0	0
T22	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	4	0	0
T53	25658	8	0	0
T58	0	2	0	0
T102	0	1	0	0
T253	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	18810	0	0
T13	31225	78	0	0
T14	1549	0	0	0
T15	0	246	0	0
T22	0	66	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T44	0	6	0	0
T45	0	45	0	0
T46	0	301	0	0
T53	25658	211	0	0
T58	0	8	0	0
T102	0	50	0	0
T253	0	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	9355272	0	0
T13	31225	30761	0	0
T14	1549	1149	0	0
T25	490	90	0	0
T41	690	290	0	0
T42	148141	147741	0	0
T43	8431	31	0	0
T53	25658	23211	0	0
T75	496	96	0	0
T85	522	122	0	0
T86	518	118	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10054024	374	0	0
T13	31225	12	0	0
T14	1549	0	0	0
T15	0	4	0	0
T22	0	1	0	0
T25	490	0	0	0
T26	448	0	0	0
T27	5215	0	0	0
T28	7302	0	0	0
T29	506	0	0	0
T30	423	0	0	0
T31	522	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T53	25658	8	0	0
T58	0	2	0	0
T102	0	1	0	0
T253	0	3	0	0