SYSRST_CTRL Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: 671f2b57e2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 6.550s 2.110ms 50 50 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 8.070s 2.467ms 50 50 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 6.470s 2.219ms 5 5 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 7.310s 2.512ms 5 5 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 16.980s 6.026ms 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 6.490s 2.044ms 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 1.090m 14.049ms 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 10.170s 2.714ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.560s 2.069ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 6.490s 2.044ms 20 20 100.00
sysrst_ctrl_csr_aliasing 10.170s 2.714ms 5 5 100.00
V1 TOTAL 165 165 100.00
V2 combo_detect sysrst_ctrl_combo_detect 9.031m 196.001ms 50 50 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 6.520m 151.662ms 94 100 94.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 5.394m 131.373ms 49 50 98.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 24.452m 1.706s 50 50 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 7.610s 2.515ms 50 50 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 6.450s 2.223ms 50 50 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 5.030m 607.289ms 50 50 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 7.720s 2.612ms 50 50 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 3.893m 707.241ms 48 50 96.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 1.800m 41.729ms 2 2 100.00
V2 stress_all sysrst_ctrl_stress_all 37.803m 887.965ms 48 50 96.00
V2 alert_test sysrst_ctrl_alert_test 6.180s 2.012ms 50 50 100.00
V2 intr_test sysrst_ctrl_intr_test 6.260s 2.013ms 50 50 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 8.590s 2.148ms 20 20 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 8.590s 2.148ms 20 20 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 16.980s 6.026ms 5 5 100.00
sysrst_ctrl_csr_rw 6.490s 2.044ms 20 20 100.00
sysrst_ctrl_csr_aliasing 10.170s 2.714ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 45.140s 9.819ms 20 20 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 16.980s 6.026ms 5 5 100.00
sysrst_ctrl_csr_rw 6.490s 2.044ms 20 20 100.00
sysrst_ctrl_csr_aliasing 10.170s 2.714ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 45.140s 9.819ms 20 20 100.00
V2 TOTAL 681 692 98.41
V2S tl_intg_err sysrst_ctrl_sec_cm 1.843m 42.013ms 5 5 100.00
sysrst_ctrl_tl_intg_err 1.976m 42.498ms 20 20 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.976m 42.498ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 4.330m 778.066ms 42 50 84.00
V3 TOTAL 42 50 84.00
TOTAL 913 932 97.96

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 15 15 11 73.33
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.85 98.96 96.38 100.00 97.44 98.33 99.81 94.03

Failure Buckets

Past Results