Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T26
1	0	Covered	T12,T13,T26
1	1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T85,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T12,T85,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T45,T86

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T85,T45
1	0	Covered	T12,T13,T26
1	1	Covered	T12,T85,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T45,T86
0	1	Covered	T77,T106
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T45,T86
0	1	Covered	T12,T45,T86
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T45,T86
1	-	Covered	T12,T45,T86

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T85,T45
0	1	Covered	T12,T85,T45
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T45,T86
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T85,T45
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T45,T86
DebounceSt	-	0	1	0	-	-	-	Covered	T85,T44,T89
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T85,T45
DetectSt	-	-	-	-	1	-	-	Covered	T77,T106
DetectSt	-	-	-	-	0	1	-	Covered	T12,T45,T86
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T45,T86
StableSt	-	-	-	-	-	-	0	Covered	T12,T45,T86
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	265	0	0
CntIncr_A	8472339	210634	0	0
CntNoWrap_A	8472339	7799045	0	0
DetectStDropOut_A	8472339	2	0	0
DetectedOut_A	8472339	870	0	0
DetectedPulseOut_A	8472339	121	0	0
DisabledIdleSt_A	8472339	7582380	0	0
DisabledNoDetection_A	8472339	7584780	0	0
EnterDebounceSt_A	8472339	144	0	0
EnterDetectSt_A	8472339	123	0	0
EnterStableSt_A	8472339	121	0	0
PulseIsPulse_A	8472339	121	0	0
StayInStableSt	8472339	749	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8472339	6846	0	0
gen_low_level_sva.LowLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	121	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	265	0	0
T12	26790	2	0	0
T13	44225	0	0	0
T14	22532	0	0	0
T15	974	0	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T44	0	1	0	0
T45	0	4	0	0
T62	0	3	0	0
T85	0	2	0	0
T86	0	4	0	0
T87	0	4	0	0
T88	0	2	0	0
T89	0	5	0	0
T90	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	210634	0	0
T12	26790	59	0	0
T13	44225	0	0	0
T14	22532	0	0	0
T15	974	0	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T44	0	2854	0	0
T45	0	86	0	0
T62	0	89	0	0
T85	0	136	0	0
T86	0	92	0	0
T87	0	82	0	0
T88	0	21	0	0
T89	0	164	0	0
T90	0	118	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7799045	0	0
T12	26790	24718	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	2	0	0
T77	615	1	0	0
T106	627	1	0	0
T111	660	0	0	0
T112	402	0	0	0
T113	7912	0	0	0
T114	491	0	0	0
T115	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	870	0	0
T12	26790	10	0	0
T13	44225	0	0	0
T14	22532	0	0	0
T15	974	0	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T45	0	16	0	0
T62	0	8	0	0
T64	0	16	0	0
T86	0	13	0	0
T87	0	15	0	0
T88	0	7	0	0
T89	0	12	0	0
T90	0	18	0	0
T116	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	121	0	0
T12	26790	1	0	0
T13	44225	0	0	0
T14	22532	0	0	0
T15	974	0	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T45	0	2	0	0
T62	0	1	0	0
T64	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	2	0	0
T116	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7582380	0	0
T12	26790	24607	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7584780	0	0
T12	26790	24620	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	144	0	0
T12	26790	1	0	0
T13	44225	0	0	0
T14	22532	0	0	0
T15	974	0	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T62	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	3	0	0
T90	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	123	0	0
T12	26790	1	0	0
T13	44225	0	0	0
T14	22532	0	0	0
T15	974	0	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T45	0	2	0	0
T62	0	1	0	0
T64	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	2	0	0
T116	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	121	0	0
T12	26790	1	0	0
T13	44225	0	0	0
T14	22532	0	0	0
T15	974	0	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T45	0	2	0	0
T62	0	1	0	0
T64	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	2	0	0
T116	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	121	0	0
T12	26790	1	0	0
T13	44225	0	0	0
T14	22532	0	0	0
T15	974	0	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T45	0	2	0	0
T62	0	1	0	0
T64	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	2	0	0
T116	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	749	0	0
T12	26790	9	0	0
T13	44225	0	0	0
T14	22532	0	0	0
T15	974	0	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T45	0	14	0	0
T62	0	7	0	0
T64	0	14	0	0
T86	0	11	0	0
T87	0	13	0	0
T88	0	6	0	0
T89	0	10	0	0
T90	0	16	0	0
T116	0	5	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	6846	0	0
T12	26790	23	0	0
T13	44225	13	0	0
T14	22532	26	0	0
T15	974	1	0	0
T16	0	8	0	0
T17	0	6	0	0
T18	0	13	0	0
T26	407	1	0	0
T27	407	0	0	0
T28	406	1	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T56	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	121	0	0
T12	26790	1	0	0
T13	44225	0	0	0
T14	22532	0	0	0
T15	974	0	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T45	0	2	0	0
T62	0	1	0	0
T64	0	2	0	0
T86	0	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	2	0	0
T90	0	2	0	0
T116	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T26
1	0	Covered	T12,T13,T26
1	1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T16,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T16,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T16,T38,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T38,T39
1	0	Covered	T12,T13,T26
1	1	Covered	T16,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T38,T60
0	1	Covered	T82,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T38,T60
0	1	Unreachable
1	0	Covered	T16,T38,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T38,T39
0	1	Covered	T16,T38,T39
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T38,T60
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T38,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T63,T82
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T38,T39
DetectSt	-	-	-	-	1	-	-	Covered	T82,T83,T84
DetectSt	-	-	-	-	0	1	-	Covered	T16,T38,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T38,T60
StableSt	-	-	-	-	-	-	0	Covered	T16,T38,T60
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	209	0	0
CntIncr_A	8472339	178925	0	0
CntNoWrap_A	8472339	7799101	0	0
DetectStDropOut_A	8472339	18	0	0
DetectedOut_A	8472339	525664	0	0
DetectedPulseOut_A	8472339	57	0	0
DisabledIdleSt_A	8472339	6594961	0	0
DisabledNoDetection_A	8472339	6597407	0	0
EnterDebounceSt_A	8472339	134	0	0
EnterDetectSt_A	8472339	75	0	0
EnterStableSt_A	8472339	57	0	0
PulseIsPulse_A	8472339	57	0	0
StayInStableSt	8472339	525607	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8472339	6846	0	0
gen_low_level_sva.LowLevelEvent_A	8472339	7801758	0	0
gen_sticky_sva.StableStDropOut_A	8472339	492459	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	209	0	0
T16	1830	4	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	2	0	0
T39	0	14	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	2	0	0
T61	0	4	0	0
T62	0	2	0	0
T63	0	8	0	0
T64	0	2	0	0
T65	0	4	0	0
T66	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	178925	0	0
T16	1830	200	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	91	0	0
T39	0	938	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	18	0	0
T61	0	70	0	0
T62	0	59	0	0
T63	0	448	0	0
T64	0	61	0	0
T65	0	129	0	0
T66	0	168	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7799101	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	18	0	0
T82	706	1	0	0
T83	19058	3	0	0
T84	0	4	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	2	0	0
T134	0	2	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	422	0	0	0
T139	421	0	0	0
T140	566	0	0	0
T141	1217	0	0	0
T142	2880	0	0	0
T143	131015	0	0	0
T144	426	0	0	0
T145	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	525664	0	0
T16	1830	356	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	265	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	98	0	0
T61	0	128	0	0
T62	0	120	0	0
T64	0	409	0	0
T65	0	688	0	0
T66	0	779	0	0
T119	0	104	0	0
T120	0	277	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	57	0	0
T16	1830	2	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	1	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	0	2	0	0
T119	0	1	0	0
T120	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	6594961	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	6597407	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	134	0	0
T16	1830	2	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	1	0	0
T39	0	14	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T63	0	8	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	75	0	0
T16	1830	2	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	1	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	0	2	0	0
T82	0	1	0	0
T119	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	57	0	0
T16	1830	2	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	1	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	0	2	0	0
T119	0	1	0	0
T120	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	57	0	0
T16	1830	2	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	1	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	0	2	0	0
T119	0	1	0	0
T120	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	525607	0	0
T16	1830	354	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	264	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	97	0	0
T61	0	126	0	0
T62	0	119	0	0
T64	0	408	0	0
T65	0	686	0	0
T66	0	777	0	0
T119	0	103	0	0
T120	0	276	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	6846	0	0
T12	26790	23	0	0
T13	44225	13	0	0
T14	22532	26	0	0
T15	974	1	0	0
T16	0	8	0	0
T17	0	6	0	0
T18	0	13	0	0
T26	407	1	0	0
T27	407	0	0	0
T28	406	1	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T56	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	492459	0	0
T16	1830	99	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	75	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	395	0	0
T61	0	218	0	0
T62	0	244	0	0
T64	0	272	0	0
T65	0	180	0	0
T66	0	154	0	0
T119	0	249	0	0
T120	0	144	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T26,T28

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T26
1	0	Covered	T12,T26,T15
1	1	Covered	T12,T26,T28

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T16,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T16,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T39,T62,T63

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T38,T39
1	0	Covered	T12,T26,T28
1	1	Covered	T16,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T39,T62,T63
0	1	Covered	T65,T80,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T39,T62,T63
0	1	Unreachable
1	0	Covered	T39,T62,T63

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T38,T39
0	1	Covered	T16,T38,T39
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T39,T62,T63
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T12,T26,T28
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T39,T62,T63
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T38,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T38,T39
DetectSt	-	-	-	-	1	-	-	Covered	T65,T80,T81
DetectSt	-	-	-	-	0	1	-	Covered	T39,T62,T63
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T62,T63
StableSt	-	-	-	-	-	-	0	Covered	T39,T62,T63
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	180	0	0
CntIncr_A	8472339	5874	0	0
CntNoWrap_A	8472339	7799130	0	0
DetectStDropOut_A	8472339	9	0	0
DetectedOut_A	8472339	9856	0	0
DetectedPulseOut_A	8472339	49	0	0
DisabledIdleSt_A	8472339	6594961	0	0
DisabledNoDetection_A	8472339	6597407	0	0
EnterDebounceSt_A	8472339	122	0	0
EnterDetectSt_A	8472339	58	0	0
EnterStableSt_A	8472339	49	0	0
PulseIsPulse_A	8472339	49	0	0
StayInStableSt	8472339	9807	0	0
gen_high_level_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_sticky_sva.StableStDropOut_A	8472339	669365	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	180	0	0
T16	1830	4	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	2	0	0
T39	0	6	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	5	0	0
T61	0	3	0	0
T62	0	2	0	0
T63	0	4	0	0
T64	0	2	0	0
T65	0	9	0	0
T66	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	5874	0	0
T16	1830	140	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	78	0	0
T39	0	261	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	370	0	0
T61	0	162	0	0
T62	0	98	0	0
T63	0	104	0	0
T64	0	72	0	0
T65	0	257	0	0
T66	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7799130	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	9	0	0
T65	8588	2	0	0
T80	0	1	0	0
T81	0	2	0	0
T146	0	2	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	757	0	0	0
T150	413	0	0	0
T151	490	0	0	0
T152	433	0	0	0
T153	508	0	0	0
T154	448	0	0	0
T155	24335	0	0	0
T156	4403	0	0	0
T157	536	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	9856	0	0
T39	2886	1364	0	0
T50	13809	0	0	0
T60	1574	0	0	0
T62	0	282	0	0
T63	0	692	0	0
T64	0	496	0	0
T83	0	205	0	0
T84	0	181	0	0
T87	655	0	0	0
T119	0	90	0	0
T122	0	221	0	0
T123	0	618	0	0
T124	0	5	0	0
T125	526	0	0	0
T126	506	0	0	0
T127	449	0	0	0
T128	523	0	0	0
T129	501	0	0	0
T130	926	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	49	0	0
T39	2886	3	0	0
T50	13809	0	0	0
T60	1574	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T87	655	0	0	0
T119	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	526	0	0	0
T126	506	0	0	0
T127	449	0	0	0
T128	523	0	0	0
T129	501	0	0	0
T130	926	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	6594961	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	6597407	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	122	0	0
T16	1830	4	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	2	0	0
T39	0	3	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	5	0	0
T61	0	3	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	0	7	0	0
T66	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	58	0	0
T39	2886	3	0	0
T50	13809	0	0	0
T60	1574	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	0	2	0	0
T83	0	1	0	0
T84	0	2	0	0
T87	655	0	0	0
T119	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T125	526	0	0	0
T126	506	0	0	0
T127	449	0	0	0
T128	523	0	0	0
T129	501	0	0	0
T130	926	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	49	0	0
T39	2886	3	0	0
T50	13809	0	0	0
T60	1574	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T87	655	0	0	0
T119	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	526	0	0	0
T126	506	0	0	0
T127	449	0	0	0
T128	523	0	0	0
T129	501	0	0	0
T130	926	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	49	0	0
T39	2886	3	0	0
T50	13809	0	0	0
T60	1574	0	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T87	655	0	0	0
T119	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	526	0	0	0
T126	506	0	0	0
T127	449	0	0	0
T128	523	0	0	0
T129	501	0	0	0
T130	926	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	9807	0	0
T39	2886	1361	0	0
T50	13809	0	0	0
T60	1574	0	0	0
T62	0	281	0	0
T63	0	690	0	0
T64	0	495	0	0
T83	0	204	0	0
T84	0	179	0	0
T87	655	0	0	0
T119	0	89	0	0
T122	0	220	0	0
T123	0	617	0	0
T124	0	4	0	0
T125	526	0	0	0
T126	506	0	0	0
T127	449	0	0	0
T128	523	0	0	0
T129	501	0	0	0
T130	926	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	669365	0	0
T39	2886	735	0	0
T50	13809	0	0	0
T60	1574	0	0	0
T62	0	36	0	0
T63	0	598	0	0
T64	0	171	0	0
T83	0	60	0	0
T84	0	369	0	0
T87	655	0	0	0
T119	0	158	0	0
T122	0	42	0	0
T123	0	153	0	0
T124	0	85	0	0
T125	526	0	0	0
T126	506	0	0	0
T127	449	0	0	0
T128	523	0	0	0
T129	501	0	0	0
T130	926	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T16,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T16,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T16,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T38,T39
1	0	Covered	T12,T13,T26
1	1	Covered	T16,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T38,T39
0	1	Covered	T38,T61,T63
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T38,T39
0	1	Unreachable
1	0	Covered	T16,T38,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T38,T39
0	1	Covered	T16,T38,T39
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T38,T39
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T60,T61,T63
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T38,T39
DetectSt	-	-	-	-	1	-	-	Covered	T38,T61,T63
DetectSt	-	-	-	-	0	1	-	Covered	T16,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T38,T39
StableSt	-	-	-	-	-	-	0	Covered	T16,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	216	0	0
CntIncr_A	8472339	121457	0	0
CntNoWrap_A	8472339	7799094	0	0
DetectStDropOut_A	8472339	27	0	0
DetectedOut_A	8472339	379665	0	0
DetectedPulseOut_A	8472339	55	0	0
DisabledIdleSt_A	8472339	6594961	0	0
DisabledNoDetection_A	8472339	6597407	0	0
EnterDebounceSt_A	8472339	134	0	0
EnterDetectSt_A	8472339	82	0	0
EnterStableSt_A	8472339	55	0	0
PulseIsPulse_A	8472339	55	0	0
StayInStableSt	8472339	379610	0	0
gen_high_event_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_high_level_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_sticky_sva.StableStDropOut_A	8472339	405827	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	216	0	0
T16	1830	4	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	4	0	0
T39	0	6	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	5	0	0
T61	0	5	0	0
T62	0	2	0	0
T63	0	9	0	0
T64	0	5	0	0
T65	0	11	0	0
T66	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	121457	0	0
T16	1830	126	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	196	0	0
T39	0	150	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	395	0	0
T61	0	120	0	0
T62	0	44	0	0
T63	0	285	0	0
T64	0	400	0	0
T65	0	454	0	0
T66	0	170	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7799094	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	27	0	0
T38	37355	1	0	0
T45	16091	0	0	0
T53	22054	0	0	0
T61	0	2	0	0
T63	0	3	0	0
T65	0	4	0	0
T80	0	3	0	0
T83	0	1	0	0
T84	0	4	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T122	0	1	0	0
T133	0	4	0	0
T158	0	1	0	0
T159	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	379665	0	0
T16	1830	342	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	1	0	0
T39	0	901	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	91	0	0
T63	0	174	0	0
T65	0	71	0	0
T66	0	634	0	0
T83	0	1	0	0
T119	0	298	0	0
T121	0	112	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	55	0	0
T16	1830	2	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	1	0	0
T39	0	3	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0
T83	0	1	0	0
T119	0	1	0	0
T121	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	6594961	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	6597407	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	134	0	0
T16	1830	2	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	2	0	0
T39	0	3	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T60	0	5	0	0
T61	0	3	0	0
T62	0	1	0	0
T63	0	5	0	0
T64	0	5	0	0
T65	0	6	0	0
T66	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	82	0	0
T16	1830	2	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	2	0	0
T39	0	3	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T61	0	2	0	0
T62	0	1	0	0
T63	0	4	0	0
T65	0	5	0	0
T66	0	2	0	0
T119	0	1	0	0
T121	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	55	0	0
T16	1830	2	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	1	0	0
T39	0	3	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0
T83	0	1	0	0
T119	0	1	0	0
T121	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	55	0	0
T16	1830	2	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	1	0	0
T39	0	3	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0
T83	0	1	0	0
T119	0	1	0	0
T121	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	379610	0	0
T16	1830	340	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T39	2886	898	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	90	0	0
T63	0	173	0	0
T65	0	70	0	0
T66	0	632	0	0
T84	0	62	0	0
T119	0	297	0	0
T121	0	110	0	0
T123	0	147	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	405827	0	0
T16	1830	220	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	128	0	0
T39	0	1343	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	291	0	0
T63	0	469	0	0
T65	0	69	0	0
T66	0	324	0	0
T83	0	61	0	0
T119	0	42	0	0
T121	0	631	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T26
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T45,T47,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T45,T47,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T45,T47,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T38,T45,T55
1	0	Covered	T12,T13,T14
1	1	Covered	T45,T47,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T47,T46
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T47,T46
0	1	Covered	T47,T46,T160
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T47,T46
1	-	Covered	T47,T46,T160

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T45,T47,T46
0	1	Covered	T45,T47,T46
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T45,T47,T46
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T45,T47,T46
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T45,T47,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T64,T102,T161
DebounceSt	-	0	0	-	-	-	-	Covered	T45,T47,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T45,T47,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T47,T46,T160
StableSt	-	-	-	-	-	-	0	Covered	T45,T47,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	74	0	0
CntIncr_A	8472339	2340	0	0
CntNoWrap_A	8472339	7799236	0	0
DetectStDropOut_A	8472339	0	0	0
DetectedOut_A	8472339	2818	0	0
DetectedPulseOut_A	8472339	35	0	0
DisabledIdleSt_A	8472339	7628810	0	0
DisabledNoDetection_A	8472339	7631201	0	0
EnterDebounceSt_A	8472339	39	0	0
EnterDetectSt_A	8472339	35	0	0
EnterStableSt_A	8472339	35	0	0
PulseIsPulse_A	8472339	35	0	0
StayInStableSt	8472339	2761	0	0
gen_high_level_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	74	0	0
T45	16091	2	0	0
T46	0	2	0	0
T47	7117	6	0	0
T53	22054	0	0	0
T64	0	1	0	0
T83	0	2	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T123	0	2	0	0
T142	0	2	0	0
T155	0	2	0	0
T159	424	0	0	0
T160	0	4	0	0
T162	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	2340	0	0
T45	16091	74	0	0
T46	0	15	0	0
T47	7117	155	0	0
T53	22054	0	0	0
T64	0	55	0	0
T83	0	59	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T123	0	100	0	0
T142	0	82	0	0
T155	0	56	0	0
T159	424	0	0	0
T160	0	166	0	0
T162	0	15	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7799236	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	2818	0	0
T45	16091	42	0	0
T46	0	129	0	0
T47	7117	183	0	0
T53	22054	0	0	0
T83	0	44	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T123	0	40	0	0
T124	0	41	0	0
T142	0	161	0	0
T155	0	42	0	0
T159	424	0	0	0
T160	0	81	0	0
T162	0	55	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	35	0	0
T45	16091	1	0	0
T46	0	1	0	0
T47	7117	3	0	0
T53	22054	0	0	0
T83	0	1	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T123	0	1	0	0
T124	0	1	0	0
T142	0	1	0	0
T155	0	1	0	0
T159	424	0	0	0
T160	0	2	0	0
T162	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7628810	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7631201	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	39	0	0
T45	16091	1	0	0
T46	0	1	0	0
T47	7117	3	0	0
T53	22054	0	0	0
T64	0	1	0	0
T83	0	1	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T123	0	1	0	0
T142	0	1	0	0
T155	0	1	0	0
T159	424	0	0	0
T160	0	2	0	0
T162	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	35	0	0
T45	16091	1	0	0
T46	0	1	0	0
T47	7117	3	0	0
T53	22054	0	0	0
T83	0	1	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T123	0	1	0	0
T124	0	1	0	0
T142	0	1	0	0
T155	0	1	0	0
T159	424	0	0	0
T160	0	2	0	0
T162	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	35	0	0
T45	16091	1	0	0
T46	0	1	0	0
T47	7117	3	0	0
T53	22054	0	0	0
T83	0	1	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T123	0	1	0	0
T124	0	1	0	0
T142	0	1	0	0
T155	0	1	0	0
T159	424	0	0	0
T160	0	2	0	0
T162	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	35	0	0
T45	16091	1	0	0
T46	0	1	0	0
T47	7117	3	0	0
T53	22054	0	0	0
T83	0	1	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T123	0	1	0	0
T124	0	1	0	0
T142	0	1	0	0
T155	0	1	0	0
T159	424	0	0	0
T160	0	2	0	0
T162	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	2761	0	0
T45	16091	40	0	0
T46	0	128	0	0
T47	7117	178	0	0
T53	22054	0	0	0
T83	0	42	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T123	0	38	0	0
T124	0	39	0	0
T142	0	160	0	0
T155	0	40	0	0
T159	424	0	0	0
T160	0	78	0	0
T162	0	53	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	12	0	0
T39	2886	0	0	0
T46	634	1	0	0
T47	7117	1	0	0
T125	526	0	0	0
T126	506	0	0	0
T127	449	0	0	0
T128	523	0	0	0
T129	501	0	0	0
T130	926	0	0	0
T142	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	407	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T26
1	1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T15,T42,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T15,T42,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T15,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T42,T43
1	0	Covered	T12,T13,T14
1	1	Covered	T15,T42,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T42,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T42,T43
0	1	Covered	T15,T42,T43
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T42,T43
1	-	Covered	T15,T42,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T42,T43
0	1	Covered	T15,T42,T43
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T42,T43
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T42,T43
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T42,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T45,T46
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T42,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T15,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T42,T43
StableSt	-	-	-	-	-	-	0	Covered	T15,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	143	0	0
CntIncr_A	8472339	15419	0	0
CntNoWrap_A	8472339	7799167	0	0
DetectStDropOut_A	8472339	0	0	0
DetectedOut_A	8472339	18171	0	0
DetectedPulseOut_A	8472339	67	0	0
DisabledIdleSt_A	8472339	7634249	0	0
DisabledNoDetection_A	8472339	7636634	0	0
EnterDebounceSt_A	8472339	76	0	0
EnterDetectSt_A	8472339	67	0	0
EnterStableSt_A	8472339	67	0	0
PulseIsPulse_A	8472339	67	0	0
StayInStableSt	8472339	18073	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8472339	2660	0	0
gen_low_level_sva.LowLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	143	0	0
T15	974	4	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	2	0	0
T42	0	5	0	0
T43	0	2	0	0
T44	0	4	0	0
T45	0	7	0	0
T46	0	3	0	0
T47	0	2	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T130	0	3	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	15419	0	0
T15	974	118	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	60	0	0
T42	0	102	0	0
T43	0	19	0	0
T44	0	138	0	0
T45	0	270	0	0
T46	0	30	0	0
T47	0	51	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T130	0	176	0	0
T169	0	87	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7799167	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	569	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	18171	0	0
T15	974	194	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	173	0	0
T42	0	116	0	0
T43	0	62	0	0
T44	0	146	0	0
T45	0	218	0	0
T46	0	61	0	0
T47	0	220	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T130	0	79	0	0
T169	0	176	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	67	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T130	0	1	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7634249	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	4	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7636634	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	4	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	76	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T130	0	2	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	67	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T130	0	1	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	67	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T130	0	1	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	67	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T130	0	1	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	18073	0	0
T15	974	192	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	171	0	0
T42	0	113	0	0
T43	0	61	0	0
T44	0	143	0	0
T45	0	214	0	0
T46	0	59	0	0
T47	0	219	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T130	0	78	0	0
T169	0	174	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	2660	0	0
T12	26790	5	0	0
T13	44225	0	0	0
T14	22532	0	0	0
T15	974	2	0	0
T20	0	1	0	0
T21	0	34	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T42	0	3	0	0
T43	0	1	0	0
T56	0	5	0	0
T58	0	2	0	0
T68	0	5	0	0
T117	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	35	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T47	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	2	0	0
T130	0	1	0	0
T160	0	2	0	0
T162	0	2	0	0