Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T26
1	0	Covered	T12,T13,T26
1	1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T20,T45,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T20,T45,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T20,T45,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T45,T46
1	0	Covered	T12,T13,T26
1	1	Covered	T20,T45,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T45,T46
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T45,T46
0	1	Covered	T20,T46,T64
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T45,T46
1	-	Covered	T20,T46,T64

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T20,T45,T46
0	1	Covered	T20,T45,T46
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T45,T46
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T20,T45,T46
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T45,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T102,T197
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T45,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T20,T45,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T46,T64
StableSt	-	-	-	-	-	-	0	Covered	T20,T45,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	99	0	0
CntIncr_A	8472339	61611	0	0
CntNoWrap_A	8472339	7799211	0	0
DetectStDropOut_A	8472339	0	0	0
DetectedOut_A	8472339	11957	0	0
DetectedPulseOut_A	8472339	48	0	0
DisabledIdleSt_A	8472339	7657164	0	0
DisabledNoDetection_A	8472339	7659568	0	0
EnterDebounceSt_A	8472339	51	0	0
EnterDetectSt_A	8472339	48	0	0
EnterStableSt_A	8472339	48	0	0
PulseIsPulse_A	8472339	48	0	0
StayInStableSt	8472339	11891	0	0
gen_high_level_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	99	0	0
T20	730	2	0	0
T21	6772	0	0	0
T45	16091	2	0	0
T46	0	2	0	0
T53	22054	0	0	0
T64	0	2	0	0
T83	0	2	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	4	0	0
T162	0	2	0	0
T171	0	2	0	0
T172	0	4	0	0
T175	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	61611	0	0
T20	730	50	0	0
T21	6772	0	0	0
T45	16091	75	0	0
T46	0	15	0	0
T53	22054	0	0	0
T64	0	75	0	0
T83	0	12	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	164	0	0
T162	0	31	0	0
T171	0	41	0	0
T172	0	76	0	0
T175	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7799211	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	11957	0	0
T20	730	40	0	0
T21	6772	0	0	0
T45	16091	377	0	0
T46	0	129	0	0
T53	22054	0	0	0
T64	0	44	0	0
T83	0	43	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	136	0	0
T162	0	89	0	0
T171	0	39	0	0
T172	0	73	0	0
T175	0	101	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	48	0	0
T20	730	1	0	0
T21	6772	0	0	0
T45	16091	1	0	0
T46	0	1	0	0
T53	22054	0	0	0
T64	0	1	0	0
T83	0	1	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	2	0	0
T162	0	1	0	0
T171	0	1	0	0
T172	0	2	0	0
T175	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7657164	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7659568	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	51	0	0
T20	730	1	0	0
T21	6772	0	0	0
T45	16091	1	0	0
T46	0	1	0	0
T53	22054	0	0	0
T64	0	1	0	0
T83	0	1	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	2	0	0
T162	0	1	0	0
T171	0	1	0	0
T172	0	2	0	0
T175	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	48	0	0
T20	730	1	0	0
T21	6772	0	0	0
T45	16091	1	0	0
T46	0	1	0	0
T53	22054	0	0	0
T64	0	1	0	0
T83	0	1	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	2	0	0
T162	0	1	0	0
T171	0	1	0	0
T172	0	2	0	0
T175	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	48	0	0
T20	730	1	0	0
T21	6772	0	0	0
T45	16091	1	0	0
T46	0	1	0	0
T53	22054	0	0	0
T64	0	1	0	0
T83	0	1	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	2	0	0
T162	0	1	0	0
T171	0	1	0	0
T172	0	2	0	0
T175	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	48	0	0
T20	730	1	0	0
T21	6772	0	0	0
T45	16091	1	0	0
T46	0	1	0	0
T53	22054	0	0	0
T64	0	1	0	0
T83	0	1	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	2	0	0
T162	0	1	0	0
T171	0	1	0	0
T172	0	2	0	0
T175	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	11891	0	0
T20	730	39	0	0
T21	6772	0	0	0
T45	16091	375	0	0
T46	0	128	0	0
T53	22054	0	0	0
T64	0	43	0	0
T83	0	41	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	133	0	0
T162	0	87	0	0
T171	0	37	0	0
T172	0	71	0	0
T175	0	100	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	29	0	0
T20	730	1	0	0
T21	6772	0	0	0
T39	2886	0	0	0
T46	634	1	0	0
T64	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T125	526	0	0	0
T126	506	0	0	0
T127	449	0	0	0
T128	523	0	0	0
T129	501	0	0	0
T130	926	0	0	0
T142	0	1	0	0
T172	0	2	0	0
T175	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T26
1	0	Covered	T12,T13,T26
1	1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T20,T45,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T20,T45,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T20,T45,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T45,T44
1	0	Covered	T12,T13,T26
1	1	Covered	T20,T45,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T45,T44
0	1	Covered	T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T45,T44
0	1	Covered	T45,T44,T64
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T45,T44
1	-	Covered	T45,T44,T64

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T20,T45,T44
0	1	Covered	T20,T45,T44
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T45,T44
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T20,T45,T44
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T45,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T83
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T45,T44
DetectSt	-	-	-	-	1	-	-	Covered	T78
DetectSt	-	-	-	-	0	1	-	Covered	T20,T45,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T44,T64
StableSt	-	-	-	-	-	-	0	Covered	T20,T45,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	66	0	0
CntIncr_A	8472339	59811	0	0
CntNoWrap_A	8472339	7799244	0	0
DetectStDropOut_A	8472339	1	0	0
DetectedOut_A	8472339	2614	0	0
DetectedPulseOut_A	8472339	31	0	0
DisabledIdleSt_A	8472339	7650547	0	0
DisabledNoDetection_A	8472339	7652941	0	0
EnterDebounceSt_A	8472339	34	0	0
EnterDetectSt_A	8472339	32	0	0
EnterStableSt_A	8472339	31	0	0
PulseIsPulse_A	8472339	31	0	0
StayInStableSt	8472339	2562	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8472339	6262	0	0
gen_low_level_sva.LowLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	66	0	0
T20	730	2	0	0
T21	6772	0	0	0
T44	0	2	0	0
T45	16091	4	0	0
T46	0	2	0	0
T53	22054	0	0	0
T64	0	6	0	0
T83	0	1	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	2	0	0
T176	0	2	0	0
T183	0	2	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	59811	0	0
T20	730	50	0	0
T21	6772	0	0	0
T44	0	69	0	0
T45	16091	130	0	0
T46	0	15	0	0
T53	22054	0	0	0
T64	0	165	0	0
T83	0	59	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	82	0	0
T176	0	37	0	0
T183	0	74	0	0
T194	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7799244	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	1	0	0
T75	7835	0	0	0
T78	758	1	0	0
T146	2669	0	0	0
T188	404	0	0	0
T189	498	0	0	0
T190	27235	0	0	0
T191	661	0	0	0
T192	517	0	0	0
T193	526	0	0	0
T200	640	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	2614	0	0
T20	730	129	0	0
T21	6772	0	0	0
T44	0	139	0	0
T45	16091	86	0	0
T46	0	61	0	0
T53	22054	0	0	0
T64	0	161	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	310	0	0
T176	0	171	0	0
T183	0	191	0	0
T194	0	39	0	0
T198	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	31	0	0
T20	730	1	0	0
T21	6772	0	0	0
T44	0	1	0	0
T45	16091	2	0	0
T46	0	1	0	0
T53	22054	0	0	0
T64	0	3	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	1	0	0
T176	0	1	0	0
T183	0	1	0	0
T194	0	1	0	0
T198	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7650547	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7652941	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	34	0	0
T20	730	1	0	0
T21	6772	0	0	0
T44	0	1	0	0
T45	16091	2	0	0
T46	0	1	0	0
T53	22054	0	0	0
T64	0	3	0	0
T83	0	1	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	1	0	0
T176	0	1	0	0
T183	0	1	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	32	0	0
T20	730	1	0	0
T21	6772	0	0	0
T44	0	1	0	0
T45	16091	2	0	0
T46	0	1	0	0
T53	22054	0	0	0
T64	0	3	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	1	0	0
T176	0	1	0	0
T183	0	1	0	0
T194	0	1	0	0
T198	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	31	0	0
T20	730	1	0	0
T21	6772	0	0	0
T44	0	1	0	0
T45	16091	2	0	0
T46	0	1	0	0
T53	22054	0	0	0
T64	0	3	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	1	0	0
T176	0	1	0	0
T183	0	1	0	0
T194	0	1	0	0
T198	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	31	0	0
T20	730	1	0	0
T21	6772	0	0	0
T44	0	1	0	0
T45	16091	2	0	0
T46	0	1	0	0
T53	22054	0	0	0
T64	0	3	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	1	0	0
T176	0	1	0	0
T183	0	1	0	0
T194	0	1	0	0
T198	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	2562	0	0
T20	730	127	0	0
T21	6772	0	0	0
T44	0	138	0	0
T45	16091	83	0	0
T46	0	59	0	0
T53	22054	0	0	0
T64	0	157	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	309	0	0
T176	0	169	0	0
T183	0	189	0	0
T194	0	37	0	0
T198	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	6262	0	0
T12	26790	9	0	0
T13	44225	11	0	0
T14	22532	32	0	0
T15	974	1	0	0
T17	0	16	0	0
T18	0	11	0	0
T26	407	1	0	0
T27	407	0	0	0
T28	406	1	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T56	0	5	0	0
T58	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	9	0	0
T44	23879	1	0	0
T45	16091	1	0	0
T53	22054	0	0	0
T64	0	2	0	0
T86	710	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T142	0	1	0	0
T159	424	0	0	0
T164	0	1	0	0
T173	0	1	0	0
T195	0	1	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T26
1	0	Covered	T12,T13,T26
1	1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T15,T43,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T15,T43,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T15,T43,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T43,T38
1	0	Covered	T12,T13,T26
1	1	Covered	T15,T43,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T43,T38
0	1	Covered	T79,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T43,T38
0	1	Covered	T15,T45,T55
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T43,T38
1	-	Covered	T15,T45,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T43,T38
0	1	Covered	T15,T43,T38
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T43,T38
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T43,T38
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T43,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T202,T203
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T43,T38
DetectSt	-	-	-	-	1	-	-	Covered	T79,T78
DetectSt	-	-	-	-	0	1	-	Covered	T15,T43,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T45,T55
StableSt	-	-	-	-	-	-	0	Covered	T15,T43,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	136	0	0
CntIncr_A	8472339	7489	0	0
CntNoWrap_A	8472339	7799174	0	0
DetectStDropOut_A	8472339	2	0	0
DetectedOut_A	8472339	5312	0	0
DetectedPulseOut_A	8472339	64	0	0
DisabledIdleSt_A	8472339	7751946	0	0
DisabledNoDetection_A	8472339	7754331	0	0
EnterDebounceSt_A	8472339	71	0	0
EnterDetectSt_A	8472339	66	0	0
EnterStableSt_A	8472339	64	0	0
PulseIsPulse_A	8472339	64	0	0
StayInStableSt	8472339	5221	0	0
gen_high_level_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	136	0	0
T15	974	4	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	2	0	0
T43	0	3	0	0
T45	0	4	0	0
T46	0	4	0	0
T55	0	2	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	2	0	0
T130	0	4	0	0
T171	0	2	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7489	0	0
T15	974	118	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	60	0	0
T43	0	38	0	0
T45	0	149	0	0
T46	0	30	0	0
T55	0	14	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	40	0	0
T130	0	176	0	0
T171	0	41	0	0
T176	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7799174	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	569	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	2	0	0
T75	7835	0	0	0
T78	758	1	0	0
T79	166285	1	0	0
T146	2669	0	0	0
T184	4430	0	0	0
T188	404	0	0	0
T189	498	0	0	0
T190	27235	0	0	0
T191	661	0	0	0
T204	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	5312	0	0
T15	974	85	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	58	0	0
T43	0	127	0	0
T45	0	172	0	0
T46	0	56	0	0
T55	0	39	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	71	0	0
T130	0	84	0	0
T171	0	39	0	0
T176	0	147	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	64	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T55	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	1	0	0
T130	0	2	0	0
T171	0	1	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7751946	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	4	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7754331	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	4	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	71	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	1	0	0
T43	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T55	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	1	0	0
T130	0	2	0	0
T171	0	1	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	66	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T55	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	1	0	0
T130	0	2	0	0
T171	0	1	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	64	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T55	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	1	0	0
T130	0	2	0	0
T171	0	1	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	64	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T55	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	1	0	0
T130	0	2	0	0
T171	0	1	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	5221	0	0
T15	974	83	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T38	0	56	0	0
T43	0	125	0	0
T45	0	169	0	0
T46	0	53	0	0
T55	0	38	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T62	0	69	0	0
T130	0	81	0	0
T171	0	37	0	0
T176	0	146	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	36	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T55	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T79	0	1	0	0
T130	0	1	0	0
T140	0	1	0	0
T162	0	2	0	0
T175	0	2	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T26
1	0	Covered	T12,T13,T26
1	1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T15,T42,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T15,T42,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T15,T42,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T42,T45
1	0	Covered	T12,T13,T14
1	1	Covered	T15,T42,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T42,T45
0	1	Covered	T42,T164,T205
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T42,T45
0	1	Covered	T15,T45,T46
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T42,T45
1	-	Covered	T15,T45,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T42,T45
0	1	Covered	T15,T42,T45
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T42,T45
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T42,T45
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T42,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T187
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T42,T45
DetectSt	-	-	-	-	1	-	-	Covered	T42,T164,T205
DetectSt	-	-	-	-	0	1	-	Covered	T15,T42,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T45,T46
StableSt	-	-	-	-	-	-	0	Covered	T15,T42,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	104	0	0
CntIncr_A	8472339	3632	0	0
CntNoWrap_A	8472339	7799206	0	0
DetectStDropOut_A	8472339	3	0	0
DetectedOut_A	8472339	3314	0	0
DetectedPulseOut_A	8472339	48	0	0
DisabledIdleSt_A	8472339	7751194	0	0
DisabledNoDetection_A	8472339	7753576	0	0
EnterDebounceSt_A	8472339	53	0	0
EnterDetectSt_A	8472339	51	0	0
EnterStableSt_A	8472339	48	0	0
PulseIsPulse_A	8472339	48	0	0
StayInStableSt	8472339	3241	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8472339	6138	0	0
gen_low_level_sva.LowLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	104	0	0
T15	974	4	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T42	0	4	0	0
T45	0	4	0	0
T46	0	2	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T64	0	4	0	0
T83	0	2	0	0
T130	0	2	0	0
T162	0	4	0	0
T169	0	2	0	0
T175	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	3632	0	0
T15	974	118	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T42	0	68	0	0
T45	0	124	0	0
T46	0	15	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T64	0	150	0	0
T83	0	59	0	0
T130	0	88	0	0
T162	0	30	0	0
T169	0	87	0	0
T175	0	112	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7799206	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	569	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	3	0	0
T38	37355	0	0	0
T42	760	1	0	0
T43	638	0	0	0
T45	16091	0	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T164	0	1	0	0
T174	562	0	0	0
T205	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	3314	0	0
T15	974	198	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T42	0	107	0	0
T45	0	80	0	0
T46	0	58	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T64	0	113	0	0
T83	0	43	0	0
T130	0	78	0	0
T162	0	81	0	0
T169	0	41	0	0
T175	0	169	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	48	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T64	0	2	0	0
T83	0	1	0	0
T130	0	1	0	0
T162	0	2	0	0
T169	0	1	0	0
T175	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7751194	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	4	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7753576	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	4	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	53	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T42	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T64	0	2	0	0
T83	0	1	0	0
T130	0	1	0	0
T162	0	2	0	0
T169	0	1	0	0
T175	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	51	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T42	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T64	0	2	0	0
T83	0	1	0	0
T130	0	1	0	0
T162	0	2	0	0
T169	0	1	0	0
T175	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	48	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T64	0	2	0	0
T83	0	1	0	0
T130	0	1	0	0
T162	0	2	0	0
T169	0	1	0	0
T175	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	48	0	0
T15	974	2	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T42	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T64	0	2	0	0
T83	0	1	0	0
T130	0	1	0	0
T162	0	2	0	0
T169	0	1	0	0
T175	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	3241	0	0
T15	974	195	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T42	0	105	0	0
T45	0	77	0	0
T46	0	57	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T64	0	110	0	0
T83	0	41	0	0
T130	0	77	0	0
T162	0	78	0	0
T169	0	39	0	0
T175	0	166	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	6138	0	0
T12	26790	13	0	0
T13	44225	15	0	0
T14	22532	29	0	0
T15	974	2	0	0
T17	0	10	0	0
T18	0	6	0	0
T19	0	12	0	0
T20	0	1	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T56	0	7	0	0
T58	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	22	0	0
T15	974	1	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T18	24617	0	0	0
T19	23445	0	0	0
T20	730	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T56	490	0	0	0
T57	121297	0	0	0
T58	426	0	0	0
T59	1138	0	0	0
T64	0	1	0	0
T130	0	1	0	0
T162	0	1	0	0
T172	0	1	0	0
T175	0	1	0	0
T185	0	1	0	0
T206	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T26
1	0	Covered	T12,T13,T26
1	1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T42,T38,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T42,T38,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T42,T38,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T42,T38,T45
1	0	Covered	T12,T13,T26
1	1	Covered	T42,T38,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T42,T38,T45
0	1	Covered	T64,T163,T207
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T38,T45
0	1	Covered	T42,T38,T45
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T42,T38,T45
1	-	Covered	T42,T38,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T42,T38,T45
0	1	Covered	T42,T38,T45
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T38,T45
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T42,T38,T45
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T42,T38,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T64,T142,T208
DebounceSt	-	0	0	-	-	-	-	Covered	T42,T38,T45
DetectSt	-	-	-	-	1	-	-	Covered	T64,T163,T207
DetectSt	-	-	-	-	0	1	-	Covered	T42,T38,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T38,T45
StableSt	-	-	-	-	-	-	0	Covered	T42,T38,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	124	0	0
CntIncr_A	8472339	14764	0	0
CntNoWrap_A	8472339	7799186	0	0
DetectStDropOut_A	8472339	3	0	0
DetectedOut_A	8472339	5355	0	0
DetectedPulseOut_A	8472339	55	0	0
DisabledIdleSt_A	8472339	7633778	0	0
DisabledNoDetection_A	8472339	7636170	0	0
EnterDebounceSt_A	8472339	67	0	0
EnterDetectSt_A	8472339	58	0	0
EnterStableSt_A	8472339	55	0	0
PulseIsPulse_A	8472339	55	0	0
StayInStableSt	8472339	5277	0	0
gen_high_level_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	124	0	0
T38	37355	2	0	0
T42	760	4	0	0
T43	638	0	0	0
T45	16091	4	0	0
T47	0	2	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T55	0	2	0	0
T62	0	4	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	2	0	0
T162	0	4	0	0
T171	0	2	0	0
T174	562	0	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	14764	0	0
T38	37355	60	0	0
T42	760	68	0	0
T43	638	0	0	0
T45	16091	134	0	0
T47	0	52	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T55	0	14	0	0
T62	0	80	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	88	0	0
T162	0	30	0	0
T171	0	41	0	0
T174	562	0	0	0
T176	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7799186	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	3	0	0
T64	67990	1	0	0
T71	17884	0	0	0
T163	671	1	0	0
T207	0	1	0	0
T209	492	0	0	0
T210	4420	0	0	0
T211	5316	0	0	0
T212	535	0	0	0
T213	650	0	0	0
T214	527	0	0	0
T215	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	5355	0	0
T38	37355	55	0	0
T42	760	142	0	0
T43	638	0	0	0
T45	16091	167	0	0
T47	0	198	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T55	0	55	0	0
T62	0	201	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	79	0	0
T162	0	47	0	0
T171	0	38	0	0
T174	562	0	0	0
T176	0	18	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	55	0	0
T38	37355	1	0	0
T42	760	2	0	0
T43	638	0	0	0
T45	16091	2	0	0
T47	0	1	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T55	0	1	0	0
T62	0	2	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	1	0	0
T162	0	2	0	0
T171	0	1	0	0
T174	562	0	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7633778	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7636170	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	67	0	0
T38	37355	1	0	0
T42	760	2	0	0
T43	638	0	0	0
T45	16091	2	0	0
T47	0	1	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T55	0	1	0	0
T62	0	2	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	1	0	0
T162	0	2	0	0
T171	0	1	0	0
T174	562	0	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	58	0	0
T38	37355	1	0	0
T42	760	2	0	0
T43	638	0	0	0
T45	16091	2	0	0
T47	0	1	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T55	0	1	0	0
T62	0	2	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	1	0	0
T162	0	2	0	0
T171	0	1	0	0
T174	562	0	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	55	0	0
T38	37355	1	0	0
T42	760	2	0	0
T43	638	0	0	0
T45	16091	2	0	0
T47	0	1	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T55	0	1	0	0
T62	0	2	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	1	0	0
T162	0	2	0	0
T171	0	1	0	0
T174	562	0	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	55	0	0
T38	37355	1	0	0
T42	760	2	0	0
T43	638	0	0	0
T45	16091	2	0	0
T47	0	1	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T55	0	1	0	0
T62	0	2	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	1	0	0
T162	0	2	0	0
T171	0	1	0	0
T174	562	0	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	5277	0	0
T38	37355	54	0	0
T42	760	139	0	0
T43	638	0	0	0
T45	16091	165	0	0
T47	0	196	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T55	0	53	0	0
T62	0	198	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	78	0	0
T162	0	44	0	0
T171	0	36	0	0
T174	562	0	0	0
T176	0	17	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	31	0	0
T38	37355	1	0	0
T42	760	1	0	0
T43	638	0	0	0
T45	16091	2	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T62	0	1	0	0
T64	0	1	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	1	0	0
T155	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T174	562	0	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T26
1	0	Covered	T12,T13,T26
1	1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T42,T43,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T42,T43,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T42,T43,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T45
1	0	Covered	T12,T13,T26
1	1	Covered	T42,T43,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T42,T43,T44
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T43,T44
0	1	Covered	T42,T44,T62
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T42,T43,T44
1	-	Covered	T42,T44,T62

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T42,T43,T44
0	1	Covered	T42,T43,T44
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T42,T43,T44
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T42,T43,T44
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T42,T43,T44
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T42,T43,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T44,T62
StableSt	-	-	-	-	-	-	0	Covered	T42,T43,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	85	0	0
CntIncr_A	8472339	2184	0	0
CntNoWrap_A	8472339	7799225	0	0
DetectStDropOut_A	8472339	0	0	0
DetectedOut_A	8472339	2735	0	0
DetectedPulseOut_A	8472339	42	0	0
DisabledIdleSt_A	8472339	7633015	0	0
DisabledNoDetection_A	8472339	7635412	0	0
EnterDebounceSt_A	8472339	43	0	0
EnterDetectSt_A	8472339	42	0	0
EnterStableSt_A	8472339	42	0	0
PulseIsPulse_A	8472339	42	0	0
StayInStableSt	8472339	2670	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8472339	6846	0	0
gen_low_level_sva.LowLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	85	0	0
T38	37355	0	0	0
T42	760	2	0	0
T43	638	2	0	0
T44	0	4	0	0
T45	16091	0	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T62	0	2	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	2	0	0
T160	0	2	0	0
T162	0	2	0	0
T174	562	0	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	2184	0	0
T38	37355	0	0	0
T42	760	34	0	0
T43	638	19	0	0
T44	0	138	0	0
T45	16091	0	0	0
T46	0	15	0	0
T47	0	51	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T62	0	40	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	88	0	0
T160	0	83	0	0
T162	0	15	0	0
T174	562	0	0	0
T176	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7799225	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	2735	0	0
T38	37355	0	0	0
T42	760	105	0	0
T43	638	62	0	0
T44	0	71	0	0
T45	16091	0	0	0
T46	0	117	0	0
T47	0	40	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T62	0	42	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	40	0	0
T160	0	129	0	0
T162	0	61	0	0
T174	562	0	0	0
T176	0	171	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	42	0	0
T38	37355	0	0	0
T42	760	1	0	0
T43	638	1	0	0
T44	0	2	0	0
T45	16091	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T62	0	1	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T174	562	0	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7633015	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22081	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7635412	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	43	0	0
T38	37355	0	0	0
T42	760	1	0	0
T43	638	1	0	0
T44	0	2	0	0
T45	16091	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T62	0	1	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T174	562	0	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	42	0	0
T38	37355	0	0	0
T42	760	1	0	0
T43	638	1	0	0
T44	0	2	0	0
T45	16091	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T62	0	1	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T174	562	0	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	42	0	0
T38	37355	0	0	0
T42	760	1	0	0
T43	638	1	0	0
T44	0	2	0	0
T45	16091	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T62	0	1	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T174	562	0	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	42	0	0
T38	37355	0	0	0
T42	760	1	0	0
T43	638	1	0	0
T44	0	2	0	0
T45	16091	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T62	0	1	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T174	562	0	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	2670	0	0
T38	37355	0	0	0
T42	760	104	0	0
T43	638	60	0	0
T44	0	69	0	0
T45	16091	0	0	0
T46	0	115	0	0
T47	0	38	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T62	0	41	0	0
T68	492	0	0	0
T85	742	0	0	0
T118	404	0	0	0
T130	0	38	0	0
T160	0	128	0	0
T162	0	60	0	0
T174	562	0	0	0
T176	0	169	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	6846	0	0
T12	26790	23	0	0
T13	44225	13	0	0
T14	22532	26	0	0
T15	974	1	0	0
T16	0	8	0	0
T17	0	6	0	0
T18	0	13	0	0
T26	407	1	0	0
T27	407	0	0	0
T28	406	1	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T56	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	18	0	0
T38	37355	0	0	0
T42	760	1	0	0
T43	638	0	0	0
T44	0	2	0	0
T45	16091	0	0	0
T48	10475	0	0	0
T49	4917	0	0	0
T62	0	1	0	0
T68	492	0	0	0
T79	0	1	0	0
T85	742	0	0	0
T118	404	0	0	0
T160	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T172	0	1	0	0
T174	562	0	0	0
T216	0	1	0	0
T217	0	1	0	0