Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T48,T49
1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T14,T48,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T14,T48,T49

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T14,T48,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T48,T49
1	0	Covered	T14,T48,T53
1	1	Covered	T14,T48,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T48,T49
0	1	Covered	T49,T53,T92
1	0	Covered	T53,T54,T92

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T48,T50
0	1	Covered	T48,T50,T51
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T48,T50
1	-	Covered	T48,T50,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T48,T49
0	1	Covered	T14,T48,T49
0	0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T48,T49
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T48,T49
IdleSt	0	-	-	-	-	-	-	Covered	T14,T48,T49
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T48,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T93,T218,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T48,T49
DetectSt	-	-	-	-	1	-	-	Covered	T49,T53,T54
DetectSt	-	-	-	-	0	1	-	Covered	T14,T48,T50
DetectSt	-	-	-	-	0	0	-	Covered	T14,T48,T49
StableSt	-	-	-	-	-	-	1	Covered	T48,T50,T51
StableSt	-	-	-	-	-	-	0	Covered	T14,T48,T50
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	2852	0	0
CntIncr_A	8472339	107222	0	0
CntNoWrap_A	8472339	7796458	0	0
DetectStDropOut_A	8472339	363	0	0
DetectedOut_A	8472339	89717	0	0
DetectedPulseOut_A	8472339	843	0	0
DisabledIdleSt_A	8472339	7320471	0	0
DisabledNoDetection_A	8472339	7322738	0	0
EnterDebounceSt_A	8472339	1449	0	0
EnterDetectSt_A	8472339	1404	0	0
EnterStableSt_A	8472339	843	0	0
PulseIsPulse_A	8472339	843	0	0
StayInStableSt	8472339	88781	0	0
gen_high_event_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_high_level_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	749	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	2852	0	0
T14	22532	2	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	6	0	0
T49	0	30	0	0
T50	0	14	0	0
T51	0	20	0	0
T52	0	38	0	0
T53	0	58	0	0
T54	0	14	0	0
T56	490	0	0	0
T92	0	50	0	0
T220	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	107222	0	0
T14	22532	55	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	117	0	0
T49	0	678	0	0
T50	0	399	0	0
T51	0	450	0	0
T52	0	741	0	0
T53	0	1520	0	0
T54	0	557	0	0
T56	490	0	0	0
T92	0	1684	0	0
T220	0	1400	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7796458	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22079	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	363	0	0
T38	37355	0	0	0
T45	16091	0	0	0
T49	4917	15	0	0
T53	22054	19	0	0
T86	710	0	0	0
T91	422	0	0	0
T92	0	15	0	0
T93	0	2	0	0
T94	0	6	0	0
T97	0	30	0	0
T98	0	15	0	0
T99	0	13	0	0
T101	0	6	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T221	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	89717	0	0
T14	22532	154	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	181	0	0
T50	0	903	0	0
T51	0	44	0	0
T52	0	1043	0	0
T56	490	0	0	0
T220	0	2561	0	0
T222	0	73	0	0
T223	0	63	0	0
T224	0	2463	0	0
T225	0	5852	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	843	0	0
T14	22532	1	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	3	0	0
T50	0	7	0	0
T51	0	10	0	0
T52	0	19	0	0
T56	490	0	0	0
T220	0	25	0	0
T222	0	1	0	0
T223	0	5	0	0
T224	0	18	0	0
T225	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7320471	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	18346	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7322738	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	18352	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	1449	0	0
T14	22532	1	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	3	0	0
T49	0	15	0	0
T50	0	7	0	0
T51	0	10	0	0
T52	0	19	0	0
T53	0	29	0	0
T54	0	7	0	0
T56	490	0	0	0
T92	0	25	0	0
T220	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	1404	0	0
T14	22532	1	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	3	0	0
T49	0	15	0	0
T50	0	7	0	0
T51	0	10	0	0
T52	0	19	0	0
T53	0	29	0	0
T54	0	7	0	0
T56	490	0	0	0
T92	0	25	0	0
T220	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	843	0	0
T14	22532	1	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	3	0	0
T50	0	7	0	0
T51	0	10	0	0
T52	0	19	0	0
T56	490	0	0	0
T220	0	25	0	0
T222	0	1	0	0
T223	0	5	0	0
T224	0	18	0	0
T225	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	843	0	0
T14	22532	1	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	3	0	0
T50	0	7	0	0
T51	0	10	0	0
T52	0	19	0	0
T56	490	0	0	0
T220	0	25	0	0
T222	0	1	0	0
T223	0	5	0	0
T224	0	18	0	0
T225	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	88781	0	0
T14	22532	152	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	177	0	0
T50	0	893	0	0
T51	0	34	0	0
T52	0	1022	0	0
T56	490	0	0	0
T220	0	2532	0	0
T222	0	71	0	0
T223	0	58	0	0
T224	0	2443	0	0
T225	0	5832	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	749	0	0
T38	37355	0	0	0
T43	638	0	0	0
T45	16091	0	0	0
T48	10475	2	0	0
T49	4917	0	0	0
T50	0	4	0	0
T51	0	10	0	0
T52	0	17	0	0
T53	22054	0	0	0
T91	422	0	0	0
T107	2324	0	0	0
T108	421	0	0	0
T118	404	0	0	0
T220	0	21	0	0
T223	0	5	0	0
T224	0	16	0	0
T225	0	8	0	0
T226	0	5	0	0
T227	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T26
1	1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T12,T13,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T19,T38,T83
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T13,T14
1	-	Covered	T12,T13,T14

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T13,T14
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T13,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T18,T19
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T13,T14
DetectSt	-	-	-	-	1	-	-	Covered	T19,T38,T83
DetectSt	-	-	-	-	0	1	-	Covered	T12,T13,T14
DetectSt	-	-	-	-	0	0	-	Covered	T12,T13,T14
StableSt	-	-	-	-	-	-	1	Covered	T12,T13,T14
StableSt	-	-	-	-	-	-	0	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	1022	0	0
CntIncr_A	8472339	56336	0	0
CntNoWrap_A	8472339	7798288	0	0
DetectStDropOut_A	8472339	72	0	0
DetectedOut_A	8472339	15841	0	0
DetectedPulseOut_A	8472339	393	0	0
DisabledIdleSt_A	8472339	7369291	0	0
DisabledNoDetection_A	8472339	7370949	0	0
EnterDebounceSt_A	8472339	555	0	0
EnterDetectSt_A	8472339	469	0	0
EnterStableSt_A	8472339	393	0	0
PulseIsPulse_A	8472339	393	0	0
StayInStableSt	8472339	15411	0	0
gen_high_level_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	354	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	1022	0	0
T12	26790	16	0	0
T13	44225	30	0	0
T14	22532	2	0	0
T15	974	0	0	0
T17	0	23	0	0
T18	0	20	0	0
T19	0	23	0	0
T21	0	3	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	20	0	0
T45	0	2	0	0
T48	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	56336	0	0
T12	26790	816	0	0
T13	44225	2580	0	0
T14	22532	74	0	0
T15	974	0	0	0
T17	0	1613	0	0
T18	0	888	0	0
T19	0	1878	0	0
T21	0	45	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	1062	0	0
T45	0	91	0	0
T48	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7798288	0	0
T12	26790	24704	0	0
T13	44225	43676	0	0
T14	22532	22079	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	72	0	0
T19	23445	11	0	0
T20	730	0	0	0
T21	6772	0	0	0
T38	37355	5	0	0
T45	16091	0	0	0
T53	22054	0	0	0
T59	1138	0	0	0
T83	0	1	0	0
T91	422	0	0	0
T95	0	5	0	0
T96	0	1	0	0
T100	0	3	0	0
T102	0	5	0	0
T103	0	3	0	0
T104	0	9	0	0
T105	0	1	0	0
T107	2324	0	0	0
T108	421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	15841	0	0
T12	26790	125	0	0
T13	44225	138	0	0
T14	22532	55	0	0
T15	974	0	0	0
T17	0	201	0	0
T18	0	453	0	0
T21	0	3	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	147	0	0
T44	0	13	0	0
T45	0	29	0	0
T48	0	54	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	393	0	0
T12	26790	8	0	0
T13	44225	15	0	0
T14	22532	1	0	0
T15	974	0	0	0
T17	0	11	0	0
T18	0	9	0	0
T21	0	1	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	5	0	0
T44	0	4	0	0
T45	0	1	0	0
T48	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7369291	0	0
T12	26790	21174	0	0
T13	44225	38271	0	0
T14	22532	21928	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7370949	0	0
T12	26790	21177	0	0
T13	44225	38271	0	0
T14	22532	21935	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	555	0	0
T12	26790	8	0	0
T13	44225	15	0	0
T14	22532	1	0	0
T15	974	0	0	0
T17	0	12	0	0
T18	0	11	0	0
T19	0	12	0	0
T21	0	2	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	10	0	0
T45	0	1	0	0
T48	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	469	0	0
T12	26790	8	0	0
T13	44225	15	0	0
T14	22532	1	0	0
T15	974	0	0	0
T17	0	11	0	0
T18	0	9	0	0
T19	0	11	0	0
T21	0	1	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	10	0	0
T45	0	1	0	0
T48	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	393	0	0
T12	26790	8	0	0
T13	44225	15	0	0
T14	22532	1	0	0
T15	974	0	0	0
T17	0	11	0	0
T18	0	9	0	0
T21	0	1	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	5	0	0
T44	0	4	0	0
T45	0	1	0	0
T48	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	393	0	0
T12	26790	8	0	0
T13	44225	15	0	0
T14	22532	1	0	0
T15	974	0	0	0
T17	0	11	0	0
T18	0	9	0	0
T21	0	1	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	5	0	0
T44	0	4	0	0
T45	0	1	0	0
T48	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	15411	0	0
T12	26790	117	0	0
T13	44225	123	0	0
T14	22532	54	0	0
T15	974	0	0	0
T17	0	190	0	0
T18	0	444	0	0
T21	0	2	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	142	0	0
T44	0	9	0	0
T45	0	28	0	0
T48	0	52	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	354	0	0
T12	26790	8	0	0
T13	44225	15	0	0
T14	22532	1	0	0
T15	974	0	0	0
T17	0	11	0	0
T18	0	9	0	0
T21	0	1	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	5	0	0
T40	0	6	0	0
T44	0	4	0	0
T45	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T48,T49
1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T14,T48,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T14,T48,T49

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T14,T48,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T48,T49
1	0	Covered	T14,T48,T53
1	1	Covered	T14,T48,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T48,T49
0	1	Covered	T48,T49,T50
1	0	Covered	T48,T53,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T51,T52
0	1	Covered	T14,T51,T52
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T51,T52
1	-	Covered	T14,T51,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T48,T49
0	1	Covered	T14,T48,T49
0	0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T48,T49
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T48,T49
IdleSt	0	-	-	-	-	-	-	Covered	T14,T48,T49
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T48,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T93,T218,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T48,T49
DetectSt	-	-	-	-	1	-	-	Covered	T48,T49,T53
DetectSt	-	-	-	-	0	1	-	Covered	T14,T51,T52
DetectSt	-	-	-	-	0	0	-	Covered	T14,T48,T49
StableSt	-	-	-	-	-	-	1	Covered	T14,T51,T52
StableSt	-	-	-	-	-	-	0	Covered	T14,T51,T52
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	3030	0	0
CntIncr_A	8472339	122762	0	0
CntNoWrap_A	8472339	7796280	0	0
DetectStDropOut_A	8472339	407	0	0
DetectedOut_A	8472339	65017	0	0
DetectedPulseOut_A	8472339	757	0	0
DisabledIdleSt_A	8472339	7339846	0	0
DisabledNoDetection_A	8472339	7342122	0	0
EnterDebounceSt_A	8472339	1550	0	0
EnterDetectSt_A	8472339	1481	0	0
EnterStableSt_A	8472339	757	0	0
PulseIsPulse_A	8472339	757	0	0
StayInStableSt	8472339	64176	0	0
gen_high_event_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_high_level_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	673	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	3030	0	0
T14	22532	24	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	14	0	0
T49	0	30	0	0
T50	0	20	0	0
T51	0	48	0	0
T52	0	24	0	0
T53	0	34	0	0
T54	0	36	0	0
T56	490	0	0	0
T92	0	14	0	0
T220	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	122762	0	0
T14	22532	792	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	413	0	0
T49	0	683	0	0
T50	0	777	0	0
T51	0	1128	0	0
T52	0	792	0	0
T53	0	917	0	0
T54	0	1436	0	0
T56	490	0	0	0
T92	0	474	0	0
T220	0	1080	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7796280	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22057	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	407	0	0
T38	37355	0	0	0
T43	638	0	0	0
T45	16091	0	0	0
T48	10475	2	0	0
T49	4917	15	0	0
T50	0	2	0	0
T53	22054	0	0	0
T91	422	0	0	0
T93	0	4	0	0
T94	0	6	0	0
T97	0	24	0	0
T98	0	10	0	0
T107	2324	0	0	0
T108	421	0	0	0
T118	404	0	0	0
T225	0	4	0	0
T226	0	11	0	0
T228	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	65017	0	0
T14	22532	1564	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T51	0	1080	0	0
T52	0	229	0	0
T56	490	0	0	0
T219	0	584	0	0
T220	0	511	0	0
T223	0	2429	0	0
T224	0	2568	0	0
T227	0	1678	0	0
T229	0	226	0	0
T230	0	3254	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	757	0	0
T14	22532	12	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T51	0	24	0	0
T52	0	12	0	0
T56	490	0	0	0
T219	0	8	0	0
T220	0	15	0	0
T223	0	20	0	0
T224	0	25	0	0
T227	0	24	0	0
T229	0	7	0	0
T230	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7339846	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	16943	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7342122	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	16944	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	1550	0	0
T14	22532	12	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	7	0	0
T49	0	15	0	0
T50	0	10	0	0
T51	0	24	0	0
T52	0	12	0	0
T53	0	17	0	0
T54	0	18	0	0
T56	490	0	0	0
T92	0	7	0	0
T220	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	1481	0	0
T14	22532	12	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	7	0	0
T49	0	15	0	0
T50	0	10	0	0
T51	0	24	0	0
T52	0	12	0	0
T53	0	17	0	0
T54	0	18	0	0
T56	490	0	0	0
T92	0	7	0	0
T220	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	757	0	0
T14	22532	12	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T51	0	24	0	0
T52	0	12	0	0
T56	490	0	0	0
T219	0	8	0	0
T220	0	15	0	0
T223	0	20	0	0
T224	0	25	0	0
T227	0	24	0	0
T229	0	7	0	0
T230	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	757	0	0
T14	22532	12	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T51	0	24	0	0
T52	0	12	0	0
T56	490	0	0	0
T219	0	8	0	0
T220	0	15	0	0
T223	0	20	0	0
T224	0	25	0	0
T227	0	24	0	0
T229	0	7	0	0
T230	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	64176	0	0
T14	22532	1546	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T51	0	1056	0	0
T52	0	216	0	0
T56	490	0	0	0
T219	0	576	0	0
T220	0	495	0	0
T223	0	2406	0	0
T224	0	2541	0	0
T227	0	1653	0	0
T229	0	219	0	0
T230	0	3225	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	673	0	0
T14	22532	6	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T51	0	24	0	0
T52	0	11	0	0
T56	490	0	0	0
T219	0	8	0	0
T220	0	14	0	0
T223	0	17	0	0
T224	0	23	0	0
T227	0	23	0	0
T229	0	7	0	0
T230	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T14,T17
1	Covered	T12,T13,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T17
1	0	Covered	T12,T13,T26
1	1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T14,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T12,T14,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T14,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T17
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T14,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T17
0	1	Covered	T12,T44,T231
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Covered	T14,T17,T18
1	0	Covered	T75,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T17,T18
1	-	Covered	T14,T17,T18

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T14,T17
0	1	Covered	T12,T14,T17
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T14,T17
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T14,T17
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T14,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T44,T51
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T14,T17
DetectSt	-	-	-	-	1	-	-	Covered	T12,T44,T231
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T18
DetectSt	-	-	-	-	0	0	-	Covered	T12,T14,T17
StableSt	-	-	-	-	-	-	1	Covered	T14,T17,T18
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	787	0	0
CntIncr_A	8472339	47917	0	0
CntNoWrap_A	8472339	7798523	0	0
DetectStDropOut_A	8472339	61	0	0
DetectedOut_A	8472339	13847	0	0
DetectedPulseOut_A	8472339	307	0	0
DisabledIdleSt_A	8472339	7389820	0	0
DisabledNoDetection_A	8472339	7391548	0	0
EnterDebounceSt_A	8472339	416	0	0
EnterDetectSt_A	8472339	371	0	0
EnterStableSt_A	8472339	307	0	0
PulseIsPulse_A	8472339	307	0	0
StayInStableSt	8472339	13513	0	0
gen_high_level_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	278	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	787	0	0
T12	26790	8	0	0
T13	44225	0	0	0
T14	22532	8	0	0
T15	974	0	0	0
T17	0	11	0	0
T18	0	10	0	0
T19	0	4	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	8	0	0
T40	0	3	0	0
T44	0	7	0	0
T51	0	2	0	0
T179	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	47917	0	0
T12	26790	469	0	0
T13	44225	0	0	0
T14	22532	168	0	0
T15	974	0	0	0
T17	0	517	0	0
T18	0	480	0	0
T19	0	212	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	325	0	0
T40	0	193	0	0
T44	0	565	0	0
T51	0	54	0	0
T179	0	280	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7798523	0	0
T12	26790	24712	0	0
T13	44225	43706	0	0
T14	22532	22073	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	61	0	0
T12	26790	4	0	0
T13	44225	0	0	0
T14	22532	0	0	0
T15	974	0	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T44	0	3	0	0
T64	0	2	0	0
T72	0	1	0	0
T75	0	1	0	0
T96	0	2	0	0
T231	0	9	0	0
T232	0	6	0	0
T233	0	3	0	0
T234	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	13847	0	0
T14	22532	348	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	341	0	0
T18	0	210	0	0
T19	0	114	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	198	0	0
T40	0	91	0	0
T41	0	77	0	0
T56	490	0	0	0
T179	0	152	0	0
T220	0	85	0	0
T235	0	131	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	307	0	0
T14	22532	4	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	5	0	0
T18	0	5	0	0
T19	0	2	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	4	0	0
T40	0	1	0	0
T41	0	4	0	0
T56	490	0	0	0
T179	0	2	0	0
T220	0	1	0	0
T235	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7389820	0	0
T12	26790	21174	0	0
T13	44225	43706	0	0
T14	22532	20522	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7391548	0	0
T12	26790	21177	0	0
T13	44225	43725	0	0
T14	22532	20524	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	416	0	0
T12	26790	4	0	0
T13	44225	0	0	0
T14	22532	4	0	0
T15	974	0	0	0
T17	0	6	0	0
T18	0	5	0	0
T19	0	2	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	4	0	0
T40	0	2	0	0
T44	0	4	0	0
T51	0	2	0	0
T179	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	371	0	0
T12	26790	4	0	0
T13	44225	0	0	0
T14	22532	4	0	0
T15	974	0	0	0
T17	0	5	0	0
T18	0	5	0	0
T19	0	2	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	4	0	0
T40	0	1	0	0
T44	0	3	0	0
T179	0	2	0	0
T235	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	307	0	0
T14	22532	4	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	5	0	0
T18	0	5	0	0
T19	0	2	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	4	0	0
T40	0	1	0	0
T41	0	4	0	0
T56	490	0	0	0
T179	0	2	0	0
T220	0	1	0	0
T235	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	307	0	0
T14	22532	4	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	5	0	0
T18	0	5	0	0
T19	0	2	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	4	0	0
T40	0	1	0	0
T41	0	4	0	0
T56	490	0	0	0
T179	0	2	0	0
T220	0	1	0	0
T235	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	13513	0	0
T14	22532	344	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	336	0	0
T18	0	205	0	0
T19	0	112	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	194	0	0
T40	0	90	0	0
T41	0	73	0	0
T56	490	0	0	0
T179	0	150	0	0
T220	0	83	0	0
T235	0	125	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	278	0	0
T14	22532	4	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	5	0	0
T18	0	5	0	0
T19	0	2	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	4	0	0
T40	0	1	0	0
T41	0	4	0	0
T56	490	0	0	0
T179	0	2	0	0
T235	0	6	0	0
T236	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T48,T49
1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T14,T48,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T14,T48,T49

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T14,T48,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T48,T49
1	0	Covered	T14,T48,T53
1	1	Covered	T14,T48,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T48,T49
0	1	Covered	T48,T49,T51
1	0	Covered	T48,T51,T92

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T53,T50
0	1	Covered	T14,T53,T50
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T53,T50
1	-	Covered	T14,T53,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T48,T49
0	1	Covered	T14,T48,T49
0	0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T48,T49
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T48,T49
IdleSt	0	-	-	-	-	-	-	Covered	T14,T48,T49
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T48,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T93,T218,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T48,T49
DetectSt	-	-	-	-	1	-	-	Covered	T48,T49,T51
DetectSt	-	-	-	-	0	1	-	Covered	T14,T53,T50
DetectSt	-	-	-	-	0	0	-	Covered	T14,T48,T49
StableSt	-	-	-	-	-	-	1	Covered	T14,T53,T50
StableSt	-	-	-	-	-	-	0	Covered	T14,T53,T50
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	2813	0	0
CntIncr_A	8472339	121213	0	0
CntNoWrap_A	8472339	7796497	0	0
DetectStDropOut_A	8472339	427	0	0
DetectedOut_A	8472339	57479	0	0
DetectedPulseOut_A	8472339	685	0	0
DisabledIdleSt_A	8472339	7346868	0	0
DisabledNoDetection_A	8472339	7349158	0	0
EnterDebounceSt_A	8472339	1436	0	0
EnterDetectSt_A	8472339	1379	0	0
EnterStableSt_A	8472339	685	0	0
PulseIsPulse_A	8472339	685	0	0
StayInStableSt	8472339	56723	0	0
gen_high_event_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_high_level_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	614	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	2813	0	0
T14	22532	24	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	22	0	0
T49	0	46	0	0
T50	0	22	0	0
T51	0	28	0	0
T52	0	46	0	0
T53	0	34	0	0
T54	0	56	0	0
T56	490	0	0	0
T92	0	8	0	0
T220	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	121213	0	0
T14	22532	612	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	646	0	0
T49	0	1062	0	0
T50	0	726	0	0
T51	0	658	0	0
T52	0	1242	0	0
T53	0	867	0	0
T54	0	2100	0	0
T56	490	0	0	0
T92	0	267	0	0
T220	0	604	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7796497	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22057	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	427	0	0
T38	37355	0	0	0
T43	638	0	0	0
T45	16091	0	0	0
T48	10475	8	0	0
T49	4917	23	0	0
T51	0	6	0	0
T53	22054	0	0	0
T91	422	0	0	0
T92	0	2	0	0
T93	0	2	0	0
T94	0	27	0	0
T97	0	11	0	0
T107	2324	0	0	0
T108	421	0	0	0
T118	404	0	0	0
T225	0	8	0	0
T226	0	15	0	0
T229	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	57479	0	0
T14	22532	1744	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T50	0	992	0	0
T52	0	1564	0	0
T53	0	2497	0	0
T54	0	1706	0	0
T56	490	0	0	0
T219	0	935	0	0
T223	0	32	0	0
T227	0	395	0	0
T228	0	1485	0	0
T230	0	2373	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	685	0	0
T14	22532	12	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T50	0	11	0	0
T52	0	23	0	0
T53	0	17	0	0
T54	0	28	0	0
T56	490	0	0	0
T219	0	9	0	0
T223	0	9	0	0
T227	0	14	0	0
T228	0	8	0	0
T230	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7346868	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	16944	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7349158	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	16945	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	1436	0	0
T14	22532	12	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	11	0	0
T49	0	23	0	0
T50	0	11	0	0
T51	0	14	0	0
T52	0	23	0	0
T53	0	17	0	0
T54	0	28	0	0
T56	490	0	0	0
T92	0	4	0	0
T220	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	1379	0	0
T14	22532	12	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	11	0	0
T49	0	23	0	0
T50	0	11	0	0
T51	0	14	0	0
T52	0	23	0	0
T53	0	17	0	0
T54	0	28	0	0
T56	490	0	0	0
T92	0	4	0	0
T220	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	685	0	0
T14	22532	12	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T50	0	11	0	0
T52	0	23	0	0
T53	0	17	0	0
T54	0	28	0	0
T56	490	0	0	0
T219	0	9	0	0
T223	0	9	0	0
T227	0	14	0	0
T228	0	8	0	0
T230	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	685	0	0
T14	22532	12	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T50	0	11	0	0
T52	0	23	0	0
T53	0	17	0	0
T54	0	28	0	0
T56	490	0	0	0
T219	0	9	0	0
T223	0	9	0	0
T227	0	14	0	0
T228	0	8	0	0
T230	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	56723	0	0
T14	22532	1726	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T50	0	979	0	0
T52	0	1539	0	0
T53	0	2473	0	0
T54	0	1678	0	0
T56	490	0	0	0
T219	0	926	0	0
T223	0	23	0	0
T227	0	380	0	0
T228	0	1476	0	0
T230	0	2359	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	614	0	0
T14	22532	6	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T50	0	9	0	0
T52	0	21	0	0
T53	0	10	0	0
T54	0	28	0	0
T56	490	0	0	0
T219	0	9	0	0
T223	0	9	0	0
T227	0	13	0	0
T228	0	7	0	0
T230	0	14	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T26
1	1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T12,T13,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T64,T95,T237
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T13,T14
1	-	Covered	T12,T13,T14

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T13,T14
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T13,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T13,T19
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T13,T14
DetectSt	-	-	-	-	1	-	-	Covered	T64,T95,T237
DetectSt	-	-	-	-	0	1	-	Covered	T12,T13,T14
DetectSt	-	-	-	-	0	0	-	Covered	T12,T13,T14
StableSt	-	-	-	-	-	-	1	Covered	T12,T13,T14
StableSt	-	-	-	-	-	-	0	Covered	T12,T13,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	770	0	0
CntIncr_A	8472339	47920	0	0
CntNoWrap_A	8472339	7798540	0	0
DetectStDropOut_A	8472339	23	0	0
DetectedOut_A	8472339	14314	0	0
DetectedPulseOut_A	8472339	333	0	0
DisabledIdleSt_A	8472339	7407246	0	0
DisabledNoDetection_A	8472339	7408993	0	0
EnterDebounceSt_A	8472339	410	0	0
EnterDetectSt_A	8472339	360	0	0
EnterStableSt_A	8472339	333	0	0
PulseIsPulse_A	8472339	333	0	0
StayInStableSt	8472339	13962	0	0
gen_high_level_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	313	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	770	0	0
T12	26790	3	0	0
T13	44225	25	0	0
T14	22532	12	0	0
T15	974	0	0	0
T17	0	4	0	0
T18	0	4	0	0
T19	0	17	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	10	0	0
T40	0	9	0	0
T44	0	4	0	0
T53	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	47920	0	0
T12	26790	185	0	0
T13	44225	1446	0	0
T14	22532	432	0	0
T15	974	0	0	0
T17	0	308	0	0
T18	0	266	0	0
T19	0	1229	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	658	0	0
T40	0	645	0	0
T44	0	196	0	0
T53	0	420	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7798540	0	0
T12	26790	24717	0	0
T13	44225	43681	0	0
T14	22532	22069	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	23	0	0
T64	67990	6	0	0
T71	17884	0	0	0
T73	29497	0	0	0
T95	29153	6	0	0
T100	0	2	0	0
T124	0	2	0	0
T135	0	1	0	0
T209	492	0	0	0
T237	0	2	0	0
T238	0	3	0	0
T239	0	1	0	0
T240	523	0	0	0
T241	701	0	0	0
T242	525	0	0	0
T243	415	0	0	0
T244	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	14314	0	0
T12	26790	16	0	0
T13	44225	805	0	0
T14	22532	341	0	0
T15	974	0	0	0
T17	0	9	0	0
T18	0	11	0	0
T19	0	155	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	75	0	0
T40	0	240	0	0
T44	0	125	0	0
T53	0	472	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	333	0	0
T12	26790	1	0	0
T13	44225	12	0	0
T14	22532	6	0	0
T15	974	0	0	0
T17	0	2	0	0
T18	0	2	0	0
T19	0	8	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	5	0	0
T40	0	4	0	0
T44	0	2	0	0
T53	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7407246	0	0
T12	26790	21174	0	0
T13	44225	38271	0	0
T14	22532	20342	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7408993	0	0
T12	26790	21177	0	0
T13	44225	38271	0	0
T14	22532	20344	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	410	0	0
T12	26790	2	0	0
T13	44225	13	0	0
T14	22532	6	0	0
T15	974	0	0	0
T17	0	2	0	0
T18	0	2	0	0
T19	0	9	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	5	0	0
T40	0	5	0	0
T44	0	2	0	0
T53	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	360	0	0
T12	26790	1	0	0
T13	44225	12	0	0
T14	22532	6	0	0
T15	974	0	0	0
T17	0	2	0	0
T18	0	2	0	0
T19	0	8	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	5	0	0
T40	0	4	0	0
T44	0	2	0	0
T53	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	333	0	0
T12	26790	1	0	0
T13	44225	12	0	0
T14	22532	6	0	0
T15	974	0	0	0
T17	0	2	0	0
T18	0	2	0	0
T19	0	8	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	5	0	0
T40	0	4	0	0
T44	0	2	0	0
T53	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	333	0	0
T12	26790	1	0	0
T13	44225	12	0	0
T14	22532	6	0	0
T15	974	0	0	0
T17	0	2	0	0
T18	0	2	0	0
T19	0	8	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	5	0	0
T40	0	4	0	0
T44	0	2	0	0
T53	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	13962	0	0
T12	26790	15	0	0
T13	44225	793	0	0
T14	22532	335	0	0
T15	974	0	0	0
T17	0	7	0	0
T18	0	9	0	0
T19	0	147	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	70	0	0
T40	0	236	0	0
T44	0	123	0	0
T53	0	465	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	313	0	0
T12	26790	1	0	0
T13	44225	12	0	0
T14	22532	6	0	0
T15	974	0	0	0
T17	0	2	0	0
T18	0	2	0	0
T19	0	8	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	5	0	0
T40	0	4	0	0
T44	0	2	0	0
T53	0	7	0	0