Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T48,T49
1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T14,T48,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T14,T48,T49

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T14,T48,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T48,T49
1	0	Covered	T14,T48,T53
1	1	Covered	T14,T48,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T48,T49
0	1	Covered	T49,T53,T51
1	0	Covered	T53,T50,T51

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T48,T54
0	1	Covered	T14,T48,T54
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T48,T54
1	-	Covered	T14,T48,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T48,T49
0	1	Covered	T14,T48,T49
0	0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T48,T49
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T48,T49
IdleSt	0	-	-	-	-	-	-	Covered	T14,T48,T49
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T48,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T93,T218,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T48,T49
DetectSt	-	-	-	-	1	-	-	Covered	T49,T53,T50
DetectSt	-	-	-	-	0	1	-	Covered	T14,T48,T54
DetectSt	-	-	-	-	0	0	-	Covered	T14,T48,T49
StableSt	-	-	-	-	-	-	1	Covered	T14,T48,T54
StableSt	-	-	-	-	-	-	0	Covered	T14,T48,T54
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	2895	0	0
CntIncr_A	8472339	125168	0	0
CntNoWrap_A	8472339	7796415	0	0
DetectStDropOut_A	8472339	382	0	0
DetectedOut_A	8472339	73410	0	0
DetectedPulseOut_A	8472339	874	0	0
DisabledIdleSt_A	8472339	7328977	0	0
DisabledNoDetection_A	8472339	7331243	0	0
EnterDebounceSt_A	8472339	1483	0	0
EnterDetectSt_A	8472339	1414	0	0
EnterStableSt_A	8472339	874	0	0
PulseIsPulse_A	8472339	874	0	0
StayInStableSt	8472339	72442	0	0
gen_high_event_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_high_level_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	779	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	2895	0	0
T14	22532	30	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	16	0	0
T49	0	12	0	0
T50	0	8	0	0
T51	0	38	0	0
T52	0	50	0	0
T53	0	32	0	0
T54	0	28	0	0
T56	490	0	0	0
T92	0	42	0	0
T220	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	125168	0	0
T14	22532	750	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	304	0	0
T49	0	272	0	0
T50	0	309	0	0
T51	0	904	0	0
T52	0	1775	0	0
T53	0	841	0	0
T54	0	1064	0	0
T56	490	0	0	0
T92	0	1050	0	0
T220	0	288	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7796415	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	22051	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	382	0	0
T38	37355	0	0	0
T45	16091	0	0	0
T49	4917	6	0	0
T51	0	9	0	0
T53	22054	9	0	0
T86	710	0	0	0
T91	422	0	0	0
T93	0	2	0	0
T94	0	12	0	0
T97	0	30	0	0
T107	2324	0	0	0
T108	421	0	0	0
T109	724	0	0	0
T110	929	0	0	0
T223	0	1	0	0
T225	0	18	0	0
T226	0	17	0	0
T228	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	73410	0	0
T14	22532	1364	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	891	0	0
T52	0	835	0	0
T54	0	75	0	0
T56	490	0	0	0
T92	0	2125	0	0
T220	0	176	0	0
T224	0	3043	0	0
T227	0	978	0	0
T229	0	1017	0	0
T245	0	439	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	874	0	0
T14	22532	15	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	8	0	0
T52	0	25	0	0
T54	0	14	0	0
T56	490	0	0	0
T92	0	21	0	0
T220	0	6	0	0
T224	0	25	0	0
T227	0	24	0	0
T229	0	23	0	0
T245	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7328977	0	0
T12	26790	24720	0	0
T13	44225	43706	0	0
T14	22532	17380	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7331243	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	17384	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	1483	0	0
T14	22532	15	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	8	0	0
T49	0	6	0	0
T50	0	4	0	0
T51	0	19	0	0
T52	0	25	0	0
T53	0	16	0	0
T54	0	14	0	0
T56	490	0	0	0
T92	0	21	0	0
T220	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	1414	0	0
T14	22532	15	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	8	0	0
T49	0	6	0	0
T50	0	4	0	0
T51	0	19	0	0
T52	0	25	0	0
T53	0	16	0	0
T54	0	14	0	0
T56	490	0	0	0
T92	0	21	0	0
T220	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	874	0	0
T14	22532	15	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	8	0	0
T52	0	25	0	0
T54	0	14	0	0
T56	490	0	0	0
T92	0	21	0	0
T220	0	6	0	0
T224	0	25	0	0
T227	0	24	0	0
T229	0	23	0	0
T245	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	874	0	0
T14	22532	15	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	8	0	0
T52	0	25	0	0
T54	0	14	0	0
T56	490	0	0	0
T92	0	21	0	0
T220	0	6	0	0
T224	0	25	0	0
T227	0	24	0	0
T229	0	23	0	0
T245	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	72442	0	0
T14	22532	1346	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	882	0	0
T52	0	807	0	0
T54	0	61	0	0
T56	490	0	0	0
T92	0	2103	0	0
T220	0	170	0	0
T224	0	3016	0	0
T227	0	951	0	0
T229	0	993	0	0
T245	0	428	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	779	0	0
T14	22532	12	0	0
T15	974	0	0	0
T16	1830	0	0	0
T17	32961	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T48	0	7	0	0
T52	0	22	0	0
T54	0	14	0	0
T56	490	0	0	0
T92	0	20	0	0
T220	0	6	0	0
T224	0	23	0	0
T227	0	21	0	0
T229	0	21	0	0
T245	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T13,T14
1	Covered	T12,T13,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T26
1	1	Covered	T12,T13,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T12,T13,T26	VC_COV_UNR
1	Covered	T12,T13,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T12,T13,T26
1	Covered	T12,T13,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T12,T13,T14
1	1	Covered	T12,T13,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T13,T14
0	1	Covered	T12,T18,T64
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T17
0	1	Covered	T13,T14,T17
1	0	Covered	T75,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T14,T17
1	-	Covered	T13,T14,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
0	0	Excluded	T12,T13,T26	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T14
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T13,T14
IdleSt	0	-	-	-	-	-	-	Covered	T12,T13,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T13,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T13,T18
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T13,T14
DetectSt	-	-	-	-	1	-	-	Covered	T12,T18,T64
DetectSt	-	-	-	-	0	1	-	Covered	T13,T14,T17
DetectSt	-	-	-	-	0	0	-	Covered	T12,T13,T14
StableSt	-	-	-	-	-	-	1	Covered	T13,T14,T17
StableSt	-	-	-	-	-	-	0	Covered	T13,T14,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T26
0	Covered	T12,T13,T26

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8472339	892	0	0
CntIncr_A	8472339	53822	0	0
CntNoWrap_A	8472339	7798418	0	0
DetectStDropOut_A	8472339	52	0	0
DetectedOut_A	8472339	16483	0	0
DetectedPulseOut_A	8472339	364	0	0
DisabledIdleSt_A	8472339	7389295	0	0
DisabledNoDetection_A	8472339	7391012	0	0
EnterDebounceSt_A	8472339	474	0	0
EnterDetectSt_A	8472339	420	0	0
EnterStableSt_A	8472339	364	0	0
PulseIsPulse_A	8472339	364	0	0
StayInStableSt	8472339	16090	0	0
gen_high_level_sva.HighLevelEvent_A	8472339	7801758	0	0
gen_not_sticky_sva.StableStDropOut_A	8472339	333	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	892	0	0
T12	26790	9	0	0
T13	44225	19	0	0
T14	22532	6	0	0
T15	974	0	0	0
T17	0	14	0	0
T18	0	7	0	0
T19	0	17	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	12	0	0
T40	0	8	0	0
T44	0	3	0	0
T48	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	53822	0	0
T12	26790	604	0	0
T13	44225	1023	0	0
T14	22532	189	0	0
T15	974	0	0	0
T17	0	560	0	0
T18	0	460	0	0
T19	0	1293	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	860	0	0
T40	0	588	0	0
T44	0	241	0	0
T48	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7798418	0	0
T12	26790	24711	0	0
T13	44225	43687	0	0
T14	22532	22075	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	52	0	0
T12	26790	3	0	0
T13	44225	0	0	0
T14	22532	0	0	0
T15	974	0	0	0
T18	0	3	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T64	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T96	0	3	0	0
T155	0	1	0	0
T232	0	3	0	0
T246	0	4	0	0
T247	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	16483	0	0
T13	44225	679	0	0
T14	22532	197	0	0
T15	974	0	0	0
T17	0	550	0	0
T19	0	91	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	188	0	0
T40	0	210	0	0
T44	0	6	0	0
T48	0	64	0	0
T52	0	193	0	0
T56	490	0	0	0
T248	0	25	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	364	0	0
T13	44225	9	0	0
T14	22532	3	0	0
T15	974	0	0	0
T17	0	7	0	0
T19	0	8	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	6	0	0
T40	0	4	0	0
T44	0	1	0	0
T48	0	1	0	0
T52	0	3	0	0
T56	490	0	0	0
T248	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7389295	0	0
T12	26790	21174	0	0
T13	44225	38271	0	0
T14	22532	20720	0	0
T15	974	573	0	0
T26	407	6	0	0
T27	407	6	0	0
T28	406	5	0	0
T29	667	266	0	0
T30	779	378	0	0
T31	403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7391012	0	0
T12	26790	21177	0	0
T13	44225	38271	0	0
T14	22532	20725	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	474	0	0
T12	26790	6	0	0
T13	44225	10	0	0
T14	22532	3	0	0
T15	974	0	0	0
T17	0	7	0	0
T18	0	4	0	0
T19	0	9	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	6	0	0
T40	0	4	0	0
T44	0	2	0	0
T48	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	420	0	0
T12	26790	3	0	0
T13	44225	9	0	0
T14	22532	3	0	0
T15	974	0	0	0
T17	0	7	0	0
T18	0	3	0	0
T19	0	8	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	6	0	0
T40	0	4	0	0
T44	0	1	0	0
T48	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	364	0	0
T13	44225	9	0	0
T14	22532	3	0	0
T15	974	0	0	0
T17	0	7	0	0
T19	0	8	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	6	0	0
T40	0	4	0	0
T44	0	1	0	0
T48	0	1	0	0
T52	0	3	0	0
T56	490	0	0	0
T248	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	364	0	0
T13	44225	9	0	0
T14	22532	3	0	0
T15	974	0	0	0
T17	0	7	0	0
T19	0	8	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	6	0	0
T40	0	4	0	0
T44	0	1	0	0
T48	0	1	0	0
T52	0	3	0	0
T56	490	0	0	0
T248	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	16090	0	0
T13	44225	670	0	0
T14	22532	193	0	0
T15	974	0	0	0
T17	0	543	0	0
T19	0	83	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	182	0	0
T40	0	206	0	0
T44	0	5	0	0
T48	0	63	0	0
T52	0	190	0	0
T56	490	0	0	0
T248	0	24	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	7801758	0	0
T12	26790	24733	0	0
T13	44225	43725	0	0
T14	22532	22089	0	0
T15	974	574	0	0
T26	407	7	0	0
T27	407	7	0	0
T28	406	6	0	0
T29	667	267	0	0
T30	779	379	0	0
T31	403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8472339	333	0	0
T13	44225	9	0	0
T14	22532	2	0	0
T15	974	0	0	0
T17	0	7	0	0
T19	0	8	0	0
T26	407	0	0	0
T27	407	0	0	0
T28	406	0	0	0
T29	667	0	0	0
T30	779	0	0	0
T31	403	0	0	0
T38	0	6	0	0
T40	0	4	0	0
T44	0	1	0	0
T48	0	1	0	0
T52	0	3	0	0
T56	490	0	0	0
T248	0	1	0	0