Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_lid_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_pwrb_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	100.00	92.31			100.00	100.00	u_ulp_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.88	100.00	87.50			100.00	100.00	u_ulp_status_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.88	100.00	87.50			100.00	100.00	u_wkup_status_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_key_invert_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_pin_allowed_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_pin_out_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_pin_out_value_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_key_intr_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_key_intr_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_auto_block_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_auto_block_out_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_sel_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_sel_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_sel_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_sel_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_det_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_det_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_det_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_det_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_sel_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_sel_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_sel_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_sel_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_det_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_det_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_det_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_det_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_out_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_out_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_out_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_out_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_combo_intr_status_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_key_intr_status_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	230556	0	0
SrcPulseCheck_M	2147483647	233801	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	230556	0	0
T1	31952563	724	0	0
T2	929792	130	0	0
T3	4875214	40	0	0
T4	1576592	70	0	0
T5	0	834	0	0
T9	448898	70	0	0
T10	0	474	0	0
T11	0	353	0	0
T12	0	70	0	0
T13	0	1092	0	0
T24	1811291	0	0	0
T25	3142882	0	0	0
T26	1489528	0	0	0
T27	6663087	0	0	0
T28	6411862	0	0	0
T35	0	66	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	233801	0	0
T1	35809047	726	0	0
T2	1038888	130	0	0
T3	5455806	102	0	0
T4	1763248	70	0	0
T5	0	835	0	0
T9	499602	70	0	0
T10	0	690	0	0
T11	0	676	0	0
T12	0	70	0	0
T13	0	621	0	0
T24	2027159	0	0	0
T25	3520418	0	0	0
T26	1666632	0	0	0
T27	7467323	0	0	0
T28	7185638	0	0	0
T35	0	16	0	0
T59	0	35	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T35
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1980	0	0
SrcPulseCheck_M	1390629705	2068	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1980	0	0
T1	1951	16	0	0
T2	425	1	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	10	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	2068	0	0
T1	966072	16	0	0
T2	27699	1	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	10	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T5,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T5,T35
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	2042	0	0
SrcPulseCheck_M	8053543	2042	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	2042	0	0
T1	966072	16	0	0
T2	27699	1	0	0
T3	146367	0	0	0
T4	47188	1	0	0
T5	0	10	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	8	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	2042	0	0
T1	1951	16	0	0
T2	425	1	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	10	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	8	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	885	0	0
SrcPulseCheck_M	1390629705	968	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	885	0	0
T1	1951	15	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	14	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	12	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	968	0	0
T1	966072	15	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	14	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	946	0	0
SrcPulseCheck_M	8053543	946	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	946	0	0
T1	966072	15	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	14	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	16	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	946	0	0
T1	1951	15	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	14	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	16	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	924	0	0
SrcPulseCheck_M	1390629705	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	924	0	0
T1	1951	10	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	14	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1012	0	0
T1	966072	10	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	15	0	0
T9	13113	1	0	0
T10	0	8	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	988	0	0
SrcPulseCheck_M	8053543	988	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	988	0	0
T1	966072	10	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	15	0	0
T9	13113	1	0	0
T10	0	8	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	988	0	0
T1	1951	10	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	15	0	0
T9	437	1	0	0
T10	0	8	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	944	0	0
SrcPulseCheck_M	1390629705	1030	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	944	0	0
T1	1951	16	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	13	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1030	0	0
T1	966072	16	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	13	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1007	0	0
SrcPulseCheck_M	8053543	1007	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1007	0	0
T1	966072	16	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	13	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1007	0	0
T1	1951	16	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	13	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	903	0	0
SrcPulseCheck_M	1390629705	987	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	903	0	0
T1	1951	3	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	9	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	987	0	0
T1	966072	3	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	9	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	964	0	0
SrcPulseCheck_M	8053543	964	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	964	0	0
T1	966072	3	0	0
T2	27699	2	0	0
T3	146367	0	0	0
T4	47188	1	0	0
T5	0	9	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	964	0	0
T1	1951	3	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	9	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	545	0	0
SrcPulseCheck_M	1390629705	631	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	545	0	0
T1	1951	9	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	15	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	13	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	631	0	0
T1	966072	9	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	15	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1131	0	0
SrcPulseCheck_M	1390629705	1250	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1131	0	0
T1	1951	12	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	7	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1250	0	0
T1	966072	12	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	7	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	2822	0	0
SrcPulseCheck_M	1390629705	2911	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	2822	0	0
T1	1951	4	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	5	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	2911	0	0
T1	966072	4	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	5	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	2887	0	0
SrcPulseCheck_M	8053543	2887	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	2887	0	0
T1	966072	4	0	0
T2	27699	2	0	0
T3	146367	0	0	0
T4	47188	1	0	0
T5	0	5	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	2887	0	0
T1	1951	4	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	5	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	6009	0	0
SrcPulseCheck_M	1390629705	6105	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	6009	0	0
T1	1951	9	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	18	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	6105	0	0
T1	966072	9	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	18	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	6074	0	0
SrcPulseCheck_M	8053543	6074	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	6074	0	0
T1	966072	9	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	18	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	6074	0	0
T1	1951	9	0	0
T2	425	2	0	0
T3	1219	2	0	0
T4	524	1	0	0
T5	0	18	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	7224	0	0
SrcPulseCheck_M	1390629705	7314	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7224	0	0
T1	1951	18	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	7	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7314	0	0
T1	966072	18	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	7	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	19	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	7282	0	0
SrcPulseCheck_M	8053543	7282	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7282	0	0
T1	966072	18	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	7	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7282	0	0
T1	1951	18	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	7	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	5894	0	0
SrcPulseCheck_M	1390629705	5989	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	5894	0	0
T1	1951	7	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	15	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	5989	0	0
T1	966072	7	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	15	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	5959	0	0
SrcPulseCheck_M	8053543	5959	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	5959	0	0
T1	966072	7	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	15	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	5959	0	0
T1	1951	7	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	15	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	984	0	0
SrcPulseCheck_M	1390629705	1068	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	984	0	0
T1	1951	13	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	7	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1068	0	0
T1	966072	13	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	7	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1044	0	0
SrcPulseCheck_M	8053543	1044	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1044	0	0
T1	966072	13	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	7	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1044	0	0
T1	1951	13	0	0
T2	425	2	0	0
T3	1219	2	0	0
T4	524	1	0	0
T5	0	7	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1959	0	0
SrcPulseCheck_M	1390629705	2043	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1959	0	0
T1	1951	18	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	17	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	2043	0	0
T1	966072	18	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	17	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	2020	0	0
SrcPulseCheck_M	8053543	2020	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	2020	0	0
T1	966072	18	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	17	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	2020	0	0
T1	1951	18	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	17	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1275	0	0
SrcPulseCheck_M	1390629705	1360	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1275	0	0
T1	1951	15	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	14	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	13	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1360	0	0
T1	966072	15	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	14	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1334	0	0
SrcPulseCheck_M	8053543	1334	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1334	0	0
T1	966072	15	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	14	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1334	0	0
T1	1951	15	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	14	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1063	0	0
SrcPulseCheck_M	1390629705	1147	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1063	0	0
T1	1951	11	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	8	0	0
T9	437	1	0	0
T10	0	5	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1147	0	0
T1	966072	11	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	8	0	0
T9	13113	1	0	0
T10	0	9	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1125	0	0
SrcPulseCheck_M	8053543	1125	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1125	0	0
T1	966072	11	0	0
T2	27699	2	0	0
T3	146367	0	0	0
T4	47188	1	0	0
T5	0	8	0	0
T9	13113	1	0	0
T10	0	9	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1125	0	0
T1	1951	11	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	8	0	0
T9	437	1	0	0
T10	0	9	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	7281	0	0
SrcPulseCheck_M	1390629705	7372	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7281	0	0
T1	1951	4	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	20	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7372	0	0
T1	966072	4	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	20	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	7349	0	0
SrcPulseCheck_M	8053543	7349	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7349	0	0
T1	966072	4	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	20	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7349	0	0
T1	1951	4	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	20	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	7041	0	0
SrcPulseCheck_M	1390629705	7130	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7041	0	0
T1	1951	15	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	15	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	13	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7130	0	0
T1	966072	15	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	15	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	7111	0	0
SrcPulseCheck_M	8053543	7111	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7111	0	0
T1	966072	15	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	15	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7111	0	0
T1	1951	15	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	15	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	7222	0	0
SrcPulseCheck_M	1390629705	7315	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7222	0	0
T1	1951	9	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	9	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7315	0	0
T1	966072	9	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	9	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	7291	0	0
SrcPulseCheck_M	8053543	7291	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7291	0	0
T1	966072	9	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	9	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7291	0	0
T1	1951	9	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	9	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	7324	0	0
SrcPulseCheck_M	1390629705	7412	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7324	0	0
T1	1951	10	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	7	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7412	0	0
T1	966072	10	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	7	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	7391	0	0
SrcPulseCheck_M	8053543	7391	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7391	0	0
T1	966072	10	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	7	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7391	0	0
T1	1951	10	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	7	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T35
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1232	0	0
SrcPulseCheck_M	1390629705	1314	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1232	0	0
T1	1951	16	0	0
T2	425	1	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	17	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1314	0	0
T1	966072	16	0	0
T2	27699	1	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	17	0	0
T9	13113	1	0	0
T10	0	9	0	0
T11	0	9	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T5,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T5,T35
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1292	0	0
SrcPulseCheck_M	8053543	1292	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1292	0	0
T1	966072	16	0	0
T2	27699	1	0	0
T3	146367	0	0	0
T4	47188	1	0	0
T5	0	17	0	0
T9	13113	1	0	0
T10	0	9	0	0
T11	0	8	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1292	0	0
T1	1951	16	0	0
T2	425	1	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	17	0	0
T9	437	1	0	0
T10	0	9	0	0
T11	0	8	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1208	0	0
SrcPulseCheck_M	1390629705	1294	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1208	0	0
T1	1951	7	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	8	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1294	0	0
T1	966072	7	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	8	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1271	0	0
SrcPulseCheck_M	8053543	1271	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1271	0	0
T1	966072	7	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	8	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1271	0	0
T1	1951	7	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	8	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1211	0	0
SrcPulseCheck_M	1390629705	1296	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1211	0	0
T1	1951	6	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	6	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1296	0	0
T1	966072	6	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	6	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1273	0	0
SrcPulseCheck_M	8053543	1273	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1273	0	0
T1	966072	6	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	6	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1273	0	0
T1	1951	6	0	0
T2	425	2	0	0
T3	1219	2	0	0
T4	524	1	0	0
T5	0	6	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1166	0	0
SrcPulseCheck_M	1390629705	1250	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1166	0	0
T1	1951	7	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	15	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1250	0	0
T1	966072	7	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	15	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1223	0	0
SrcPulseCheck_M	8053543	1223	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1223	0	0
T1	966072	7	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	15	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	8	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1223	0	0
T1	1951	7	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	15	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	8	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	8007	0	0
SrcPulseCheck_M	1390629705	8096	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	8007	0	0
T1	1951	22	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	5	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	13	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	8096	0	0
T1	966072	22	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	5	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	8070	0	0
SrcPulseCheck_M	8053543	8070	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	8070	0	0
T1	966072	22	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	5	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	16	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	8070	0	0
T1	1951	22	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	5	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	16	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	7718	0	0
SrcPulseCheck_M	1390629705	7806	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7718	0	0
T1	1951	12	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	21	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7806	0	0
T1	966072	12	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	21	0	0
T9	13113	1	0	0
T10	0	9	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	7783	0	0
SrcPulseCheck_M	8053543	7783	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7783	0	0
T1	966072	12	0	0
T2	27699	2	0	0
T3	146367	0	0	0
T4	47188	1	0	0
T5	0	21	0	0
T9	13113	1	0	0
T10	0	9	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7783	0	0
T1	1951	12	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	21	0	0
T9	437	1	0	0
T10	0	9	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	7830	0	0
SrcPulseCheck_M	1390629705	7915	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7830	0	0
T1	1951	4	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	16	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7915	0	0
T1	966072	6	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	16	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	7893	0	0
SrcPulseCheck_M	8053543	7893	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7893	0	0
T1	966072	5	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	16	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7893	0	0
T1	1951	5	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	16	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T35
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	7916	0	0
SrcPulseCheck_M	1390629705	8009	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7916	0	0
T1	1951	4	0	0
T2	425	1	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	7	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	13	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	8009	0	0
T1	966072	4	0	0
T2	27699	1	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	7	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T5,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T35
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	7985	0	0
SrcPulseCheck_M	8053543	7985	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	7985	0	0
T1	966072	4	0	0
T2	27699	1	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	7	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	8	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	7985	0	0
T1	1951	4	0	0
T2	425	1	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	7	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	8	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1865	0	0
SrcPulseCheck_M	1390629705	1955	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1865	0	0
T1	1951	10	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	15	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1955	0	0
T1	966072	10	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	15	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1930	0	0
SrcPulseCheck_M	8053543	1930	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1930	0	0
T1	966072	10	0	0
T2	27699	2	0	0
T3	146367	0	0	0
T4	47188	1	0	0
T5	0	15	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1930	0	0
T1	1951	10	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	15	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1793	0	0
SrcPulseCheck_M	1390629705	1875	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1793	0	0
T1	1951	3	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	14	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1875	0	0
T1	966072	3	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	14	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1855	0	0
SrcPulseCheck_M	8053543	1855	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1855	0	0
T1	966072	3	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	14	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1855	0	0
T1	1951	3	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	14	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1764	0	0
SrcPulseCheck_M	1390629705	1850	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1764	0	0
T1	1951	12	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	10	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1850	0	0
T1	966072	12	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	10	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1825	0	0
SrcPulseCheck_M	8053543	1825	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1825	0	0
T1	966072	12	0	0
T2	27699	2	0	0
T3	146367	0	0	0
T4	47188	1	0	0
T5	0	10	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1825	0	0
T1	1951	12	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	10	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T35
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1798	0	0
SrcPulseCheck_M	1390629705	1887	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1798	0	0
T1	1951	6	0	0
T2	425	1	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	12	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1887	0	0
T1	966072	6	0	0
T2	27699	1	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	12	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T35
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1863	0	0
SrcPulseCheck_M	8053543	1863	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1863	0	0
T1	966072	6	0	0
T2	27699	1	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	12	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1863	0	0
T1	1951	6	0	0
T2	425	1	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	12	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T35
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1925	0	0
SrcPulseCheck_M	1390629705	2013	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1925	0	0
T1	1951	17	0	0
T2	425	1	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	12	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	2013	0	0
T1	966072	17	0	0
T2	27699	1	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	12	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T5,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T35
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1989	0	0
SrcPulseCheck_M	8053543	1989	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1989	0	0
T1	966072	17	0	0
T2	27699	1	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	12	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1989	0	0
T1	1951	17	0	0
T2	425	1	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	12	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1788	0	0
SrcPulseCheck_M	1390629705	1871	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1788	0	0
T1	1951	4	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	16	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1871	0	0
T1	966072	4	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	16	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T13	0	20	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1850	0	0
SrcPulseCheck_M	8053543	1850	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1850	0	0
T1	966072	4	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	16	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1850	0	0
T1	1951	4	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	16	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1793	0	0
SrcPulseCheck_M	1390629705	1872	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1793	0	0
T1	1951	13	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	14	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	13	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1872	0	0
T1	966072	13	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	14	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1849	0	0
SrcPulseCheck_M	8053543	1849	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1849	0	0
T1	966072	13	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	14	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	8	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1849	0	0
T1	1951	13	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	14	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	8	0	0
T12	0	1	0	0
T13	0	17	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T35
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1783	0	0
SrcPulseCheck_M	1390629705	1871	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1783	0	0
T1	1951	5	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	1	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1871	0	0
T1	966072	5	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	1	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T35

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T35
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1390629705	1847	0	0
SrcPulseCheck_M	8053543	1847	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1847	0	0
T1	966072	5	0	0
T2	27699	2	0	0
T3	146367	1	0	0
T4	47188	1	0	0
T5	0	1	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1847	0	0
T1	1951	5	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	1	0	0
T9	437	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T13	0	18	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	1093	0	0
SrcPulseCheck_M	1390629705	1172	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	1093	0	0
T1	1951	7	0	0
T2	425	2	0	0
T3	1219	1	0	0
T4	524	1	0	0
T5	0	11	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	1172	0	0
T1	966072	7	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	11	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	10	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8053543	644	0	0
SrcPulseCheck_M	1390629705	731	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8053543	644	0	0
T1	1951	13	0	0
T2	425	2	0	0
T3	1219	0	0	0
T4	524	1	0	0
T5	0	18	0	0
T9	437	1	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	14	0	0
T24	434	0	0	0
T25	403	0	0	0
T26	406	0	0	0
T27	402	0	0	0
T28	403	0	0	0
T35	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1390629705	731	0	0
T1	966072	13	0	0
T2	27699	2	0	0
T3	146367	2	0	0
T4	47188	1	0	0
T5	0	18	0	0
T9	13113	1	0	0
T10	0	10	0	0
T11	0	9	0	0
T12	0	1	0	0
T24	54401	0	0	0
T25	94787	0	0	0
T26	44682	0	0	0
T27	201461	0	0	0
T28	193847	0	0	0
T59	0	1	0	0