Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T32,T33
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T32,T33
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T90,T99,T101

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T90,T99,T101

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T90,T99,T101

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T90,T99,T101
1	0	Covered	T15,T32,T33
1	1	Covered	T90,T99,T101

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T90,T99,T101
0	1	Covered	T123
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T90,T99,T101
0	1	Covered	T90,T99,T101
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T90,T99,T101
1	-	Covered	T90,T99,T101

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T90,T99,T101
0	1	Covered	T90,T99,T101
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T90,T99,T101
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T90,T99,T101
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T90,T99,T101
DebounceSt	-	0	1	0	-	-	-	Covered	T99,T100,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T90,T99,T101
DetectSt	-	-	-	-	1	-	-	Covered	T123
DetectSt	-	-	-	-	0	1	-	Covered	T90,T99,T101
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T90,T99,T101
StableSt	-	-	-	-	-	-	0	Covered	T90,T99,T101
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	284	0	0
CntIncr_A	5743868	118028	0	0
CntNoWrap_A	5743868	5092567	0	0
DetectStDropOut_A	5743868	1	0	0
DetectedOut_A	5743868	874	0	0
DetectedPulseOut_A	5743868	131	0	0
DisabledIdleSt_A	5743868	4968231	0	0
DisabledNoDetection_A	5743868	4970442	0	0
EnterDebounceSt_A	5743868	158	0	0
EnterDetectSt_A	5743868	132	0	0
EnterStableSt_A	5743868	131	0	0
PulseIsPulse_A	5743868	131	0	0
StayInStableSt	5743868	743	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5743868	6835	0	0
gen_low_level_sva.LowLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	131	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	284	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T55	550	0	0	0
T69	5338	0	0	0
T70	0	6	0	0
T72	0	4	0	0
T79	0	6	0	0
T84	492	0	0	0
T90	627	2	0	0
T99	0	3	0	0
T100	0	1	0	0
T101	0	2	0	0
T102	0	4	0	0
T103	0	2	0	0
T104	0	6	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	118028	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T55	550	0	0	0
T69	5338	0	0	0
T70	0	3900	0	0
T79	0	142	0	0
T84	492	0	0	0
T90	627	14	0	0
T99	0	123	0	0
T100	0	97	0	0
T101	0	51	0	0
T102	0	120	0	0
T103	0	28	0	0
T104	0	8878	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T109	0	893	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092567	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1	0	0
T123	703	1	0	0
T127	491	0	0	0
T128	14747	0	0	0
T129	14132	0	0	0
T130	424	0	0	0
T131	444	0	0	0
T132	4669	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	874	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T52	0	15	0	0
T55	550	0	0	0
T69	5338	0	0	0
T70	0	28	0	0
T72	0	13	0	0
T79	0	25	0	0
T84	492	0	0	0
T90	627	10	0	0
T99	0	7	0	0
T101	0	4	0	0
T102	0	15	0	0
T103	0	12	0	0
T104	0	17	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	131	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T52	0	2	0	0
T55	550	0	0	0
T69	5338	0	0	0
T70	0	3	0	0
T72	0	2	0	0
T79	0	3	0	0
T84	492	0	0	0
T90	627	1	0	0
T99	0	1	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	3	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4968231	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4970442	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	158	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T55	550	0	0	0
T69	5338	0	0	0
T70	0	4	0	0
T79	0	3	0	0
T84	492	0	0	0
T90	627	1	0	0
T99	0	2	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	3	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T109	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	132	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T52	0	2	0	0
T55	550	0	0	0
T69	5338	0	0	0
T70	0	3	0	0
T72	0	2	0	0
T79	0	3	0	0
T84	492	0	0	0
T90	627	1	0	0
T99	0	1	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	3	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	131	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T52	0	2	0	0
T55	550	0	0	0
T69	5338	0	0	0
T70	0	3	0	0
T72	0	2	0	0
T79	0	3	0	0
T84	492	0	0	0
T90	627	1	0	0
T99	0	1	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	3	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	131	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T52	0	2	0	0
T55	550	0	0	0
T69	5338	0	0	0
T70	0	3	0	0
T72	0	2	0	0
T79	0	3	0	0
T84	492	0	0	0
T90	627	1	0	0
T99	0	1	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	3	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	743	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T52	0	13	0	0
T55	550	0	0	0
T69	5338	0	0	0
T70	0	25	0	0
T72	0	11	0	0
T79	0	22	0	0
T84	492	0	0	0
T90	627	9	0	0
T99	0	6	0	0
T101	0	3	0	0
T102	0	13	0	0
T103	0	11	0	0
T104	0	14	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	6835	0	0
T15	25917	8	0	0
T16	2477	5	0	0
T17	9820	17	0	0
T32	463	3	0	0
T33	437	7	0	0
T34	504	5	0	0
T35	6387	26	0	0
T36	1404	12	0	0
T37	421	2	0	0
T38	4966	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	131	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T52	0	2	0	0
T55	550	0	0	0
T69	5338	0	0	0
T70	0	3	0	0
T72	0	2	0	0
T79	0	3	0	0
T84	492	0	0	0
T90	627	1	0	0
T99	0	1	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	3	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T32,T33
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T32,T33
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T18,T49,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T18,T49,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T18,T49,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T49,T50
1	0	Covered	T15,T32,T33
1	1	Covered	T18,T49,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T49,T50
0	1	Covered	T80,T97,T98
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T49,T50
0	1	Unreachable
1	0	Covered	T18,T49,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T49,T50
0	1	Covered	T18,T49,T50
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T49,T50
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T49,T50
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T49,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T133,T91
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T49,T50
DetectSt	-	-	-	-	1	-	-	Covered	T80,T97,T98
DetectSt	-	-	-	-	0	1	-	Covered	T18,T49,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T49,T50
StableSt	-	-	-	-	-	-	0	Covered	T18,T49,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	155	0	0
CntIncr_A	5743868	119743	0	0
CntNoWrap_A	5743868	5092696	0	0
DetectStDropOut_A	5743868	11	0	0
DetectedOut_A	5743868	15132	0	0
DetectedPulseOut_A	5743868	41	0	0
DisabledIdleSt_A	5743868	4806262	0	0
DisabledNoDetection_A	5743868	4808524	0	0
EnterDebounceSt_A	5743868	103	0	0
EnterDetectSt_A	5743868	52	0	0
EnterStableSt_A	5743868	41	0	0
PulseIsPulse_A	5743868	41	0	0
StayInStableSt	5743868	15091	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5743868	6835	0	0
gen_low_level_sva.LowLevelEvent_A	5743868	5095117	0	0
gen_sticky_sva.StableStDropOut_A	5743868	136100	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	155	0	0
T18	1663	2	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	2	0	0
T50	0	2	0	0
T63	10230	0	0	0
T71	0	2	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	6	0	0
T81	0	2	0	0
T82	0	2	0	0
T94	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	119743	0	0
T18	1663	70	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	74	0	0
T50	0	43	0	0
T63	10230	0	0	0
T71	0	51	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	75	0	0
T79	0	37	0	0
T80	0	205	0	0
T81	0	16	0	0
T82	0	38	0	0
T94	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092696	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	11	0	0
T62	8585	0	0	0
T80	11898	2	0	0
T97	1054	1	0	0
T98	0	1	0	0
T138	0	5	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	526	0	0	0
T142	402	0	0	0
T143	495	0	0	0
T144	736	0	0	0
T145	29796	0	0	0
T146	30764	0	0	0
T147	454	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	15132	0	0
T18	1663	389	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	14	0	0
T50	0	24	0	0
T63	10230	0	0	0
T71	0	348	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	303	0	0
T79	0	102	0	0
T80	0	176	0	0
T81	0	45	0	0
T82	0	11	0	0
T83	0	7956	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	41	0	0
T18	1663	1	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	1	0	0
T50	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4806262	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4808524	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	103	0	0
T18	1663	1	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	1	0	0
T50	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T94	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	52	0	0
T18	1663	1	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	1	0	0
T50	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	41	0	0
T18	1663	1	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	1	0	0
T50	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	41	0	0
T18	1663	1	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	1	0	0
T50	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	15091	0	0
T18	1663	388	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	13	0	0
T50	0	23	0	0
T63	10230	0	0	0
T71	0	347	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	302	0	0
T79	0	101	0	0
T80	0	175	0	0
T81	0	44	0	0
T82	0	10	0	0
T83	0	7955	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	6835	0	0
T15	25917	8	0	0
T16	2477	5	0	0
T17	9820	17	0	0
T32	463	3	0	0
T33	437	7	0	0
T34	504	5	0	0
T35	6387	26	0	0
T36	1404	12	0	0
T37	421	2	0	0
T38	4966	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	136100	0	0
T18	1663	150	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	77	0	0
T50	0	54	0	0
T63	10230	0	0	0
T71	0	170	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	161	0	0
T79	0	192	0	0
T80	0	5407	0	0
T81	0	97	0	0
T82	0	125	0	0
T83	0	72	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T32,T33,T34

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T15,T32
1	0	Covered	T32,T33,T34
1	1	Covered	T32,T33,T34

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T18,T49,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T18,T49,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T18,T50,T78

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T49,T50
1	0	Covered	T32,T33,T34
1	1	Covered	T18,T49,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T50,T78
0	1	Covered	T80,T94,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T50,T78
0	1	Unreachable
1	0	Covered	T18,T50,T78

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T49,T50
0	1	Covered	T18,T49,T50
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T50,T78
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T49,T50
IdleSt	0	-	-	-	-	-	-	Covered	T32,T33,T34
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T50,T78
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T71,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T49,T50
DetectSt	-	-	-	-	1	-	-	Covered	T80,T94,T96
DetectSt	-	-	-	-	0	1	-	Covered	T18,T50,T78
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T50,T78
StableSt	-	-	-	-	-	-	0	Covered	T18,T50,T78
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	153	0	0
CntIncr_A	5743868	41242	0	0
CntNoWrap_A	5743868	5092698	0	0
DetectStDropOut_A	5743868	14	0	0
DetectedOut_A	5743868	19642	0	0
DetectedPulseOut_A	5743868	47	0	0
DisabledIdleSt_A	5743868	4806262	0	0
DisabledNoDetection_A	5743868	4808524	0	0
EnterDebounceSt_A	5743868	92	0	0
EnterDetectSt_A	5743868	61	0	0
EnterStableSt_A	5743868	47	0	0
PulseIsPulse_A	5743868	47	0	0
StayInStableSt	5743868	19595	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_sticky_sva.StableStDropOut_A	5743868	154647	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	153	0	0
T18	1663	2	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	1	0	0
T50	0	2	0	0
T63	10230	0	0	0
T71	0	5	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	2	0	0
T79	0	2	0	0
T80	0	6	0	0
T81	0	2	0	0
T82	0	2	0	0
T94	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	41242	0	0
T18	1663	27	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	75	0	0
T50	0	10	0	0
T63	10230	0	0	0
T71	0	355	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	85	0	0
T79	0	99	0	0
T80	0	1074	0	0
T81	0	130	0	0
T82	0	46	0	0
T94	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092698	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	14	0	0
T52	5795	0	0	0
T80	11898	2	0	0
T94	515	1	0	0
T96	0	2	0	0
T141	526	0	0	0
T142	402	0	0	0
T143	495	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	2	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	580	0	0	0
T155	408	0	0	0
T156	641	0	0	0
T157	32476	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	19642	0	0
T18	1663	199	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T50	565	1	0	0
T57	0	261	0	0
T63	10230	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T78	1404	374	0	0
T79	0	177	0	0
T80	0	4507	0	0
T82	0	40	0	0
T83	0	48	0	0
T133	0	417	0	0
T134	0	597	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	47	0	0
T18	1663	1	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T50	565	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T78	1404	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4806262	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4808524	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	92	0	0
T18	1663	1	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	1	0	0
T50	0	1	0	0
T63	10230	0	0	0
T71	0	5	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	3	0	0
T81	0	2	0	0
T82	0	1	0	0
T94	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	61	0	0
T18	1663	1	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T50	565	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T78	1404	1	0	0
T79	0	1	0	0
T80	0	3	0	0
T82	0	1	0	0
T83	0	1	0	0
T94	0	1	0	0
T133	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	47	0	0
T18	1663	1	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T50	565	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T78	1404	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	47	0	0
T18	1663	1	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T50	565	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T78	1404	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	19595	0	0
T18	1663	198	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T56	722	0	0	0
T57	0	260	0	0
T63	10230	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T78	1404	373	0	0
T79	0	176	0	0
T80	0	4506	0	0
T82	0	39	0	0
T83	0	47	0	0
T95	0	19	0	0
T133	0	416	0	0
T134	0	596	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	154647	0	0
T18	1663	387	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T50	565	122	0	0
T57	0	74	0	0
T63	10230	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T78	1404	89	0	0
T79	0	51	0	0
T80	0	78	0	0
T82	0	77	0	0
T83	0	11307	0	0
T133	0	280	0	0
T134	0	87	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T32,T33

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T18,T49,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T18,T49,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T49,T78,T79

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T49,T50
1	0	Covered	T15,T32,T33
1	1	Covered	T18,T49,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T49,T79,T80
0	1	Covered	T78,T94,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T79,T80
0	1	Unreachable
1	0	Covered	T49,T79,T80

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T49,T50
0	1	Covered	T18,T49,T50
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T49,T78,T79
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T49,T50
IdleSt	0	-	-	-	-	-	-	Covered	T15,T32,T33
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T49,T78,T79
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T50,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T49,T50
DetectSt	-	-	-	-	1	-	-	Covered	T78,T94,T95
DetectSt	-	-	-	-	0	1	-	Covered	T49,T79,T80
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T49,T79,T80
StableSt	-	-	-	-	-	-	0	Covered	T49,T79,T80
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	155	0	0
CntIncr_A	5743868	43569	0	0
CntNoWrap_A	5743868	5092696	0	0
DetectStDropOut_A	5743868	12	0	0
DetectedOut_A	5743868	59877	0	0
DetectedPulseOut_A	5743868	36	0	0
DisabledIdleSt_A	5743868	4806262	0	0
DisabledNoDetection_A	5743868	4808524	0	0
EnterDebounceSt_A	5743868	107	0	0
EnterDetectSt_A	5743868	48	0	0
EnterStableSt_A	5743868	36	0	0
PulseIsPulse_A	5743868	36	0	0
StayInStableSt	5743868	59841	0	0
gen_high_event_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_sticky_sva.StableStDropOut_A	5743868	132293	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	155	0	0
T18	1663	5	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	2	0	0
T50	0	1	0	0
T63	10230	0	0	0
T71	0	2	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	7	0	0
T79	0	2	0	0
T80	0	4	0	0
T81	0	2	0	0
T82	0	2	0	0
T94	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	43569	0	0
T18	1663	115	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	80	0	0
T50	0	38	0	0
T63	10230	0	0	0
T71	0	50	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	300	0	0
T79	0	35	0	0
T80	0	285	0	0
T81	0	11	0	0
T82	0	79	0	0
T94	0	15	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092696	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	12	0	0
T56	722	0	0	0
T59	23656	0	0	0
T60	1089	0	0	0
T70	31534	0	0	0
T78	1404	3	0	0
T79	8000	0	0	0
T80	11898	0	0	0
T94	0	1	0	0
T95	0	1	0	0
T100	2017	0	0	0
T125	0	3	0	0
T136	689	0	0	0
T137	495	0	0	0
T138	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	59877	0	0
T49	1274	75	0	0
T57	0	119	0	0
T60	1089	0	0	0
T70	31534	0	0	0
T71	0	348	0	0
T77	11612	0	0	0
T79	8000	42	0	0
T80	11898	426	0	0
T81	0	19	0	0
T82	0	75	0	0
T83	0	292	0	0
T100	2017	0	0	0
T125	0	1	0	0
T134	0	90	0	0
T135	421	0	0	0
T136	689	0	0	0
T137	495	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	36	0	0
T49	1274	1	0	0
T57	0	1	0	0
T60	1089	0	0	0
T70	31534	0	0	0
T71	0	1	0	0
T77	11612	0	0	0
T79	8000	1	0	0
T80	11898	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T100	2017	0	0	0
T125	0	1	0	0
T134	0	1	0	0
T135	421	0	0	0
T136	689	0	0	0
T137	495	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4806262	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4808524	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	107	0	0
T18	1663	5	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T49	1274	1	0	0
T50	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T78	0	4	0	0
T79	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	1	0	0
T94	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	48	0	0
T49	1274	1	0	0
T56	722	0	0	0
T57	0	1	0	0
T59	23656	0	0	0
T60	1089	0	0	0
T71	0	1	0	0
T77	11612	0	0	0
T78	1404	3	0	0
T79	8000	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T94	0	1	0	0
T100	2017	0	0	0
T135	421	0	0	0
T136	689	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	36	0	0
T49	1274	1	0	0
T57	0	1	0	0
T60	1089	0	0	0
T70	31534	0	0	0
T71	0	1	0	0
T77	11612	0	0	0
T79	8000	1	0	0
T80	11898	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T100	2017	0	0	0
T125	0	1	0	0
T134	0	1	0	0
T135	421	0	0	0
T136	689	0	0	0
T137	495	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	36	0	0
T49	1274	1	0	0
T57	0	1	0	0
T60	1089	0	0	0
T70	31534	0	0	0
T71	0	1	0	0
T77	11612	0	0	0
T79	8000	1	0	0
T80	11898	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T100	2017	0	0	0
T125	0	1	0	0
T134	0	1	0	0
T135	421	0	0	0
T136	689	0	0	0
T137	495	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	59841	0	0
T49	1274	74	0	0
T57	0	118	0	0
T60	1089	0	0	0
T70	31534	0	0	0
T71	0	347	0	0
T77	11612	0	0	0
T79	8000	41	0	0
T80	11898	425	0	0
T81	0	18	0	0
T82	0	74	0	0
T83	0	291	0	0
T100	2017	0	0	0
T134	0	89	0	0
T135	421	0	0	0
T136	689	0	0	0
T137	495	0	0	0
T158	0	16	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	132293	0	0
T49	1274	26	0	0
T57	0	275	0	0
T60	1089	0	0	0
T70	31534	0	0	0
T71	0	173	0	0
T77	11612	0	0	0
T79	8000	257	0	0
T80	11898	5121	0	0
T81	0	135	0	0
T82	0	29	0	0
T83	0	10998	0	0
T100	2017	0	0	0
T125	0	155	0	0
T134	0	686	0	0
T135	421	0	0	0
T136	689	0	0	0
T137	495	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T15,T32
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T51,T56

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T17,T51,T56

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T51,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T23,T51
1	0	Covered	T48,T15,T32
1	1	Covered	T17,T51,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T51,T56
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T51,T56
0	1	Covered	T17,T51,T159
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T51,T56
1	-	Covered	T17,T51,T159

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T51,T56
0	1	Covered	T17,T51,T56
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T51,T56
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T51,T56
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T51,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T160,T161
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T51,T56
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T17,T51,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T51,T53
StableSt	-	-	-	-	-	-	0	Covered	T17,T51,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	82	0	0
CntIncr_A	5743868	55763	0	0
CntNoWrap_A	5743868	5092769	0	0
DetectStDropOut_A	5743868	0	0	0
DetectedOut_A	5743868	53612	0	0
DetectedPulseOut_A	5743868	40	0	0
DisabledIdleSt_A	5743868	4807930	0	0
DisabledNoDetection_A	5743868	4810144	0	0
EnterDebounceSt_A	5743868	42	0	0
EnterDetectSt_A	5743868	40	0	0
EnterStableSt_A	5743868	40	0	0
PulseIsPulse_A	5743868	40	0	0
StayInStableSt	5743868	53550	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	82	0	0
T17	9820	4	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	8	0	0
T53	0	2	0	0
T56	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	10230	0	0	0
T71	0	2	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T133	0	2	0	0
T159	0	4	0	0
T160	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	55763	0	0
T17	9820	142	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	53720	0	0
T53	0	22	0	0
T56	0	100	0	0
T61	0	70	0	0
T62	0	87	0	0
T63	10230	0	0	0
T71	0	81	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T133	0	11	0	0
T159	0	120	0	0
T160	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092769	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	53612	0	0
T17	9820	77	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	50547	0	0
T53	0	4	0	0
T56	0	42	0	0
T61	0	51	0	0
T62	0	158	0	0
T63	10230	0	0	0
T71	0	50	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T133	0	43	0	0
T159	0	236	0	0
T160	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	40	0	0
T17	9820	2	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	4	0	0
T53	0	1	0	0
T56	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T133	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4807930	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4810144	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	42	0	0
T17	9820	2	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	4	0	0
T53	0	1	0	0
T56	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T133	0	1	0	0
T159	0	2	0	0
T160	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	40	0	0
T17	9820	2	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	4	0	0
T53	0	1	0	0
T56	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T133	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	40	0	0
T17	9820	2	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	4	0	0
T53	0	1	0	0
T56	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T133	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	40	0	0
T17	9820	2	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	4	0	0
T53	0	1	0	0
T56	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T133	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	53550	0	0
T17	9820	74	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	50542	0	0
T53	0	3	0	0
T56	0	40	0	0
T61	0	50	0	0
T62	0	156	0	0
T63	10230	0	0	0
T71	0	48	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T133	0	41	0	0
T159	0	233	0	0
T160	0	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	16	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	3	0	0
T61	0	1	0	0
T63	10230	0	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T15,T32
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T51,T56

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T17,T51,T56

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T51,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T51,T56
1	0	Covered	T15,T32,T33
1	1	Covered	T17,T51,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T51,T56
0	1	Covered	T17
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T51,T56
0	1	Covered	T17,T51,T56
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T51,T56
1	-	Covered	T17,T51,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T51,T56
0	1	Covered	T17,T51,T56
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T51,T56
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T51,T56
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T51,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T167,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T51,T56
DetectSt	-	-	-	-	1	-	-	Covered	T17
DetectSt	-	-	-	-	0	1	-	Covered	T17,T51,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T51,T56
StableSt	-	-	-	-	-	-	0	Covered	T17,T51,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	123	0	0
CntIncr_A	5743868	115376	0	0
CntNoWrap_A	5743868	5092728	0	0
DetectStDropOut_A	5743868	1	0	0
DetectedOut_A	5743868	35585	0	0
DetectedPulseOut_A	5743868	57	0	0
DisabledIdleSt_A	5743868	4836101	0	0
DisabledNoDetection_A	5743868	4838315	0	0
EnterDebounceSt_A	5743868	67	0	0
EnterDetectSt_A	5743868	58	0	0
EnterStableSt_A	5743868	57	0	0
PulseIsPulse_A	5743868	57	0	0
StayInStableSt	5743868	35505	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5743868	2593	0	0
gen_low_level_sva.LowLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	123	0	0
T17	9820	4	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	9	0	0
T53	0	2	0	0
T56	0	2	0	0
T57	0	2	0	0
T59	0	2	0	0
T63	10230	0	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T95	0	2	0	0
T159	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	115376	0	0
T17	9820	142	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	80518	0	0
T53	0	22	0	0
T56	0	100	0	0
T57	0	88	0	0
T59	0	73	0	0
T63	10230	0	0	0
T71	0	81	0	0
T72	0	16	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T95	0	94	0	0
T169	0	3	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092728	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T63	10230	0	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	35585	0	0
T17	9820	12	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	18087	0	0
T53	0	3	0	0
T56	0	70	0	0
T57	0	43	0	0
T59	0	46	0	0
T63	10230	0	0	0
T71	0	47	0	0
T72	0	112	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T95	0	214	0	0
T159	0	53	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	57	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	4	0	0
T53	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T95	0	1	0	0
T159	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4836101	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4838315	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	67	0	0
T17	9820	2	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	5	0	0
T53	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T95	0	1	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	58	0	0
T17	9820	2	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	4	0	0
T53	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T95	0	1	0	0
T159	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	57	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	4	0	0
T53	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T95	0	1	0	0
T159	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	57	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	4	0	0
T53	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T95	0	1	0	0
T159	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	35505	0	0
T17	9820	11	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	18081	0	0
T53	0	2	0	0
T56	0	69	0	0
T57	0	41	0	0
T59	0	45	0	0
T63	10230	0	0	0
T71	0	46	0	0
T72	0	110	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T95	0	212	0	0
T159	0	51	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	2593	0	0
T16	2477	7	0	0
T17	9820	8	0	0
T32	463	6	0	0
T33	437	3	0	0
T34	504	7	0	0
T35	6387	0	0	0
T36	1404	13	0	0
T37	421	2	0	0
T38	4966	0	0	0
T73	447	3	0	0
T74	0	4	0	0
T75	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	32	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T51	0	2	0	0
T54	0	2	0	0
T56	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T159	0	2	0	0
T168	0	1	0	0