Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	89.69	91.30	90.48		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	92.41	93.48	95.24		83.33	90.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	92.41	93.48	95.24		83.33	90.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
92.41	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
92.41	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
89.69	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T35,T16
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T35,T16
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T35,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T35,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T16,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T35,T16
1	0	Covered	T15,T35,T16
1	1	Covered	T15,T35,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T17,T24,T83
1	0	Covered	T53,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T16,T17
1	0	Covered	T53,T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T16,T17
1	-	Covered	T15,T16,T17

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
92.41	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
92.41	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T15,T32
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T23,T90

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T23,T90

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T23,T90

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T23,T90
1	0	Covered	T15,T32,T33
1	1	Covered	T17,T23,T90

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T23,T90
0	1	Covered	T17,T91,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T23,T90
0	1	Covered	T17,T23,T90
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T23,T90
1	-	Covered	T17,T23,T90

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T35,T38,T20
1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T38,T20
1	0	Covered	T35,T20,T63
1	1	Covered	T35,T38,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T38,T20
0	1	Covered	T35,T38,T20
1	0	Covered	T35,T20,T65

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T20,T63
0	1	Covered	T35,T20,T63
1	0	Covered	T53,T93,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T20,T63
1	-	Covered	T35,T20,T63

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T32,T33

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T18,T49,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T18,T49,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T49,T78,T79

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T49,T50
1	0	Covered	T15,T32,T33
1	1	Covered	T18,T49,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T49,T79,T80
0	1	Covered	T78,T94,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T79,T80
0	1	Unreachable
1	0	Covered	T49,T79,T80

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
89.69	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T15,T32
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T23,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T23,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T23,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T23,T51
1	0	Covered	T48,T15,T32
1	1	Covered	T17,T23,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T23,T51
0	1	Covered	T72,T58,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T23,T51
0	1	Covered	T17,T23,T51
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T23,T51
1	-	Covered	T17,T23,T51

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T32,T33,T34

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T15,T32
1	0	Covered	T32,T33,T34
1	1	Covered	T32,T33,T34

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T18,T49,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T18,T49,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T18,T50,T78

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T49,T50
1	0	Covered	T32,T33,T34
1	1	Covered	T18,T49,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T50,T78
0	1	Covered	T80,T94,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T50,T78
0	1	Unreachable
1	0	Covered	T18,T50,T78

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T32,T33
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T32,T33
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T18,T49,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T18,T49,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T18,T49,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T49,T50
1	0	Covered	T15,T32,T33
1	1	Covered	T18,T49,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T49,T50
0	1	Covered	T80,T97,T98
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T49,T50
0	1	Unreachable
1	0	Covered	T18,T49,T50

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
92.41	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
92.41	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
89.69	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T23,T90
0	1	Covered	T17,T23,T90
0	0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T23,T90
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T17,T23,T90
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T23,T90
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T99,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T23,T90
DetectSt	-	-	-	-	1	-	-	Covered	T17,T80,T94
DetectSt	-	-	-	-	0	1	-	Covered	T17,T23,T90
DetectSt	-	-	-	-	0	0	-	Covered	T15,T16,T17
StableSt	-	-	-	-	-	-	1	Covered	T17,T23,T90
StableSt	-	-	-	-	-	-	0	Covered	T17,T23,T90
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T38,T18
0	1	Covered	T35,T38,T18
0	0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T38,T20
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T35,T38,T18
IdleSt	0	-	-	-	-	-	-	Covered	T15,T32,T33
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T38,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T50,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T38,T18
DetectSt	-	-	-	-	1	-	-	Covered	T35,T38,T20
DetectSt	-	-	-	-	0	1	-	Covered	T35,T20,T63
DetectSt	-	-	-	-	0	0	-	Covered	T35,T38,T20
StableSt	-	-	-	-	-	-	1	Covered	T35,T20,T63
StableSt	-	-	-	-	-	-	0	Covered	T35,T20,T63
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	149340568	17646	0	0
CntIncr_A	149340568	1704688	0	0
CntNoWrap_A	149340568	132396480	0	0
DetectStDropOut_A	149340568	1591	0	0
DetectedOut_A	149340568	808806	0	0
DetectedPulseOut_A	149340568	6065	0	0
DisabledIdleSt_A	149340568	125212242	0	0
DisabledNoDetection_A	149340568	125267040	0	0
EnterDebounceSt_A	149340568	9127	0	0
EnterDetectSt_A	149340568	8547	0	0
EnterStableSt_A	149340568	6065	0	0
PulseIsPulse_A	149340568	6065	0	0
StayInStableSt	149340568	801942	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	51694812	50925	0	0
gen_high_event_sva.HighLevelEvent_A	28719340	25475585	0	0
gen_high_level_sva.HighLevelEvent_A	97645756	86616989	0	0
gen_low_level_sva.LowLevelEvent_A	51694812	45856053	0	0
gen_not_sticky_sva.StableStDropOut_A	132108964	5079	0	0
gen_sticky_sva.StableStDropOut_A	17231604	423040	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149340568	17646	0	0
T15	25917	14	0	0
T16	4954	2	0	0
T17	19640	5	0	0
T19	0	24	0	0
T20	0	30	0	0
T21	0	8	0	0
T22	0	27	0	0
T24	4149	2	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	12774	19	0	0
T36	2808	0	0	0
T37	842	0	0	0
T38	9932	12	0	0
T51	232339	5	0	0
T55	550	0	0	0
T69	5338	0	0	0
T70	0	6	0	0
T72	0	4	0	0
T73	447	0	0	0
T79	0	6	0	0
T84	492	0	0	0
T90	627	2	0	0
T99	0	3	0	0
T100	0	1	0	0
T101	0	2	0	0
T102	0	4	0	0
T103	0	2	0	0
T104	0	6	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149340568	1704688	0	0
T15	25917	804	0	0
T16	4954	25	0	0
T17	19640	177	0	0
T19	0	2044	0	0
T20	0	1185	0	0
T21	0	244	0	0
T22	0	2127	0	0
T24	4149	43	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	12774	482	0	0
T36	2808	0	0	0
T37	842	0	0	0
T38	9932	277	0	0
T51	232339	70	0	0
T55	550	0	0	0
T69	5338	0	0	0
T70	0	3900	0	0
T73	447	0	0	0
T79	0	142	0	0
T84	492	0	0	0
T90	627	14	0	0
T99	0	123	0	0
T100	0	97	0	0
T101	0	51	0	0
T102	0	120	0	0
T103	0	28	0	0
T104	0	8878	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T109	0	893	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149340568	132396480	0	0
T15	673842	661782	0	0
T16	64402	5562	0	0
T32	12038	1612	0	0
T33	11362	936	0	0
T34	13104	2678	0	0
T35	166062	155561	0	0
T36	36504	5252	0	0
T37	10946	520	0	0
T38	129116	118542	0	0
T48	218478	52	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149340568	1591	0	0
T17	19640	1	0	0
T18	3326	0	0	0
T19	67346	0	0	0
T20	67180	0	0	0
T21	15340	0	0	0
T24	0	1	0	0
T38	4966	6	0	0
T63	20460	0	0	0
T65	0	10	0	0
T73	894	0	0	0
T74	996	0	0	0
T75	816	0	0	0
T76	882	0	0	0
T83	0	5	0	0
T91	0	1	0	0
T95	29444	0	0	0
T110	0	11	0	0
T111	0	22	0	0
T112	0	21	0	0
T113	0	5	0	0
T114	0	10	0	0
T115	0	10	0	0
T116	0	5	0	0
T117	0	5	0	0
T118	0	1	0	0
T119	0	8	0	0
T120	0	5	0	0
T121	0	3	0	0
T122	0	2	0	0
T123	703	1	0	0
T124	0	3	0	0
T125	1518	0	0	0
T126	502	0	0	0
T127	491	0	0	0
T128	14747	0	0	0
T129	14132	0	0	0
T130	424	0	0	0
T131	444	0	0	0
T132	4669	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149340568	808806	0	0
T15	25917	97	0	0
T16	4954	3	0	0
T17	19640	3	0	0
T19	0	183	0	0
T20	0	1701	0	0
T21	0	154	0	0
T22	0	257	0	0
T24	4149	0	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	12774	1212	0	0
T36	2808	0	0	0
T37	842	0	0	0
T38	9932	0	0	0
T51	232339	6	0	0
T52	0	15	0	0
T55	550	0	0	0
T69	5338	31	0	0
T70	0	28	0	0
T72	0	13	0	0
T73	447	0	0	0
T77	0	21	0	0
T79	0	25	0	0
T84	492	0	0	0
T90	627	10	0	0
T99	0	7	0	0
T101	0	4	0	0
T102	0	15	0	0
T103	0	12	0	0
T104	0	17	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149340568	6065	0	0
T15	25917	6	0	0
T16	4954	1	0	0
T17	19640	1	0	0
T19	0	11	0	0
T20	0	15	0	0
T21	0	4	0	0
T22	0	12	0	0
T24	4149	0	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	12774	9	0	0
T36	2808	0	0	0
T37	842	0	0	0
T38	9932	0	0	0
T51	232339	2	0	0
T52	0	2	0	0
T55	550	0	0	0
T69	5338	5	0	0
T70	0	3	0	0
T72	0	2	0	0
T73	447	0	0	0
T77	0	2	0	0
T79	0	3	0	0
T84	492	0	0	0
T90	627	1	0	0
T99	0	1	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	3	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149340568	125212242	0	0
T15	673842	640590	0	0
T16	64402	5477	0	0
T32	12038	1612	0	0
T33	11362	936	0	0
T34	13104	2678	0	0
T35	166062	142197	0	0
T36	36504	5252	0	0
T37	10946	520	0	0
T38	129116	108486	0	0
T48	218478	52	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149340568	125267040	0	0
T15	673842	640810	0	0
T16	64402	5606	0	0
T32	12038	1638	0	0
T33	11362	962	0	0
T34	13104	2704	0	0
T35	166062	142219	0	0
T36	36504	5304	0	0
T37	10946	546	0	0
T38	129116	108508	0	0
T48	218478	78	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149340568	9127	0	0
T15	25917	8	0	0
T16	4954	1	0	0
T17	19640	3	0	0
T19	0	13	0	0
T20	0	15	0	0
T21	0	4	0	0
T22	0	15	0	0
T24	4149	1	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	12774	10	0	0
T36	2808	0	0	0
T37	842	0	0	0
T38	9932	6	0	0
T51	232339	3	0	0
T55	550	0	0	0
T69	5338	0	0	0
T70	0	4	0	0
T73	447	0	0	0
T79	0	3	0	0
T84	492	0	0	0
T90	627	1	0	0
T99	0	2	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	3	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T109	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149340568	8547	0	0
T15	25917	6	0	0
T16	4954	1	0	0
T17	19640	2	0	0
T19	0	11	0	0
T20	0	15	0	0
T21	0	4	0	0
T22	0	12	0	0
T24	4149	1	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	12774	9	0	0
T36	2808	0	0	0
T37	842	0	0	0
T38	9932	0	0	0
T51	232339	2	0	0
T52	0	2	0	0
T55	550	0	0	0
T69	5338	5	0	0
T70	0	3	0	0
T72	0	2	0	0
T73	447	0	0	0
T79	0	3	0	0
T84	492	0	0	0
T90	627	1	0	0
T99	0	1	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	3	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149340568	6065	0	0
T15	25917	6	0	0
T16	4954	1	0	0
T17	19640	1	0	0
T19	0	11	0	0
T20	0	15	0	0
T21	0	4	0	0
T22	0	12	0	0
T24	4149	0	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	12774	9	0	0
T36	2808	0	0	0
T37	842	0	0	0
T38	9932	0	0	0
T51	232339	2	0	0
T52	0	2	0	0
T55	550	0	0	0
T69	5338	5	0	0
T70	0	3	0	0
T72	0	2	0	0
T73	447	0	0	0
T77	0	2	0	0
T79	0	3	0	0
T84	492	0	0	0
T90	627	1	0	0
T99	0	1	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	3	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149340568	6065	0	0
T15	25917	6	0	0
T16	4954	1	0	0
T17	19640	1	0	0
T19	0	11	0	0
T20	0	15	0	0
T21	0	4	0	0
T22	0	12	0	0
T24	4149	0	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	12774	9	0	0
T36	2808	0	0	0
T37	842	0	0	0
T38	9932	0	0	0
T51	232339	2	0	0
T52	0	2	0	0
T55	550	0	0	0
T69	5338	5	0	0
T70	0	3	0	0
T72	0	2	0	0
T73	447	0	0	0
T77	0	2	0	0
T79	0	3	0	0
T84	492	0	0	0
T90	627	1	0	0
T99	0	1	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	3	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	149340568	801942	0	0
T15	25917	91	0	0
T16	4954	2	0	0
T17	19640	2	0	0
T19	0	172	0	0
T20	0	1677	0	0
T21	0	150	0	0
T22	0	245	0	0
T24	4149	0	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	12774	1203	0	0
T36	2808	0	0	0
T37	842	0	0	0
T38	9932	0	0	0
T51	232339	4	0	0
T52	0	13	0	0
T55	550	0	0	0
T69	5338	26	0	0
T70	0	25	0	0
T72	0	11	0	0
T73	447	0	0	0
T77	0	19	0	0
T79	0	22	0	0
T84	492	0	0	0
T90	627	9	0	0
T99	0	6	0	0
T101	0	3	0	0
T102	0	13	0	0
T103	0	11	0	0
T104	0	14	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51694812	50925	0	0
T15	181419	73	0	0
T16	22293	46	0	0
T17	88380	99	0	0
T32	4167	45	0	0
T33	3933	52	0	0
T34	4536	46	0	0
T35	57483	178	0	0
T36	12636	103	0	0
T37	3789	19	0	0
T38	44694	181	0	0
T73	894	6	0	0
T74	0	10	0	0
T75	0	1	0	0
T76	0	4	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28719340	25475585	0	0
T15	129585	127325	0	0
T16	12385	1095	0	0
T32	2315	315	0	0
T33	2185	185	0	0
T34	2520	520	0	0
T35	31935	29935	0	0
T36	7020	1020	0	0
T37	2105	105	0	0
T38	24830	22830	0	0
T48	42015	15	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97645756	86616989	0	0
T15	440589	432905	0	0
T16	42109	3723	0	0
T32	7871	1071	0	0
T33	7429	629	0	0
T34	8568	1768	0	0
T35	108579	101779	0	0
T36	23868	3468	0	0
T37	7157	357	0	0
T38	84422	77622	0	0
T48	142851	51	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51694812	45856053	0	0
T15	233253	229185	0	0
T16	22293	1971	0	0
T32	4167	567	0	0
T33	3933	333	0	0
T34	4536	936	0	0
T35	57483	53883	0	0
T36	12636	1836	0	0
T37	3789	189	0	0
T38	44694	41094	0	0
T48	75627	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132108964	5079	0	0
T15	25917	6	0	0
T16	4954	1	0	0
T17	19640	1	0	0
T19	0	11	0	0
T20	0	6	0	0
T21	0	4	0	0
T22	0	12	0	0
T24	4149	0	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	12774	9	0	0
T36	2808	0	0	0
T37	842	0	0	0
T38	9932	0	0	0
T51	232339	2	0	0
T52	0	2	0	0
T55	550	0	0	0
T69	5338	5	0	0
T70	0	3	0	0
T72	0	2	0	0
T73	447	0	0	0
T77	0	2	0	0
T79	0	3	0	0
T84	492	0	0	0
T90	627	1	0	0
T99	0	1	0	0
T101	0	2	0	0
T102	0	2	0	0
T103	0	1	0	0
T104	0	3	0	0
T105	427	0	0	0
T106	445	0	0	0
T107	429	0	0	0
T108	505	0	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17231604	423040	0	0
T18	3326	537	0	0
T19	67346	0	0	0
T20	67180	0	0	0
T21	15340	0	0	0
T49	2548	103	0	0
T50	565	176	0	0
T57	0	349	0	0
T60	1089	0	0	0
T63	20460	0	0	0
T70	31534	0	0	0
T71	0	343	0	0
T74	996	0	0	0
T75	816	0	0	0
T76	1764	0	0	0
T77	23224	0	0	0
T78	1404	250	0	0
T79	8000	500	0	0
T80	11898	10606	0	0
T81	0	232	0	0
T82	0	231	0	0
T83	0	22377	0	0
T100	2017	0	0	0
T125	0	155	0	0
T133	0	280	0	0
T134	0	773	0	0
T135	421	0	0	0
T136	689	0	0	0
T137	495	0	0	0