Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T15,T32
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T51,T72,T57

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T51,T72,T57

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T51,T72,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T51,T56,T70
1	0	Covered	T48,T15,T32
1	1	Covered	T51,T72,T57

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T51,T57,T53
0	1	Covered	T72
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T51,T57,T53
0	1	Covered	T170,T171,T172
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T51,T57,T53
1	-	Covered	T170,T171,T172

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T51,T72,T57
0	1	Covered	T51,T72,T57
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T51,T72,T57
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T51,T72,T57
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T51,T72,T57
DebounceSt	-	0	1	0	-	-	-	Covered	T58,T167,T62
DebounceSt	-	0	0	-	-	-	-	Covered	T51,T72,T57
DetectSt	-	-	-	-	1	-	-	Covered	T72
DetectSt	-	-	-	-	0	1	-	Covered	T51,T57,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T53,T170,T171
StableSt	-	-	-	-	-	-	0	Covered	T51,T57,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	58	0	0
CntIncr_A	5743868	28261	0	0
CntNoWrap_A	5743868	5092793	0	0
DetectStDropOut_A	5743868	1	0	0
DetectedOut_A	5743868	1765	0	0
DetectedPulseOut_A	5743868	26	0	0
DisabledIdleSt_A	5743868	4993936	0	0
DisabledNoDetection_A	5743868	4996160	0	0
EnterDebounceSt_A	5743868	31	0	0
EnterDetectSt_A	5743868	27	0	0
EnterStableSt_A	5743868	26	0	0
PulseIsPulse_A	5743868	26	0	0
StayInStableSt	5743868	1721	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	6	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	58	0	0
T49	1274	0	0	0
T51	232339	4	0	0
T53	0	2	0	0
T55	550	0	0	0
T57	0	2	0	0
T58	0	1	0	0
T62	0	3	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T72	0	2	0	0
T77	11612	0	0	0
T91	0	2	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T167	0	1	0	0
T170	0	2	0	0
T171	0	2	0	0
T173	429	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	28261	0	0
T49	1274	0	0	0
T51	232339	154	0	0
T53	0	22	0	0
T55	550	0	0	0
T57	0	45	0	0
T58	0	76	0	0
T62	0	174	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T72	0	16	0	0
T77	11612	0	0	0
T91	0	58	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T167	0	50	0	0
T170	0	95	0	0
T171	0	84	0	0
T173	429	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092793	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1	0	0
T72	5062	1	0	0
T174	4077	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1765	0	0
T49	1274	0	0	0
T51	232339	101	0	0
T53	0	4	0	0
T55	550	0	0	0
T57	0	50	0	0
T62	0	158	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T91	0	44	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T164	0	66	0	0
T170	0	40	0	0
T171	0	170	0	0
T173	429	0	0	0
T175	0	41	0	0
T176	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	26	0	0
T49	1274	0	0	0
T51	232339	2	0	0
T53	0	1	0	0
T55	550	0	0	0
T57	0	1	0	0
T62	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T91	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T164	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T173	429	0	0	0
T175	0	1	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4993936	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4996160	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	31	0	0
T49	1274	0	0	0
T51	232339	2	0	0
T53	0	1	0	0
T55	550	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T62	0	2	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T72	0	1	0	0
T77	11612	0	0	0
T91	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T167	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T173	429	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	27	0	0
T49	1274	0	0	0
T51	232339	2	0	0
T53	0	1	0	0
T55	550	0	0	0
T57	0	1	0	0
T62	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T72	0	1	0	0
T77	11612	0	0	0
T91	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T170	0	1	0	0
T171	0	1	0	0
T173	429	0	0	0
T175	0	1	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	26	0	0
T49	1274	0	0	0
T51	232339	2	0	0
T53	0	1	0	0
T55	550	0	0	0
T57	0	1	0	0
T62	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T91	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T164	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T173	429	0	0	0
T175	0	1	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	26	0	0
T49	1274	0	0	0
T51	232339	2	0	0
T53	0	1	0	0
T55	550	0	0	0
T57	0	1	0	0
T62	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T91	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T164	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T173	429	0	0	0
T175	0	1	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1721	0	0
T49	1274	0	0	0
T51	232339	97	0	0
T53	0	3	0	0
T55	550	0	0	0
T57	0	48	0	0
T62	0	156	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T91	0	42	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T164	0	64	0	0
T170	0	39	0	0
T171	0	169	0	0
T173	429	0	0	0
T175	0	39	0	0
T176	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	6	0	0
T96	1517	0	0	0
T170	7470	1	0	0
T171	889	1	0	0
T172	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	572	0	0	0
T181	410	0	0	0
T182	9716	0	0	0
T183	18004	0	0	0
T184	15687	0	0	0
T185	1401	0	0	0
T186	21892	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T15,T32
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T23,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T17,T23,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T23,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T23,T51
1	0	Covered	T15,T32,T33
1	1	Covered	T17,T23,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T23,T51
0	1	Covered	T124
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T23,T51
0	1	Covered	T17,T23,T51
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T23,T51
1	-	Covered	T17,T23,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T23,T51
0	1	Covered	T17,T23,T51
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T23,T51
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T23,T51
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T23,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T164,T187
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T23,T51
DetectSt	-	-	-	-	1	-	-	Covered	T124
DetectSt	-	-	-	-	0	1	-	Covered	T17,T23,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T23,T51
StableSt	-	-	-	-	-	-	0	Covered	T17,T23,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	122	0	0
CntIncr_A	5743868	45901	0	0
CntNoWrap_A	5743868	5092729	0	0
DetectStDropOut_A	5743868	1	0	0
DetectedOut_A	5743868	76727	0	0
DetectedPulseOut_A	5743868	59	0	0
DisabledIdleSt_A	5743868	4847870	0	0
DisabledNoDetection_A	5743868	4850084	0	0
EnterDebounceSt_A	5743868	62	0	0
EnterDetectSt_A	5743868	60	0	0
EnterStableSt_A	5743868	59	0	0
PulseIsPulse_A	5743868	59	0	0
StayInStableSt	5743868	76645	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5743868	2912	0	0
gen_low_level_sva.LowLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	122	0	0
T17	9820	2	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	2	0	0
T51	0	6	0	0
T52	0	4	0	0
T53	0	2	0	0
T57	0	2	0	0
T63	10230	0	0	0
T71	0	4	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T82	0	2	0	0
T159	0	4	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	45901	0	0
T17	9820	71	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	87	0	0
T51	0	26937	0	0
T52	0	104	0	0
T53	0	22	0	0
T57	0	45	0	0
T63	10230	0	0	0
T71	0	162	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T82	0	81	0	0
T159	0	120	0	0
T188	0	15975	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092729	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1	0	0
T124	57370	1	0	0
T189	881	0	0	0
T190	512	0	0	0
T191	11661	0	0	0
T192	417	0	0	0
T193	648	0	0	0
T194	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	76727	0	0
T17	9820	111	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	127	0	0
T51	0	71832	0	0
T52	0	141	0	0
T53	0	3	0	0
T57	0	128	0	0
T63	10230	0	0	0
T71	0	105	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T82	0	130	0	0
T159	0	214	0	0
T188	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	59	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	0	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T71	0	2	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T82	0	1	0	0
T159	0	2	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4847870	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4850084	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	62	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	0	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T71	0	2	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T82	0	1	0	0
T159	0	2	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	60	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	0	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T71	0	2	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T82	0	1	0	0
T159	0	2	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	59	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	0	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T71	0	2	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T82	0	1	0	0
T159	0	2	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	59	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	1	0	0
T51	0	3	0	0
T52	0	2	0	0
T53	0	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T71	0	2	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T82	0	1	0	0
T159	0	2	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	76645	0	0
T17	9820	110	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	126	0	0
T51	0	71829	0	0
T52	0	138	0	0
T53	0	2	0	0
T57	0	127	0	0
T63	10230	0	0	0
T71	0	102	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T82	0	128	0	0
T159	0	211	0	0
T188	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	2912	0	0
T16	2477	4	0	0
T17	9820	5	0	0
T32	463	5	0	0
T33	437	4	0	0
T34	504	6	0	0
T35	6387	0	0	0
T36	1404	8	0	0
T37	421	2	0	0
T38	4966	0	0	0
T73	447	3	0	0
T74	0	6	0	0
T76	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	34	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	1	0	0
T51	0	3	0	0
T52	0	1	0	0
T54	0	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T71	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T167	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T32,T33

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T15,T32
1	0	Covered	T15,T32,T33
1	1	Covered	T15,T32,T33

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T23,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T17,T23,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T23,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T23,T51
1	0	Covered	T15,T32,T33
1	1	Covered	T17,T23,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T23,T51
0	1	Covered	T72,T195,T196
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T23,T51
0	1	Covered	T23,T51,T61
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T23,T51
1	-	Covered	T23,T51,T61

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T23,T51
0	1	Covered	T17,T23,T51
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T23,T51
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T23,T51
IdleSt	0	-	-	-	-	-	-	Covered	T15,T32,T33
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T23,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T175,T195,T92
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T23,T51
DetectSt	-	-	-	-	1	-	-	Covered	T72,T195,T196
DetectSt	-	-	-	-	0	1	-	Covered	T17,T23,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T51,T53
StableSt	-	-	-	-	-	-	0	Covered	T17,T23,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	136	0	0
CntIncr_A	5743868	83370	0	0
CntNoWrap_A	5743868	5092715	0	0
DetectStDropOut_A	5743868	4	0	0
DetectedOut_A	5743868	46670	0	0
DetectedPulseOut_A	5743868	62	0	0
DisabledIdleSt_A	5743868	4840889	0	0
DisabledNoDetection_A	5743868	4843103	0	0
EnterDebounceSt_A	5743868	70	0	0
EnterDetectSt_A	5743868	66	0	0
EnterStableSt_A	5743868	62	0	0
PulseIsPulse_A	5743868	62	0	0
StayInStableSt	5743868	46576	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	136	0	0
T17	9820	2	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	2	0	0
T51	0	8	0	0
T52	0	2	0	0
T53	0	2	0	0
T61	0	2	0	0
T63	10230	0	0	0
T70	0	2	0	0
T72	0	2	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	2	0	0
T95	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	83370	0	0
T17	9820	71	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	87	0	0
T51	0	53695	0	0
T52	0	52	0	0
T53	0	22	0	0
T61	0	70	0	0
T63	10230	0	0	0
T70	0	29	0	0
T72	0	16	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	66	0	0
T95	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092715	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4	0	0
T72	5062	1	0	0
T174	4077	0	0	0
T195	581	1	0	0
T196	1965	1	0	0
T197	0	1	0	0
T198	425	0	0	0
T199	683	0	0	0
T200	505	0	0	0
T201	502	0	0	0
T202	672	0	0	0
T203	3797	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	46670	0	0
T17	9820	304	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	44	0	0
T51	0	41851	0	0
T52	0	38	0	0
T53	0	3	0	0
T61	0	163	0	0
T63	10230	0	0	0
T70	0	40	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	118	0	0
T95	0	214	0	0
T167	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	62	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	1	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	1	0	0
T61	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	1	0	0
T95	0	1	0	0
T167	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4840889	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4843103	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	70	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	1	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	1	0	0
T61	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T72	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	1	0	0
T95	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	66	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	1	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	1	0	0
T61	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T72	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	1	0	0
T95	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	62	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	1	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	1	0	0
T61	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	1	0	0
T95	0	1	0	0
T167	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	62	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	1	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	1	0	0
T61	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	1	0	0
T95	0	1	0	0
T167	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	46576	0	0
T17	9820	302	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	43	0	0
T51	0	41846	0	0
T52	0	36	0	0
T53	0	2	0	0
T61	0	162	0	0
T63	10230	0	0	0
T70	0	38	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	116	0	0
T95	0	212	0	0
T167	0	84	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	28	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	3	0	0
T54	0	1	0	0
T55	550	0	0	0
T61	0	1	0	0
T69	5338	0	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T167	0	1	0	0
T168	0	1	0	0
T204	0	3	0	0
T205	0	2	0	0
T206	0	1	0	0
T207	0	1	0	0
T208	406	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T32,T33
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T32,T33
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T57,T53,T61

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T57,T53,T61

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T57,T53,T61

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T51,T59
1	0	Covered	T15,T32,T33
1	1	Covered	T57,T53,T61

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T57,T53,T61
0	1	Covered	T124,T179
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T57,T53,T61
0	1	Covered	T57,T54,T205
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T57,T53,T61
1	-	Covered	T57,T54,T205

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T57,T53,T61
0	1	Covered	T57,T53,T61
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T57,T53,T61
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T57,T53,T61
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T57,T53,T61
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T57,T53,T61
DetectSt	-	-	-	-	1	-	-	Covered	T124,T179
DetectSt	-	-	-	-	0	1	-	Covered	T57,T53,T61
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T57,T53,T54
StableSt	-	-	-	-	-	-	0	Covered	T57,T53,T61
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	54	0	0
CntIncr_A	5743868	27616	0	0
CntNoWrap_A	5743868	5092797	0	0
DetectStDropOut_A	5743868	2	0	0
DetectedOut_A	5743868	2102	0	0
DetectedPulseOut_A	5743868	25	0	0
DisabledIdleSt_A	5743868	4960215	0	0
DisabledNoDetection_A	5743868	4962432	0	0
EnterDebounceSt_A	5743868	27	0	0
EnterDetectSt_A	5743868	27	0	0
EnterStableSt_A	5743868	25	0	0
PulseIsPulse_A	5743868	25	0	0
StayInStableSt	5743868	2064	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5743868	6533	0	0
gen_low_level_sva.LowLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	54	0	0
T53	0	2	0	0
T54	0	2	0	0
T57	8461	2	0	0
T58	7700	0	0	0
T61	0	2	0	0
T87	8031	0	0	0
T110	7049	0	0	0
T162	0	2	0	0
T175	0	2	0	0
T205	0	4	0	0
T206	0	2	0	0
T209	0	2	0	0
T210	0	2	0	0
T211	503	0	0	0
T212	422	0	0	0
T213	405	0	0	0
T214	1916	0	0	0
T215	432	0	0	0
T216	790	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	27616	0	0
T53	0	22	0	0
T54	0	36	0	0
T57	8461	45	0	0
T58	7700	0	0	0
T61	0	70	0	0
T87	8031	0	0	0
T110	7049	0	0	0
T162	0	85	0	0
T175	0	26448	0	0
T205	0	72	0	0
T206	0	77	0	0
T209	0	11	0	0
T210	0	57	0	0
T211	503	0	0	0
T212	422	0	0	0
T213	405	0	0	0
T214	1916	0	0	0
T215	432	0	0	0
T216	790	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092797	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	2	0	0
T124	57370	1	0	0
T179	820	1	0	0
T189	881	0	0	0
T190	512	0	0	0
T191	11661	0	0	0
T192	417	0	0	0
T193	648	0	0	0
T194	404	0	0	0
T217	7575	0	0	0
T218	1833	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	2102	0	0
T53	0	4	0	0
T54	0	85	0	0
T57	8461	38	0	0
T58	7700	0	0	0
T61	0	43	0	0
T87	8031	0	0	0
T110	7049	0	0	0
T162	0	1	0	0
T175	0	41	0	0
T205	0	122	0	0
T206	0	137	0	0
T209	0	26	0	0
T210	0	55	0	0
T211	503	0	0	0
T212	422	0	0	0
T213	405	0	0	0
T214	1916	0	0	0
T215	432	0	0	0
T216	790	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	25	0	0
T53	0	1	0	0
T54	0	1	0	0
T57	8461	1	0	0
T58	7700	0	0	0
T61	0	1	0	0
T87	8031	0	0	0
T110	7049	0	0	0
T162	0	1	0	0
T175	0	1	0	0
T205	0	2	0	0
T206	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	503	0	0	0
T212	422	0	0	0
T213	405	0	0	0
T214	1916	0	0	0
T215	432	0	0	0
T216	790	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4960215	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4962432	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	27	0	0
T53	0	1	0	0
T54	0	1	0	0
T57	8461	1	0	0
T58	7700	0	0	0
T61	0	1	0	0
T87	8031	0	0	0
T110	7049	0	0	0
T162	0	1	0	0
T175	0	1	0	0
T205	0	2	0	0
T206	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	503	0	0	0
T212	422	0	0	0
T213	405	0	0	0
T214	1916	0	0	0
T215	432	0	0	0
T216	790	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	27	0	0
T53	0	1	0	0
T54	0	1	0	0
T57	8461	1	0	0
T58	7700	0	0	0
T61	0	1	0	0
T87	8031	0	0	0
T110	7049	0	0	0
T162	0	1	0	0
T175	0	1	0	0
T205	0	2	0	0
T206	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	503	0	0	0
T212	422	0	0	0
T213	405	0	0	0
T214	1916	0	0	0
T215	432	0	0	0
T216	790	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	25	0	0
T53	0	1	0	0
T54	0	1	0	0
T57	8461	1	0	0
T58	7700	0	0	0
T61	0	1	0	0
T87	8031	0	0	0
T110	7049	0	0	0
T162	0	1	0	0
T175	0	1	0	0
T205	0	2	0	0
T206	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	503	0	0	0
T212	422	0	0	0
T213	405	0	0	0
T214	1916	0	0	0
T215	432	0	0	0
T216	790	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	25	0	0
T53	0	1	0	0
T54	0	1	0	0
T57	8461	1	0	0
T58	7700	0	0	0
T61	0	1	0	0
T87	8031	0	0	0
T110	7049	0	0	0
T162	0	1	0	0
T175	0	1	0	0
T205	0	2	0	0
T206	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	503	0	0	0
T212	422	0	0	0
T213	405	0	0	0
T214	1916	0	0	0
T215	432	0	0	0
T216	790	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	2064	0	0
T53	0	3	0	0
T54	0	84	0	0
T57	8461	37	0	0
T58	7700	0	0	0
T61	0	41	0	0
T87	8031	0	0	0
T110	7049	0	0	0
T175	0	39	0	0
T205	0	120	0	0
T206	0	135	0	0
T209	0	24	0	0
T210	0	53	0	0
T211	503	0	0	0
T212	422	0	0	0
T213	405	0	0	0
T214	1916	0	0	0
T215	432	0	0	0
T216	790	0	0	0
T219	0	85	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	6533	0	0
T15	25917	12	0	0
T16	2477	4	0	0
T17	9820	13	0	0
T32	463	5	0	0
T33	437	4	0	0
T34	504	4	0	0
T35	6387	25	0	0
T36	1404	11	0	0
T37	421	2	0	0
T38	4966	23	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	10	0	0
T54	0	1	0	0
T57	8461	1	0	0
T58	7700	0	0	0
T87	8031	0	0	0
T110	7049	0	0	0
T124	0	1	0	0
T162	0	1	0	0
T179	0	1	0	0
T197	0	1	0	0
T205	0	2	0	0
T211	503	0	0	0
T212	422	0	0	0
T213	405	0	0	0
T214	1916	0	0	0
T215	432	0	0	0
T216	790	0	0	0
T219	0	1	0	0
T220	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T32,T33

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T15,T32
1	0	Covered	T15,T32,T33
1	1	Covered	T15,T32,T33

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T23,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T17,T23,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T23,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T23,T51
1	0	Covered	T15,T32,T33
1	1	Covered	T17,T23,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T23,T51
0	1	Covered	T221,T172
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T23,T51
0	1	Covered	T23,T70,T71
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T23,T51
1	-	Covered	T23,T70,T71

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T23,T51
0	1	Covered	T17,T23,T51
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T23,T51
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T23,T51
IdleSt	0	-	-	-	-	-	-	Covered	T15,T32,T33
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T23,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T188,T159,T61
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T23,T51
DetectSt	-	-	-	-	1	-	-	Covered	T221,T172
DetectSt	-	-	-	-	0	1	-	Covered	T17,T23,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T70,T71
StableSt	-	-	-	-	-	-	0	Covered	T17,T23,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	123	0	0
CntIncr_A	5743868	104109	0	0
CntNoWrap_A	5743868	5092728	0	0
DetectStDropOut_A	5743868	2	0	0
DetectedOut_A	5743868	54970	0	0
DetectedPulseOut_A	5743868	55	0	0
DisabledIdleSt_A	5743868	4761826	0	0
DisabledNoDetection_A	5743868	4764036	0	0
EnterDebounceSt_A	5743868	68	0	0
EnterDetectSt_A	5743868	57	0	0
EnterStableSt_A	5743868	55	0	0
PulseIsPulse_A	5743868	55	0	0
StayInStableSt	5743868	54895	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	123	0	0
T17	9820	2	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	4	0	0
T51	0	4	0	0
T55	0	2	0	0
T57	0	2	0	0
T63	10230	0	0	0
T70	0	2	0	0
T71	0	4	0	0
T72	0	2	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	2	0	0
T188	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	104109	0	0
T17	9820	71	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	174	0	0
T51	0	26855	0	0
T55	0	12	0	0
T57	0	88	0	0
T63	10230	0	0	0
T70	0	29	0	0
T71	0	162	0	0
T72	0	16	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	66	0	0
T169	0	4	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092728	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	2	0	0
T92	1991	0	0	0
T172	0	1	0	0
T221	807	1	0	0
T222	499	0	0	0
T223	483	0	0	0
T224	32210	0	0	0
T225	404	0	0	0
T226	501	0	0	0
T227	506	0	0	0
T228	958	0	0	0
T229	68268	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	54970	0	0
T17	9820	109	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	130	0	0
T51	0	50490	0	0
T53	0	4	0	0
T55	0	129	0	0
T57	0	145	0	0
T63	10230	0	0	0
T70	0	109	0	0
T71	0	174	0	0
T72	0	41	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	55	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	2	0	0
T51	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4761826	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4764036	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	68	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	2	0	0
T51	0	2	0	0
T55	0	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	1	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	57	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	2	0	0
T51	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	55	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	2	0	0
T51	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	55	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	2	0	0
T51	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	54895	0	0
T17	9820	107	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T23	0	127	0	0
T51	0	50486	0	0
T53	0	3	0	0
T55	0	127	0	0
T57	0	143	0	0
T63	10230	0	0	0
T70	0	108	0	0
T71	0	171	0	0
T72	0	40	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	33	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T55	550	0	0	0
T62	0	1	0	0
T69	5338	0	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T84	492	0	0	0
T90	627	0	0	0
T91	0	1	0	0
T95	0	1	0	0
T105	427	0	0	0
T106	445	0	0	0
T159	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T208	406	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T32,T33
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T32,T33
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T23,T59,T60

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T23,T59,T60

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T23,T59,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T23,T51,T55
1	0	Covered	T15,T32,T33
1	1	Covered	T23,T59,T60

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T59,T60
0	1	Covered	T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T59,T60
0	1	Covered	T23,T61,T54
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T59,T60
1	-	Covered	T23,T61,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T59,T60
0	1	Covered	T23,T59,T60
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T23,T59,T60
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T59,T60
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T59,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T71,T230
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T59,T60
DetectSt	-	-	-	-	1	-	-	Covered	T91
DetectSt	-	-	-	-	0	1	-	Covered	T23,T59,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T53,T61
StableSt	-	-	-	-	-	-	0	Covered	T23,T59,T60
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	84	0	0
CntIncr_A	5743868	18341	0	0
CntNoWrap_A	5743868	5092767	0	0
DetectStDropOut_A	5743868	1	0	0
DetectedOut_A	5743868	3455	0	0
DetectedPulseOut_A	5743868	40	0	0
DisabledIdleSt_A	5743868	4845302	0	0
DisabledNoDetection_A	5743868	4847514	0	0
EnterDebounceSt_A	5743868	43	0	0
EnterDetectSt_A	5743868	41	0	0
EnterStableSt_A	5743868	40	0	0
PulseIsPulse_A	5743868	40	0	0
StayInStableSt	5743868	3392	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5743868	6150	0	0
gen_low_level_sva.LowLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	84	0	0
T23	1684	2	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T53	0	2	0	0
T54	0	6	0	0
T55	550	0	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0
T69	5338	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T84	492	0	0	0
T90	627	0	0	0
T95	0	2	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	2	0	0
T208	406	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	18341	0	0
T23	1684	87	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T53	0	22	0	0
T54	0	108	0	0
T55	550	0	0	0
T59	0	73	0	0
T60	0	80	0	0
T61	0	70	0	0
T69	5338	0	0	0
T71	0	81	0	0
T72	0	16	0	0
T84	492	0	0	0
T90	627	0	0	0
T95	0	94	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	15975	0	0
T208	406	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092767	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1	0	0
T91	25600	1	0	0
T231	443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	3455	0	0
T23	1684	43	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T53	0	3	0	0
T54	0	120	0	0
T55	550	0	0	0
T59	0	165	0	0
T60	0	265	0	0
T61	0	162	0	0
T69	5338	0	0	0
T72	0	55	0	0
T84	492	0	0	0
T90	627	0	0	0
T95	0	42	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	46	0	0
T204	0	249	0	0
T208	406	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	40	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	550	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T69	5338	0	0	0
T72	0	1	0	0
T84	492	0	0	0
T90	627	0	0	0
T95	0	1	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	1	0	0
T204	0	1	0	0
T208	406	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4845302	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4847514	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	43	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	550	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T69	5338	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T84	492	0	0	0
T90	627	0	0	0
T95	0	1	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	1	0	0
T208	406	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	41	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	550	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T69	5338	0	0	0
T72	0	1	0	0
T84	492	0	0	0
T90	627	0	0	0
T95	0	1	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	1	0	0
T204	0	1	0	0
T208	406	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	40	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	550	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T69	5338	0	0	0
T72	0	1	0	0
T84	492	0	0	0
T90	627	0	0	0
T95	0	1	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	1	0	0
T204	0	1	0	0
T208	406	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	40	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	550	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T69	5338	0	0	0
T72	0	1	0	0
T84	492	0	0	0
T90	627	0	0	0
T95	0	1	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	1	0	0
T204	0	1	0	0
T208	406	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	3392	0	0
T23	1684	42	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T53	0	2	0	0
T54	0	116	0	0
T55	550	0	0	0
T59	0	163	0	0
T60	0	263	0	0
T61	0	161	0	0
T69	5338	0	0	0
T72	0	53	0	0
T84	492	0	0	0
T90	627	0	0	0
T95	0	40	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	44	0	0
T204	0	247	0	0
T208	406	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	6150	0	0
T15	25917	14	0	0
T16	2477	6	0	0
T17	9820	7	0	0
T32	463	6	0	0
T33	437	8	0	0
T34	504	4	0	0
T35	6387	36	0	0
T36	1404	10	0	0
T37	421	2	0	0
T38	4966	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	15	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	0	0	0
T54	0	2	0	0
T55	550	0	0	0
T61	0	1	0	0
T69	5338	0	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T170	0	2	0	0
T172	0	1	0	0
T205	0	1	0	0
T207	0	2	0	0
T208	406	0	0	0
T221	0	1	0	0
T232	0	1	0	0
T233	0	1	0	0