Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T32,T33

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T15,T32
1	0	Covered	T15,T32,T33
1	1	Covered	T15,T32,T33

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T23,T51,T60

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T23,T51,T60

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T23,T51,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T23,T51,T60
1	0	Covered	T15,T32,T33
1	1	Covered	T23,T51,T60

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T51,T60
0	1	Covered	T196
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T51,T60,T52
0	1	Covered	T23,T51,T60
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T51,T60,T52
1	-	Covered	T23,T51,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T51,T60
0	1	Covered	T23,T51,T60
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T23,T51,T60
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T51,T60
IdleSt	0	-	-	-	-	-	-	Covered	T15,T32,T33
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T51,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T23,T57,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T51,T60
DetectSt	-	-	-	-	1	-	-	Covered	T196
DetectSt	-	-	-	-	0	1	-	Covered	T23,T51,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T51,T60
StableSt	-	-	-	-	-	-	0	Covered	T51,T60,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	113	0	0
CntIncr_A	5743868	103282	0	0
CntNoWrap_A	5743868	5092738	0	0
DetectStDropOut_A	5743868	1	0	0
DetectedOut_A	5743868	3811	0	0
DetectedPulseOut_A	5743868	53	0	0
DisabledIdleSt_A	5743868	4770396	0	0
DisabledNoDetection_A	5743868	4772617	0	0
EnterDebounceSt_A	5743868	60	0	0
EnterDetectSt_A	5743868	54	0	0
EnterStableSt_A	5743868	53	0	0
PulseIsPulse_A	5743868	53	0	0
StayInStableSt	5743868	3739	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	113	0	0
T23	1684	3	0	0
T24	4149	0	0	0
T51	232339	6	0	0
T52	0	4	0	0
T53	0	2	0	0
T54	0	6	0	0
T55	550	0	0	0
T57	0	5	0	0
T58	0	1	0	0
T60	0	2	0	0
T61	0	3	0	0
T69	5338	0	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	2	0	0
T208	406	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	103282	0	0
T23	1684	174	0	0
T24	4149	0	0	0
T51	232339	26952	0	0
T52	0	104	0	0
T53	0	22	0	0
T54	0	108	0	0
T55	550	0	0	0
T57	0	178	0	0
T58	0	76	0	0
T60	0	80	0	0
T61	0	140	0	0
T69	5338	0	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	15975	0	0
T208	406	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092738	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1	0	0
T196	1965	1	0	0
T202	672	0	0	0
T203	3797	0	0	0
T234	666	0	0	0
T235	1796	0	0	0
T236	751	0	0	0
T237	768	0	0	0
T238	522	0	0	0
T239	1427	0	0	0
T240	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	3811	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	289	0	0
T52	0	140	0	0
T53	0	2	0	0
T54	0	166	0	0
T55	550	0	0	0
T57	0	184	0	0
T60	0	166	0	0
T61	0	166	0	0
T69	5338	0	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T160	0	51	0	0
T188	0	45	0	0
T208	406	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	53	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	3	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	550	0	0	0
T57	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T69	5338	0	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T160	0	2	0	0
T188	0	1	0	0
T208	406	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4770396	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4772617	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	60	0	0
T23	1684	2	0	0
T24	4149	0	0	0
T51	232339	3	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	550	0	0	0
T57	0	3	0	0
T58	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T69	5338	0	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	1	0	0
T208	406	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	54	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	3	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	550	0	0	0
T57	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T69	5338	0	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T160	0	2	0	0
T188	0	1	0	0
T208	406	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	53	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	3	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	550	0	0	0
T57	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T69	5338	0	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T160	0	2	0	0
T188	0	1	0	0
T208	406	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	53	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	3	0	0
T52	0	2	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	550	0	0	0
T57	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T69	5338	0	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T160	0	2	0	0
T188	0	1	0	0
T208	406	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	3739	0	0
T49	1274	0	0	0
T51	232339	285	0	0
T52	0	137	0	0
T53	0	1	0	0
T54	0	162	0	0
T55	550	0	0	0
T57	0	181	0	0
T60	0	165	0	0
T61	0	164	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T160	0	49	0	0
T173	429	0	0	0
T188	0	43	0	0
T209	0	98	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	32	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	2	0	0
T52	0	1	0	0
T54	0	2	0	0
T55	550	0	0	0
T57	0	1	0	0
T60	0	1	0	0
T69	5338	0	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T160	0	2	0	0
T206	0	1	0	0
T208	406	0	0	0
T209	0	3	0	0
T241	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T32,T33
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T32,T33
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T55,T57,T58

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T55,T57,T58

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T55,T57,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T55,T56,T169
1	0	Covered	T15,T32,T33
1	1	Covered	T55,T57,T58

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T55,T57,T58
0	1	Covered	T124
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T55,T57,T58
0	1	Covered	T57,T61,T54
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T55,T57,T58
1	-	Covered	T57,T61,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T55,T57,T58
0	1	Covered	T55,T57,T58
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T55,T57,T58
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T55,T57,T58
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T55,T57,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T62
DebounceSt	-	0	0	-	-	-	-	Covered	T55,T57,T58
DetectSt	-	-	-	-	1	-	-	Covered	T124
DetectSt	-	-	-	-	0	1	-	Covered	T55,T57,T58
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T57,T53,T61
StableSt	-	-	-	-	-	-	0	Covered	T55,T57,T58
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	91	0	0
CntIncr_A	5743868	2286	0	0
CntNoWrap_A	5743868	5092760	0	0
DetectStDropOut_A	5743868	1	0	0
DetectedOut_A	5743868	3706	0	0
DetectedPulseOut_A	5743868	44	0	0
DisabledIdleSt_A	5743868	4960484	0	0
DisabledNoDetection_A	5743868	4962701	0	0
EnterDebounceSt_A	5743868	46	0	0
EnterDetectSt_A	5743868	45	0	0
EnterStableSt_A	5743868	44	0	0
PulseIsPulse_A	5743868	44	0	0
StayInStableSt	5743868	3642	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5743868	6122	0	0
gen_low_level_sva.LowLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	91	0	0
T49	1274	0	0	0
T53	0	2	0	0
T54	0	4	0	0
T55	550	2	0	0
T57	8461	4	0	0
T58	0	2	0	0
T61	0	2	0	0
T62	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T91	0	2	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T173	429	0	0	0
T209	0	2	0	0
T210	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	2286	0	0
T49	1274	0	0	0
T53	0	22	0	0
T54	0	72	0	0
T55	550	12	0	0
T57	8461	90	0	0
T58	0	76	0	0
T61	0	70	0	0
T62	0	87	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T91	0	85	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T173	429	0	0	0
T209	0	11	0	0
T210	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092760	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1	0	0
T124	57370	1	0	0
T189	881	0	0	0
T190	512	0	0	0
T191	11661	0	0	0
T192	417	0	0	0
T193	648	0	0	0
T194	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	3706	0	0
T49	1274	0	0	0
T53	0	4	0	0
T54	0	8	0	0
T55	550	55	0	0
T57	8461	93	0	0
T58	0	38	0	0
T61	0	40	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T91	0	42	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T171	0	170	0	0
T173	429	0	0	0
T209	0	40	0	0
T210	0	55	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	44	0	0
T49	1274	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	550	1	0	0
T57	8461	2	0	0
T58	0	1	0	0
T61	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T91	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T171	0	1	0	0
T173	429	0	0	0
T209	0	1	0	0
T210	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4960484	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4962701	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	46	0	0
T49	1274	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	550	1	0	0
T57	8461	2	0	0
T58	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T91	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T173	429	0	0	0
T209	0	1	0	0
T210	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	45	0	0
T49	1274	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	550	1	0	0
T57	8461	2	0	0
T58	0	1	0	0
T61	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T91	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T171	0	1	0	0
T173	429	0	0	0
T209	0	1	0	0
T210	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	44	0	0
T49	1274	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	550	1	0	0
T57	8461	2	0	0
T58	0	1	0	0
T61	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T91	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T171	0	1	0	0
T173	429	0	0	0
T209	0	1	0	0
T210	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	44	0	0
T49	1274	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T55	550	1	0	0
T57	8461	2	0	0
T58	0	1	0	0
T61	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T91	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T171	0	1	0	0
T173	429	0	0	0
T209	0	1	0	0
T210	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	3642	0	0
T49	1274	0	0	0
T53	0	3	0	0
T54	0	6	0	0
T55	550	53	0	0
T57	8461	90	0	0
T58	0	36	0	0
T61	0	39	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T91	0	40	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T171	0	169	0	0
T173	429	0	0	0
T209	0	39	0	0
T210	0	53	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	6122	0	0
T15	25917	9	0	0
T16	2477	5	0	0
T17	9820	8	0	0
T32	463	7	0	0
T33	437	7	0	0
T34	504	5	0	0
T35	6387	24	0	0
T36	1404	11	0	0
T37	421	3	0	0
T38	4966	26	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	22	0	0
T54	0	2	0	0
T57	8461	1	0	0
T58	7700	0	0	0
T61	0	1	0	0
T87	8031	0	0	0
T110	7049	0	0	0
T163	0	1	0	0
T171	0	1	0	0
T195	0	1	0	0
T207	0	1	0	0
T209	0	1	0	0
T211	503	0	0	0
T212	422	0	0	0
T213	405	0	0	0
T214	1916	0	0	0
T215	432	0	0	0
T216	790	0	0	0
T219	0	1	0	0
T242	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T32,T33

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T15,T32
1	0	Covered	T15,T32,T33
1	1	Covered	T15,T32,T33

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T51,T55,T60

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T51,T55,T60

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T51,T55,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T51,T55,T60
1	0	Covered	T15,T32,T33
1	1	Covered	T51,T55,T60

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T51,T55,T60
0	1	Covered	T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T51,T55,T60
0	1	Covered	T51,T55,T60
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T51,T55,T60
1	-	Covered	T51,T55,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T51,T55,T60
0	1	Covered	T51,T55,T60
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T51,T55,T60
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T51,T55,T60
IdleSt	0	-	-	-	-	-	-	Covered	T15,T32,T33
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T51,T55,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T233,T243
DebounceSt	-	0	0	-	-	-	-	Covered	T51,T55,T60
DetectSt	-	-	-	-	1	-	-	Covered	T92
DetectSt	-	-	-	-	0	1	-	Covered	T51,T55,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T51,T55,T60
StableSt	-	-	-	-	-	-	0	Covered	T51,T55,T60
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	143	0	0
CntIncr_A	5743868	100087	0	0
CntNoWrap_A	5743868	5092708	0	0
DetectStDropOut_A	5743868	1	0	0
DetectedOut_A	5743868	67141	0	0
DetectedPulseOut_A	5743868	69	0	0
DisabledIdleSt_A	5743868	4803167	0	0
DisabledNoDetection_A	5743868	4805379	0	0
EnterDebounceSt_A	5743868	74	0	0
EnterDetectSt_A	5743868	70	0	0
EnterStableSt_A	5743868	69	0	0
PulseIsPulse_A	5743868	69	0	0
StayInStableSt	5743868	67044	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	143	0	0
T49	1274	0	0	0
T51	232339	7	0	0
T52	0	2	0	0
T53	0	2	0	0
T55	550	2	0	0
T60	0	4	0	0
T61	0	2	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T82	0	2	0	0
T107	429	0	0	0
T108	505	0	0	0
T133	0	2	0	0
T135	421	0	0	0
T159	0	4	0	0
T173	429	0	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	100087	0	0
T49	1274	0	0	0
T51	232339	80446	0	0
T52	0	52	0	0
T53	0	22	0	0
T55	550	12	0	0
T60	0	160	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T82	0	81	0	0
T107	429	0	0	0
T108	505	0	0	0
T133	0	11	0	0
T135	421	0	0	0
T159	0	120	0	0
T169	0	3	0	0
T173	429	0	0	0
T188	0	15975	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092708	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1	0	0
T92	1991	1	0	0
T224	32210	0	0	0
T225	404	0	0	0
T226	501	0	0	0
T227	506	0	0	0
T228	958	0	0	0
T229	68268	0	0	0
T244	503	0	0	0
T245	500	0	0	0
T246	500	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	67141	0	0
T49	1274	0	0	0
T51	232339	44859	0	0
T52	0	202	0	0
T53	0	3	0	0
T55	550	43	0	0
T60	0	273	0	0
T61	0	348	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T82	0	130	0	0
T107	429	0	0	0
T108	505	0	0	0
T133	0	65	0	0
T135	421	0	0	0
T159	0	142	0	0
T173	429	0	0	0
T188	0	16022	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	69	0	0
T49	1274	0	0	0
T51	232339	3	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	550	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T82	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T133	0	1	0	0
T135	421	0	0	0
T159	0	2	0	0
T173	429	0	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4803167	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4805379	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	74	0	0
T49	1274	0	0	0
T51	232339	4	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	550	1	0	0
T60	0	2	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T82	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T133	0	1	0	0
T135	421	0	0	0
T159	0	2	0	0
T169	0	1	0	0
T173	429	0	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	70	0	0
T49	1274	0	0	0
T51	232339	3	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	550	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T82	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T133	0	1	0	0
T135	421	0	0	0
T159	0	2	0	0
T173	429	0	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	69	0	0
T49	1274	0	0	0
T51	232339	3	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	550	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T82	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T133	0	1	0	0
T135	421	0	0	0
T159	0	2	0	0
T173	429	0	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	69	0	0
T49	1274	0	0	0
T51	232339	3	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	550	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T82	0	1	0	0
T107	429	0	0	0
T108	505	0	0	0
T133	0	1	0	0
T135	421	0	0	0
T159	0	2	0	0
T173	429	0	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	67044	0	0
T49	1274	0	0	0
T51	232339	44854	0	0
T52	0	200	0	0
T53	0	2	0	0
T55	550	42	0	0
T60	0	271	0	0
T61	0	346	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T82	0	128	0	0
T107	429	0	0	0
T108	505	0	0	0
T133	0	63	0	0
T135	421	0	0	0
T159	0	139	0	0
T173	429	0	0	0
T188	0	16020	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	39	0	0
T49	1274	0	0	0
T51	232339	1	0	0
T55	550	1	0	0
T60	0	2	0	0
T62	0	1	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T168	0	1	0	0
T173	429	0	0	0
T204	0	2	0	0
T205	0	3	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T32,T33
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T32,T33
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T55,T56

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T17,T55,T56

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T17,T55,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T51,T55
1	0	Covered	T15,T32,T33
1	1	Covered	T17,T55,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T55,T56
0	1	Covered	T172
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T55,T56
0	1	Covered	T159,T204,T207
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T55,T56
1	-	Covered	T159,T204,T207

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T55,T56
0	1	Covered	T17,T55,T56
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T55,T56
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T55,T56
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T55,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T247
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T55,T56
DetectSt	-	-	-	-	1	-	-	Covered	T172
DetectSt	-	-	-	-	0	1	-	Covered	T17,T55,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T53,T159,T204
StableSt	-	-	-	-	-	-	0	Covered	T17,T55,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	77	0	0
CntIncr_A	5743868	1951	0	0
CntNoWrap_A	5743868	5092774	0	0
DetectStDropOut_A	5743868	1	0	0
DetectedOut_A	5743868	3757	0	0
DetectedPulseOut_A	5743868	37	0	0
DisabledIdleSt_A	5743868	4990551	0	0
DisabledNoDetection_A	5743868	4992764	0	0
EnterDebounceSt_A	5743868	39	0	0
EnterDetectSt_A	5743868	38	0	0
EnterStableSt_A	5743868	37	0	0
PulseIsPulse_A	5743868	37	0	0
StayInStableSt	5743868	3698	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5743868	6110	0	0
gen_low_level_sva.LowLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	77	0	0
T17	9820	2	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T53	0	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T63	10230	0	0	0
T70	0	2	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T159	0	2	0	0
T160	0	2	0	0
T204	0	4	0	0
T206	0	2	0	0
T209	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1951	0	0
T17	9820	71	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T53	0	22	0	0
T55	0	12	0	0
T56	0	100	0	0
T63	10230	0	0	0
T70	0	29	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T159	0	60	0	0
T160	0	44	0	0
T204	0	124	0	0
T206	0	77	0	0
T209	0	11	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092774	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1	0	0
T172	24255	1	0	0
T177	772	0	0	0
T248	5321	0	0	0
T249	14366	0	0	0
T250	523	0	0	0
T251	860	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	3757	0	0
T17	9820	37	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T53	0	4	0	0
T55	0	54	0	0
T56	0	42	0	0
T63	10230	0	0	0
T70	0	79	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T159	0	136	0	0
T160	0	182	0	0
T204	0	86	0	0
T206	0	49	0	0
T209	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	37	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T204	0	2	0	0
T206	0	1	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4990551	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4992764	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	39	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T204	0	2	0	0
T206	0	1	0	0
T209	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	38	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T204	0	2	0	0
T206	0	1	0	0
T209	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	37	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T204	0	2	0	0
T206	0	1	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	37	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T63	10230	0	0	0
T70	0	1	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T204	0	2	0	0
T206	0	1	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	3698	0	0
T17	9820	35	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T53	0	3	0	0
T55	0	52	0	0
T56	0	40	0	0
T63	10230	0	0	0
T70	0	77	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T159	0	135	0	0
T160	0	180	0	0
T204	0	84	0	0
T206	0	47	0	0
T209	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	6110	0	0
T15	25917	14	0	0
T16	2477	5	0	0
T17	9820	7	0	0
T32	463	7	0	0
T33	437	5	0	0
T34	504	5	0	0
T35	6387	15	0	0
T36	1404	14	0	0
T37	421	2	0	0
T38	4966	32	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	13	0	0
T61	827	0	0	0
T92	0	1	0	0
T114	7070	0	0	0
T159	942	1	0	0
T161	0	1	0	0
T163	0	1	0	0
T165	0	1	0	0
T167	10171	0	0	0
T178	0	1	0	0
T196	0	1	0	0
T204	0	2	0	0
T207	0	1	0	0
T252	0	1	0	0
T253	981	0	0	0
T254	422	0	0	0
T255	23378	0	0	0
T256	556	0	0	0
T257	680	0	0	0
T258	510	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T32,T33

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T48,T15,T32
1	0	Covered	T15,T32,T33
1	1	Covered	T15,T32,T33

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T23,T51,T59

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T23,T51,T59

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T23,T51,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T23,T51,T56
1	0	Covered	T15,T32,T33
1	1	Covered	T23,T51,T59

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T51,T59
0	1	Covered	T58,T91,T230
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T51,T59
0	1	Covered	T23,T51,T60
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T51,T59
1	-	Covered	T23,T51,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T51,T59
0	1	Covered	T23,T51,T59
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T23,T51,T59
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T51,T59
IdleSt	0	-	-	-	-	-	-	Covered	T15,T32,T33
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T51,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T188,T221,T243
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T51,T59
DetectSt	-	-	-	-	1	-	-	Covered	T58,T91,T230
DetectSt	-	-	-	-	0	1	-	Covered	T23,T51,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T51,T60
StableSt	-	-	-	-	-	-	0	Covered	T23,T51,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	147	0	0
CntIncr_A	5743868	103905	0	0
CntNoWrap_A	5743868	5092704	0	0
DetectStDropOut_A	5743868	3	0	0
DetectedOut_A	5743868	5703	0	0
DetectedPulseOut_A	5743868	69	0	0
DisabledIdleSt_A	5743868	4844299	0	0
DisabledNoDetection_A	5743868	4846512	0	0
EnterDebounceSt_A	5743868	76	0	0
EnterDetectSt_A	5743868	72	0	0
EnterStableSt_A	5743868	69	0	0
PulseIsPulse_A	5743868	69	0	0
StayInStableSt	5743868	5608	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	41	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	147	0	0
T23	1684	2	0	0
T24	4149	0	0	0
T51	232339	10	0	0
T55	550	0	0	0
T57	0	2	0	0
T58	0	4	0	0
T59	0	2	0	0
T60	0	4	0	0
T69	5338	0	0	0
T70	0	2	0	0
T71	0	4	0	0
T82	0	2	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	1	0	0
T208	406	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	103905	0	0
T23	1684	87	0	0
T24	4149	0	0	0
T51	232339	80463	0	0
T55	550	0	0	0
T57	0	45	0	0
T58	0	152	0	0
T59	0	73	0	0
T60	0	160	0	0
T69	5338	0	0	0
T70	0	29	0	0
T71	0	162	0	0
T82	0	81	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	15975	0	0
T208	406	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092704	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	3	0	0
T58	7700	1	0	0
T87	8031	0	0	0
T91	0	1	0	0
T110	7049	0	0	0
T213	405	0	0	0
T214	1916	0	0	0
T215	432	0	0	0
T216	790	0	0	0
T230	0	1	0	0
T259	411	0	0	0
T260	494	0	0	0
T261	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5703	0	0
T23	1684	42	0	0
T24	4149	0	0	0
T51	232339	249	0	0
T53	0	3	0	0
T55	550	0	0	0
T57	0	225	0	0
T58	0	92	0	0
T59	0	48	0	0
T60	0	275	0	0
T69	5338	0	0	0
T70	0	108	0	0
T71	0	103	0	0
T82	0	131	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T208	406	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	69	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	5	0	0
T53	0	1	0	0
T55	550	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T69	5338	0	0	0
T70	0	1	0	0
T71	0	2	0	0
T82	0	1	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T208	406	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4844299	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4846512	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	76	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	5	0	0
T55	550	0	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	2	0	0
T69	5338	0	0	0
T70	0	1	0	0
T71	0	2	0	0
T82	0	1	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T188	0	1	0	0
T208	406	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	72	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	5	0	0
T53	0	1	0	0
T55	550	0	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T60	0	2	0	0
T69	5338	0	0	0
T70	0	1	0	0
T71	0	2	0	0
T82	0	1	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T208	406	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	69	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	5	0	0
T53	0	1	0	0
T55	550	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T69	5338	0	0	0
T70	0	1	0	0
T71	0	2	0	0
T82	0	1	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T208	406	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	69	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	5	0	0
T53	0	1	0	0
T55	550	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T69	5338	0	0	0
T70	0	1	0	0
T71	0	2	0	0
T82	0	1	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T208	406	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5608	0	0
T23	1684	41	0	0
T24	4149	0	0	0
T51	232339	242	0	0
T53	0	2	0	0
T55	550	0	0	0
T57	0	223	0	0
T58	0	90	0	0
T59	0	46	0	0
T60	0	273	0	0
T69	5338	0	0	0
T70	0	107	0	0
T71	0	101	0	0
T82	0	129	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T208	406	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	41	0	0
T23	1684	1	0	0
T24	4149	0	0	0
T51	232339	3	0	0
T55	550	0	0	0
T60	0	2	0	0
T62	0	1	0	0
T69	5338	0	0	0
T70	0	1	0	0
T71	0	2	0	0
T84	492	0	0	0
T90	627	0	0	0
T105	427	0	0	0
T106	445	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T204	0	1	0	0
T205	0	2	0	0
T208	406	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T32,T33
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T32,T33
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T51,T52,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T51,T52,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T51,T52,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T51,T55,T56
1	0	Covered	T15,T32,T33
1	1	Covered	T51,T52,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T51,T52,T53
0	1	Covered	T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T51,T52,T53
0	1	Covered	T51,T209,T205
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T51,T52,T53
1	-	Covered	T51,T209,T205

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T51,T52,T53
0	1	Covered	T51,T52,T53
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T51,T52,T53
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T51,T52,T53
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T51,T52,T53
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T51,T52,T53
DetectSt	-	-	-	-	1	-	-	Covered	T92
DetectSt	-	-	-	-	0	1	-	Covered	T51,T52,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T51,T53,T209
StableSt	-	-	-	-	-	-	0	Covered	T51,T52,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	94	0	0
CntIncr_A	5743868	2324	0	0
CntNoWrap_A	5743868	5092757	0	0
DetectStDropOut_A	5743868	1	0	0
DetectedOut_A	5743868	3324	0	0
DetectedPulseOut_A	5743868	46	0	0
DisabledIdleSt_A	5743868	5030051	0	0
DisabledNoDetection_A	5743868	5032262	0	0
EnterDebounceSt_A	5743868	47	0	0
EnterDetectSt_A	5743868	47	0	0
EnterStableSt_A	5743868	46	0	0
PulseIsPulse_A	5743868	46	0	0
StayInStableSt	5743868	3255	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5743868	6835	0	0
gen_low_level_sva.LowLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	94	0	0
T49	1274	0	0	0
T51	232339	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	550	0	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T160	0	2	0	0
T168	0	2	0	0
T170	0	4	0	0
T173	429	0	0	0
T204	0	2	0	0
T205	0	4	0	0
T209	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	2324	0	0
T49	1274	0	0	0
T51	232339	57	0	0
T52	0	52	0	0
T53	0	22	0	0
T54	0	36	0	0
T55	550	0	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T160	0	44	0	0
T168	0	64	0	0
T170	0	190	0	0
T173	429	0	0	0
T204	0	62	0	0
T205	0	72	0	0
T209	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092757	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1	0	0
T92	1991	1	0	0
T224	32210	0	0	0
T225	404	0	0	0
T226	501	0	0	0
T227	506	0	0	0
T228	958	0	0	0
T229	68268	0	0	0
T244	503	0	0	0
T245	500	0	0	0
T246	500	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	3324	0	0
T49	1274	0	0	0
T51	232339	47	0	0
T52	0	45	0	0
T53	0	4	0	0
T54	0	161	0	0
T55	550	0	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T160	0	94	0	0
T168	0	38	0	0
T170	0	86	0	0
T173	429	0	0	0
T204	0	143	0	0
T205	0	198	0	0
T209	0	73	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	46	0	0
T49	1274	0	0	0
T51	232339	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	550	0	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T160	0	1	0	0
T168	0	1	0	0
T170	0	2	0	0
T173	429	0	0	0
T204	0	1	0	0
T205	0	2	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5030051	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5032262	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	47	0	0
T49	1274	0	0	0
T51	232339	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	550	0	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T160	0	1	0	0
T168	0	1	0	0
T170	0	2	0	0
T173	429	0	0	0
T204	0	1	0	0
T205	0	2	0	0
T209	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	47	0	0
T49	1274	0	0	0
T51	232339	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	550	0	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T160	0	1	0	0
T168	0	1	0	0
T170	0	2	0	0
T173	429	0	0	0
T204	0	1	0	0
T205	0	2	0	0
T209	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	46	0	0
T49	1274	0	0	0
T51	232339	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	550	0	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T160	0	1	0	0
T168	0	1	0	0
T170	0	2	0	0
T173	429	0	0	0
T204	0	1	0	0
T205	0	2	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	46	0	0
T49	1274	0	0	0
T51	232339	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	550	0	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T160	0	1	0	0
T168	0	1	0	0
T170	0	2	0	0
T173	429	0	0	0
T204	0	1	0	0
T205	0	2	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	3255	0	0
T49	1274	0	0	0
T51	232339	46	0	0
T52	0	43	0	0
T53	0	3	0	0
T54	0	159	0	0
T55	550	0	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T160	0	92	0	0
T168	0	36	0	0
T170	0	83	0	0
T173	429	0	0	0
T204	0	141	0	0
T205	0	195	0	0
T209	0	72	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	6835	0	0
T15	25917	8	0	0
T16	2477	5	0	0
T17	9820	17	0	0
T32	463	3	0	0
T33	437	7	0	0
T34	504	5	0	0
T35	6387	26	0	0
T36	1404	12	0	0
T37	421	2	0	0
T38	4966	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	21	0	0
T49	1274	0	0	0
T51	232339	1	0	0
T55	550	0	0	0
T65	25743	0	0	0
T69	5338	0	0	0
T77	11612	0	0	0
T107	429	0	0	0
T108	505	0	0	0
T135	421	0	0	0
T170	0	1	0	0
T171	0	1	0	0
T173	429	0	0	0
T205	0	1	0	0
T207	0	1	0	0
T209	0	1	0	0
T219	0	1	0	0
T221	0	1	0	0
T232	0	1	0	0
T262	0	1	0	0