Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T35,T38,T20
1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T38,T20
1	0	Covered	T20,T63,T65
1	1	Covered	T35,T38,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T38,T20
0	1	Covered	T38,T65,T110
1	0	Covered	T65,T263,T110

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T20,T63
0	1	Covered	T35,T20,T63
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T20,T63
1	-	Covered	T35,T20,T63

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T38,T20
0	1	Covered	T35,T38,T20
0	0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T38,T20
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T35,T38,T20
IdleSt	0	-	-	-	-	-	-	Covered	T35,T38,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T38,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T264,T265
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T38,T20
DetectSt	-	-	-	-	1	-	-	Covered	T38,T65,T263
DetectSt	-	-	-	-	0	1	-	Covered	T35,T20,T63
DetectSt	-	-	-	-	0	0	-	Covered	T35,T38,T20
StableSt	-	-	-	-	-	-	1	Covered	T35,T20,T63
StableSt	-	-	-	-	-	-	0	Covered	T35,T20,T63
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	3191	0	0
CntIncr_A	5743868	104988	0	0
CntNoWrap_A	5743868	5089660	0	0
DetectStDropOut_A	5743868	315	0	0
DetectedOut_A	5743868	81706	0	0
DetectedPulseOut_A	5743868	1149	0	0
DisabledIdleSt_A	5743868	4654146	0	0
DisabledNoDetection_A	5743868	4656214	0	0
EnterDebounceSt_A	5743868	1611	0	0
EnterDetectSt_A	5743868	1581	0	0
EnterStableSt_A	5743868	1149	0	0
PulseIsPulse_A	5743868	1149	0	0
StayInStableSt	5743868	80449	0	0
gen_high_event_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	1041	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	3191	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	24	0	0
T35	6387	18	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	12	0	0
T63	0	50	0	0
T64	0	50	0	0
T65	0	36	0	0
T66	0	18	0	0
T73	447	0	0	0
T263	0	28	0	0
T266	0	14	0	0
T267	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	104988	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	972	0	0
T35	6387	459	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	277	0	0
T63	0	2250	0	0
T64	0	1475	0	0
T65	0	1445	0	0
T66	0	405	0	0
T73	447	0	0	0
T263	0	977	0	0
T266	0	280	0	0
T267	0	680	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5089660	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5968	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4553	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	315	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T38	4966	6	0	0
T63	10230	0	0	0
T65	0	10	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T110	0	11	0	0
T111	0	22	0	0
T112	0	21	0	0
T114	0	10	0	0
T115	0	10	0	0
T116	0	5	0	0
T117	0	5	0	0
T119	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	81706	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	1544	0	0
T35	6387	1212	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T53	0	325	0	0
T63	0	1100	0	0
T64	0	1802	0	0
T66	0	1320	0	0
T73	447	0	0	0
T266	0	525	0	0
T267	0	139	0	0
T268	0	1056	0	0
T269	0	936	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1149	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	12	0	0
T35	6387	9	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T53	0	5	0	0
T63	0	25	0	0
T64	0	25	0	0
T66	0	9	0	0
T73	447	0	0	0
T266	0	7	0	0
T267	0	10	0	0
T268	0	22	0	0
T269	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4654146	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	2015	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	2014	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4656214	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	2015	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	2014	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1611	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	12	0	0
T35	6387	9	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	6	0	0
T63	0	25	0	0
T64	0	25	0	0
T65	0	18	0	0
T66	0	9	0	0
T73	447	0	0	0
T263	0	14	0	0
T266	0	7	0	0
T267	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1581	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	12	0	0
T35	6387	9	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	6	0	0
T63	0	25	0	0
T64	0	25	0	0
T65	0	18	0	0
T66	0	9	0	0
T73	447	0	0	0
T263	0	14	0	0
T266	0	7	0	0
T267	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1149	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	12	0	0
T35	6387	9	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T53	0	5	0	0
T63	0	25	0	0
T64	0	25	0	0
T66	0	9	0	0
T73	447	0	0	0
T266	0	7	0	0
T267	0	10	0	0
T268	0	22	0	0
T269	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1149	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	12	0	0
T35	6387	9	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T53	0	5	0	0
T63	0	25	0	0
T64	0	25	0	0
T66	0	9	0	0
T73	447	0	0	0
T266	0	7	0	0
T267	0	10	0	0
T268	0	22	0	0
T269	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	80449	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	1526	0	0
T35	6387	1203	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T53	0	320	0	0
T63	0	1075	0	0
T64	0	1774	0	0
T66	0	1307	0	0
T73	447	0	0	0
T266	0	516	0	0
T267	0	129	0	0
T268	0	1031	0	0
T269	0	923	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1041	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	6	0	0
T35	6387	9	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T53	0	5	0	0
T63	0	25	0	0
T64	0	22	0	0
T66	0	5	0	0
T73	447	0	0	0
T266	0	5	0	0
T267	0	10	0	0
T268	0	19	0	0
T269	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T35,T16
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T35,T16
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T35,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T15,T35,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T16,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T35,T16
1	0	Covered	T15,T35,T16
1	1	Covered	T15,T35,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T17,T24,T83
1	0	Covered	T53,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T16,T17
1	0	Covered	T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T16,T17
1	-	Covered	T15,T16,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T35,T16
0	1	Covered	T15,T35,T16
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T35,T16
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T16,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T35,T17
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T35,T16
DetectSt	-	-	-	-	1	-	-	Covered	T17,T24,T83
DetectSt	-	-	-	-	0	1	-	Covered	T15,T16,T17
DetectSt	-	-	-	-	0	0	-	Covered	T15,T16,T17
StableSt	-	-	-	-	-	-	1	Covered	T15,T16,T17
StableSt	-	-	-	-	-	-	0	Covered	T15,T16,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	939	0	0
CntIncr_A	5743868	46576	0	0
CntNoWrap_A	5743868	5091912	0	0
DetectStDropOut_A	5743868	29	0	0
DetectedOut_A	5743868	13735	0	0
DetectedPulseOut_A	5743868	393	0	0
DisabledIdleSt_A	5743868	4717534	0	0
DisabledNoDetection_A	5743868	4719106	0	0
EnterDebounceSt_A	5743868	515	0	0
EnterDetectSt_A	5743868	427	0	0
EnterStableSt_A	5743868	393	0	0
PulseIsPulse_A	5743868	393	0	0
StayInStableSt	5743868	13324	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	370	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	939	0	0
T15	25917	14	0	0
T16	2477	2	0	0
T17	9820	5	0	0
T19	0	24	0	0
T20	0	6	0	0
T21	0	8	0	0
T22	0	27	0	0
T24	0	2	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	1	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	46576	0	0
T15	25917	804	0	0
T16	2477	25	0	0
T17	9820	177	0	0
T19	0	2044	0	0
T20	0	213	0	0
T21	0	244	0	0
T22	0	2127	0	0
T24	0	43	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	23	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5091912	0	0
T15	25917	25441	0	0
T16	2477	212	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5985	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	29	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T24	0	1	0	0
T63	10230	0	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	5	0	0
T91	0	1	0	0
T113	0	5	0	0
T118	0	1	0	0
T120	0	5	0	0
T121	0	3	0	0
T122	0	2	0	0
T124	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	13735	0	0
T15	25917	97	0	0
T16	2477	3	0	0
T17	9820	3	0	0
T19	0	183	0	0
T20	0	157	0	0
T21	0	154	0	0
T22	0	257	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	6	0	0
T69	0	31	0	0
T77	0	21	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	393	0	0
T15	25917	6	0	0
T16	2477	1	0	0
T17	9820	1	0	0
T19	0	11	0	0
T20	0	3	0	0
T21	0	4	0	0
T22	0	12	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	2	0	0
T69	0	5	0	0
T77	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4717534	0	0
T15	25917	20145	0	0
T16	2477	127	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	4774	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4719106	0	0
T15	25917	20145	0	0
T16	2477	131	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	4775	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	515	0	0
T15	25917	8	0	0
T16	2477	1	0	0
T17	9820	3	0	0
T19	0	13	0	0
T20	0	3	0	0
T21	0	4	0	0
T22	0	15	0	0
T24	0	1	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	1	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	427	0	0
T15	25917	6	0	0
T16	2477	1	0	0
T17	9820	2	0	0
T19	0	11	0	0
T20	0	3	0	0
T21	0	4	0	0
T22	0	12	0	0
T24	0	1	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	2	0	0
T69	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	393	0	0
T15	25917	6	0	0
T16	2477	1	0	0
T17	9820	1	0	0
T19	0	11	0	0
T20	0	3	0	0
T21	0	4	0	0
T22	0	12	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	2	0	0
T69	0	5	0	0
T77	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	393	0	0
T15	25917	6	0	0
T16	2477	1	0	0
T17	9820	1	0	0
T19	0	11	0	0
T20	0	3	0	0
T21	0	4	0	0
T22	0	12	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	2	0	0
T69	0	5	0	0
T77	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	13324	0	0
T15	25917	91	0	0
T16	2477	2	0	0
T17	9820	2	0	0
T19	0	172	0	0
T20	0	151	0	0
T21	0	150	0	0
T22	0	245	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	4	0	0
T69	0	26	0	0
T77	0	19	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	370	0	0
T15	25917	6	0	0
T16	2477	1	0	0
T17	9820	1	0	0
T19	0	11	0	0
T21	0	4	0	0
T22	0	12	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	2	0	0
T69	0	5	0	0
T77	0	2	0	0
T101	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T35,T38,T20
1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T38,T20
1	0	Covered	T35,T20,T63
1	1	Covered	T35,T38,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T38,T20
0	1	Covered	T35,T38,T65
1	0	Covered	T35,T65,T66

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T63,T64
0	1	Covered	T20,T63,T64
1	0	Covered	T53,T93,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T63,T64
1	-	Covered	T20,T63,T64

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T38,T20
0	1	Covered	T35,T38,T20
0	0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T38,T20
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T35,T38,T20
IdleSt	0	-	-	-	-	-	-	Covered	T35,T38,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T38,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T264,T265
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T38,T20
DetectSt	-	-	-	-	1	-	-	Covered	T35,T38,T65
DetectSt	-	-	-	-	0	1	-	Covered	T20,T63,T64
DetectSt	-	-	-	-	0	0	-	Covered	T35,T38,T20
StableSt	-	-	-	-	-	-	1	Covered	T20,T63,T64
StableSt	-	-	-	-	-	-	0	Covered	T20,T63,T64
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	2899	0	0
CntIncr_A	5743868	103362	0	0
CntNoWrap_A	5743868	5089952	0	0
DetectStDropOut_A	5743868	301	0	0
DetectedOut_A	5743868	63008	0	0
DetectedPulseOut_A	5743868	916	0	0
DisabledIdleSt_A	5743868	4666950	0	0
DisabledNoDetection_A	5743868	4669044	0	0
EnterDebounceSt_A	5743868	1471	0	0
EnterDetectSt_A	5743868	1432	0	0
EnterStableSt_A	5743868	916	0	0
PulseIsPulse_A	5743868	916	0	0
StayInStableSt	5743868	62010	0	0
gen_high_event_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	814	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	2899	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	26	0	0
T35	6387	20	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	34	0	0
T63	0	10	0	0
T64	0	56	0	0
T65	0	52	0	0
T66	0	24	0	0
T73	447	0	0	0
T263	0	28	0	0
T266	0	26	0	0
T267	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	103362	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	884	0	0
T35	6387	511	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	791	0	0
T63	0	395	0	0
T64	0	1876	0	0
T65	0	2094	0	0
T66	0	618	0	0
T73	447	0	0	0
T263	0	970	0	0
T266	0	713	0	0
T267	0	420	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5089952	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5966	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4531	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	301	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T35	6387	6	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	17	0	0
T53	0	1	0	0
T65	0	14	0	0
T66	0	5	0	0
T73	447	0	0	0
T111	0	12	0	0
T112	0	9	0	0
T263	0	7	0	0
T269	0	2	0	0
T270	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	63008	0	0
T20	33590	2580	0	0
T21	7670	0	0	0
T53	0	348	0	0
T63	10230	205	0	0
T64	24353	3437	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T109	9297	0	0	0
T110	0	329	0	0
T114	0	1662	0	0
T264	0	83	0	0
T267	0	546	0	0
T268	0	2499	0	0
T271	0	52	0	0
T272	422	0	0	0
T273	423	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	916	0	0
T20	33590	13	0	0
T21	7670	0	0	0
T53	0	5	0	0
T63	10230	5	0	0
T64	24353	28	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T109	9297	0	0	0
T110	0	17	0	0
T114	0	30	0	0
T264	0	7	0	0
T267	0	10	0	0
T268	0	24	0	0
T271	0	14	0	0
T272	422	0	0	0
T273	423	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4666950	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	3234	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	2014	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4669044	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	3234	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	2014	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1471	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	13	0	0
T35	6387	10	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	17	0	0
T63	0	5	0	0
T64	0	28	0	0
T65	0	26	0	0
T66	0	12	0	0
T73	447	0	0	0
T263	0	14	0	0
T266	0	13	0	0
T267	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1432	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	13	0	0
T35	6387	10	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	17	0	0
T63	0	5	0	0
T64	0	28	0	0
T65	0	26	0	0
T66	0	12	0	0
T73	447	0	0	0
T263	0	14	0	0
T266	0	13	0	0
T267	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	916	0	0
T20	33590	13	0	0
T21	7670	0	0	0
T53	0	5	0	0
T63	10230	5	0	0
T64	24353	28	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T109	9297	0	0	0
T110	0	17	0	0
T114	0	30	0	0
T264	0	7	0	0
T267	0	10	0	0
T268	0	24	0	0
T271	0	14	0	0
T272	422	0	0	0
T273	423	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	916	0	0
T20	33590	13	0	0
T21	7670	0	0	0
T53	0	5	0	0
T63	10230	5	0	0
T64	24353	28	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T109	9297	0	0	0
T110	0	17	0	0
T114	0	30	0	0
T264	0	7	0	0
T267	0	10	0	0
T268	0	24	0	0
T271	0	14	0	0
T272	422	0	0	0
T273	423	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	62010	0	0
T20	33590	2559	0	0
T21	7670	0	0	0
T53	0	343	0	0
T63	10230	200	0	0
T64	24353	3402	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T109	9297	0	0	0
T110	0	312	0	0
T114	0	1632	0	0
T264	0	76	0	0
T267	0	535	0	0
T268	0	2469	0	0
T271	0	38	0	0
T272	422	0	0	0
T273	423	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	814	0	0
T20	33590	5	0	0
T21	7670	0	0	0
T53	0	4	0	0
T63	10230	5	0	0
T64	24353	21	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T109	9297	0	0	0
T110	0	17	0	0
T114	0	30	0	0
T264	0	7	0	0
T267	0	9	0	0
T268	0	18	0	0
T271	0	14	0	0
T272	422	0	0	0
T273	423	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T35,T38
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T35,T38
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T15,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T17,T19
1	0	Covered	T15,T35,T16
1	1	Covered	T15,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T19,T20
0	1	Covered	T95,T274,T120
1	0	Covered	T53,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T19,T20
0	1	Covered	T15,T19,T20
1	0	Covered	T53,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T19,T20
1	-	Covered	T15,T19,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T19,T20
0	1	Covered	T15,T19,T20
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T19,T20
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T19,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T51,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T53,T95,T274
DetectSt	-	-	-	-	0	1	-	Covered	T15,T19,T20
DetectSt	-	-	-	-	0	0	-	Covered	T15,T19,T20
StableSt	-	-	-	-	-	-	1	Covered	T15,T19,T20
StableSt	-	-	-	-	-	-	0	Covered	T15,T19,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	735	0	0
CntIncr_A	5743868	38139	0	0
CntNoWrap_A	5743868	5092116	0	0
DetectStDropOut_A	5743868	38	0	0
DetectedOut_A	5743868	14096	0	0
DetectedPulseOut_A	5743868	305	0	0
DisabledIdleSt_A	5743868	4733271	0	0
DisabledNoDetection_A	5743868	4734910	0	0
EnterDebounceSt_A	5743868	389	0	0
EnterDetectSt_A	5743868	348	0	0
EnterStableSt_A	5743868	305	0	0
PulseIsPulse_A	5743868	305	0	0
StayInStableSt	5743868	13773	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	285	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	735	0	0
T15	25917	8	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	12	0	0
T20	0	14	0	0
T21	0	2	0	0
T22	0	13	0	0
T24	0	10	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	7	0	0
T59	0	3	0	0
T70	0	2	0	0
T77	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	38139	0	0
T15	25917	472	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	648	0	0
T20	0	462	0	0
T21	0	74	0	0
T22	0	1075	0	0
T24	0	190	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	351	0	0
T59	0	137	0	0
T70	0	109	0	0
T77	0	250	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092116	0	0
T15	25917	25447	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	38	0	0
T95	29444	1	0	0
T113	15750	0	0	0
T120	0	2	0	0
T121	0	1	0	0
T122	0	6	0	0
T125	1518	0	0	0
T126	502	0	0	0
T158	199194	0	0	0
T242	0	4	0	0
T274	7203	2	0	0
T275	0	2	0	0
T276	0	13	0	0
T277	0	2	0	0
T278	0	3	0	0
T279	402	0	0	0
T280	406	0	0	0
T281	6088	0	0	0
T282	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	14096	0	0
T15	25917	47	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	459	0	0
T20	0	412	0	0
T21	0	24	0	0
T22	0	66	0	0
T24	0	22	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	233	0	0
T59	0	23	0	0
T70	0	23	0	0
T77	0	129	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	305	0	0
T15	25917	4	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	6	0	0
T20	0	7	0	0
T21	0	1	0	0
T22	0	6	0	0
T24	0	5	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	3	0	0
T59	0	1	0	0
T70	0	1	0	0
T77	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4733271	0	0
T15	25917	20145	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4734910	0	0
T15	25917	20145	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	389	0	0
T15	25917	4	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	6	0	0
T20	0	7	0	0
T21	0	1	0	0
T22	0	7	0	0
T24	0	5	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	4	0	0
T59	0	2	0	0
T70	0	1	0	0
T77	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	348	0	0
T15	25917	4	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	6	0	0
T20	0	7	0	0
T21	0	1	0	0
T22	0	6	0	0
T24	0	5	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	3	0	0
T59	0	1	0	0
T70	0	1	0	0
T77	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	305	0	0
T15	25917	4	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	6	0	0
T20	0	7	0	0
T21	0	1	0	0
T22	0	6	0	0
T24	0	5	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	3	0	0
T59	0	1	0	0
T70	0	1	0	0
T77	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	305	0	0
T15	25917	4	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	6	0	0
T20	0	7	0	0
T21	0	1	0	0
T22	0	6	0	0
T24	0	5	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	3	0	0
T59	0	1	0	0
T70	0	1	0	0
T77	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	13773	0	0
T15	25917	43	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	453	0	0
T20	0	405	0	0
T21	0	23	0	0
T22	0	60	0	0
T24	0	17	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	230	0	0
T59	0	22	0	0
T70	0	22	0	0
T77	0	127	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	285	0	0
T15	25917	4	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	6	0	0
T20	0	7	0	0
T21	0	1	0	0
T22	0	6	0	0
T24	0	5	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	3	0	0
T59	0	1	0	0
T70	0	1	0	0
T77	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T35,T38,T20
1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T38,T20
1	0	Covered	T35,T20,T63
1	1	Covered	T35,T38,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T38,T20
0	1	Covered	T35,T38,T111
1	0	Covered	T35,T266,T269

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T63,T65
0	1	Covered	T20,T63,T65
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T63,T65
1	-	Covered	T20,T63,T65

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T38,T20
0	1	Covered	T35,T38,T20
0	0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T38,T20
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T35,T38,T20
IdleSt	0	-	-	-	-	-	-	Covered	T35,T38,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T38,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T264,T265
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T38,T20
DetectSt	-	-	-	-	1	-	-	Covered	T35,T38,T266
DetectSt	-	-	-	-	0	1	-	Covered	T20,T63,T65
DetectSt	-	-	-	-	0	0	-	Covered	T35,T38,T20
StableSt	-	-	-	-	-	-	1	Covered	T20,T63,T65
StableSt	-	-	-	-	-	-	0	Covered	T20,T63,T65
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	3009	0	0
CntIncr_A	5743868	105423	0	0
CntNoWrap_A	5743868	5089842	0	0
DetectStDropOut_A	5743868	318	0	0
DetectedOut_A	5743868	78502	0	0
DetectedPulseOut_A	5743868	911	0	0
DisabledIdleSt_A	5743868	4655476	0	0
DisabledNoDetection_A	5743868	4657549	0	0
EnterDebounceSt_A	5743868	1524	0	0
EnterDetectSt_A	5743868	1485	0	0
EnterStableSt_A	5743868	911	0	0
PulseIsPulse_A	5743868	911	0	0
StayInStableSt	5743868	77487	0	0
gen_high_event_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	806	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	3009	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	8	0	0
T35	6387	22	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	52	0	0
T63	0	10	0	0
T64	0	64	0	0
T65	0	14	0	0
T66	0	10	0	0
T73	447	0	0	0
T263	0	26	0	0
T266	0	2	0	0
T267	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	105423	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	292	0	0
T35	6387	565	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	1223	0	0
T63	0	440	0	0
T64	0	3136	0	0
T65	0	441	0	0
T66	0	170	0	0
T73	447	0	0	0
T263	0	806	0	0
T266	0	55	0	0
T267	0	546	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5089842	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5964	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4513	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	318	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T35	6387	5	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	26	0	0
T53	0	1	0	0
T73	447	0	0	0
T93	0	12	0	0
T111	0	5	0	0
T112	0	3	0	0
T115	0	10	0	0
T119	0	10	0	0
T269	0	14	0	0
T283	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	78502	0	0
T20	33590	641	0	0
T21	7670	0	0	0
T49	1274	0	0	0
T53	0	404	0	0
T63	10230	160	0	0
T64	0	1135	0	0
T65	25743	786	0	0
T66	0	326	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T110	0	86	0	0
T173	429	0	0	0
T263	0	1465	0	0
T267	0	962	0	0
T268	0	1012	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	911	0	0
T20	33590	4	0	0
T21	7670	0	0	0
T49	1274	0	0	0
T53	0	5	0	0
T63	10230	5	0	0
T64	0	32	0	0
T65	25743	7	0	0
T66	0	5	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T110	0	5	0	0
T173	429	0	0	0
T263	0	13	0	0
T267	0	13	0	0
T268	0	22	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4655476	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	3234	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	2014	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4657549	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	3234	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	2014	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1524	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	4	0	0
T35	6387	11	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	26	0	0
T63	0	5	0	0
T64	0	32	0	0
T65	0	7	0	0
T66	0	5	0	0
T73	447	0	0	0
T263	0	13	0	0
T266	0	1	0	0
T267	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1485	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	4	0	0
T35	6387	11	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	26	0	0
T63	0	5	0	0
T64	0	32	0	0
T65	0	7	0	0
T66	0	5	0	0
T73	447	0	0	0
T263	0	13	0	0
T266	0	1	0	0
T267	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	911	0	0
T20	33590	4	0	0
T21	7670	0	0	0
T49	1274	0	0	0
T53	0	5	0	0
T63	10230	5	0	0
T64	0	32	0	0
T65	25743	7	0	0
T66	0	5	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T110	0	5	0	0
T173	429	0	0	0
T263	0	13	0	0
T267	0	13	0	0
T268	0	22	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	911	0	0
T20	33590	4	0	0
T21	7670	0	0	0
T49	1274	0	0	0
T53	0	5	0	0
T63	10230	5	0	0
T64	0	32	0	0
T65	25743	7	0	0
T66	0	5	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T110	0	5	0	0
T173	429	0	0	0
T263	0	13	0	0
T267	0	13	0	0
T268	0	22	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	77487	0	0
T20	33590	635	0	0
T21	7670	0	0	0
T49	1274	0	0	0
T53	0	399	0	0
T63	10230	155	0	0
T64	0	1101	0	0
T65	25743	777	0	0
T66	0	319	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T110	0	81	0	0
T173	429	0	0	0
T263	0	1452	0	0
T267	0	947	0	0
T268	0	987	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	806	0	0
T20	33590	2	0	0
T21	7670	0	0	0
T49	1274	0	0	0
T53	0	4	0	0
T63	10230	5	0	0
T64	0	30	0	0
T65	25743	5	0	0
T66	0	3	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T77	11612	0	0	0
T110	0	5	0	0
T173	429	0	0	0
T263	0	13	0	0
T267	0	11	0	0
T268	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T35,T38
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T35,T38
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T17,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T15,T17,T19

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T17,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T17,T19
1	0	Covered	T15,T35,T16
1	1	Covered	T15,T17,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T17,T19
0	1	Covered	T17,T24,T133
1	0	Covered	T53,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T19,T20
0	1	Covered	T15,T19,T20
1	0	Covered	T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T19,T20
1	-	Covered	T15,T19,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T17,T19
0	1	Covered	T15,T17,T19
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T17,T19
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T17,T19
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T17,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T19,T22
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T17,T19
DetectSt	-	-	-	-	1	-	-	Covered	T17,T24,T133
DetectSt	-	-	-	-	0	1	-	Covered	T15,T19,T20
DetectSt	-	-	-	-	0	0	-	Covered	T15,T17,T19
StableSt	-	-	-	-	-	-	1	Covered	T15,T19,T20
StableSt	-	-	-	-	-	-	0	Covered	T15,T19,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	846	0	0
CntIncr_A	5743868	45336	0	0
CntNoWrap_A	5743868	5092005	0	0
DetectStDropOut_A	5743868	62	0	0
DetectedOut_A	5743868	14424	0	0
DetectedPulseOut_A	5743868	328	0	0
DisabledIdleSt_A	5743868	4713010	0	0
DisabledNoDetection_A	5743868	4714618	0	0
EnterDebounceSt_A	5743868	453	0	0
EnterDetectSt_A	5743868	394	0	0
EnterStableSt_A	5743868	328	0	0
PulseIsPulse_A	5743868	328	0	0
StayInStableSt	5743868	14063	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	293	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	846	0	0
T15	25917	5	0	0
T16	2477	0	0	0
T17	9820	2	0	0
T19	0	7	0	0
T20	0	4	0	0
T22	0	13	0	0
T24	0	6	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	2	0	0
T65	0	4	0	0
T69	0	5	0	0
T77	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	45336	0	0
T15	25917	285	0	0
T16	2477	0	0	0
T17	9820	133	0	0
T19	0	575	0	0
T20	0	156	0	0
T22	0	1075	0	0
T24	0	136	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	107	0	0
T65	0	180	0	0
T69	0	181	0	0
T77	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092005	0	0
T15	25917	25450	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	62	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	0	0	0
T21	7670	0	0	0
T24	0	2	0	0
T63	10230	0	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T95	0	3	0	0
T133	0	1	0	0
T145	0	7	0	0
T175	0	5	0	0
T209	0	8	0	0
T241	0	1	0	0
T284	0	4	0	0
T285	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	14424	0	0
T15	25917	36	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	75	0	0
T20	0	95	0	0
T22	0	66	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	64	0	0
T59	0	327	0	0
T65	0	131	0	0
T66	0	74	0	0
T69	0	12	0	0
T70	0	65	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	328	0	0
T15	25917	2	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	3	0	0
T20	0	2	0	0
T22	0	6	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	1	0	0
T59	0	8	0	0
T65	0	2	0	0
T66	0	1	0	0
T69	0	2	0	0
T70	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4713010	0	0
T15	25917	20145	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4714618	0	0
T15	25917	20145	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	453	0	0
T15	25917	3	0	0
T16	2477	0	0	0
T17	9820	1	0	0
T19	0	4	0	0
T20	0	2	0	0
T22	0	7	0	0
T24	0	4	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	1	0	0
T65	0	2	0	0
T69	0	3	0	0
T77	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	394	0	0
T15	25917	2	0	0
T16	2477	0	0	0
T17	9820	1	0	0
T19	0	3	0	0
T20	0	2	0	0
T22	0	6	0	0
T24	0	2	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	1	0	0
T65	0	2	0	0
T66	0	1	0	0
T69	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	328	0	0
T15	25917	2	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	3	0	0
T20	0	2	0	0
T22	0	6	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	1	0	0
T59	0	8	0	0
T65	0	2	0	0
T66	0	1	0	0
T69	0	2	0	0
T70	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	328	0	0
T15	25917	2	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	3	0	0
T20	0	2	0	0
T22	0	6	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	1	0	0
T59	0	8	0	0
T65	0	2	0	0
T66	0	1	0	0
T69	0	2	0	0
T70	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	14063	0	0
T15	25917	34	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	72	0	0
T20	0	93	0	0
T22	0	60	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	63	0	0
T59	0	319	0	0
T65	0	129	0	0
T66	0	73	0	0
T69	0	10	0	0
T70	0	60	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	293	0	0
T15	25917	2	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T19	0	3	0	0
T20	0	2	0	0
T22	0	6	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	1	0	0
T59	0	8	0	0
T65	0	2	0	0
T66	0	1	0	0
T69	0	2	0	0
T70	0	5	0	0